Searched refs:CFG_SYS_SDRAM_BASE (Results 251 - 275 of 556) sorted by relevance

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/u-boot/include/configs/
H A Dverdin-am62.h15 #define CFG_SYS_SDRAM_BASE 0x80000000 macro
H A Dcolibri-imx8x.h49 #define CFG_SYS_SDRAM_BASE 0x80000000 macro
H A DM5373EVB.h63 * Please note that CFG_SYS_SDRAM_BASE _must_ start at 0
65 #define CFG_SYS_SDRAM_BASE 0x40000000 macro
78 #define CFG_SYS_BOOTMAPSZ (CFG_SYS_SDRAM_BASE + (CFG_SYS_SDRAM_SIZE << 20))
110 #define CFG_SYS_CACHE_ACR0 (CFG_SYS_SDRAM_BASE | \
H A DM5253DEMO.h70 * Please note that CFG_SYS_SDRAM_BASE _must_ start at 0
72 #define CFG_SYS_SDRAM_BASE 0x00000000 macro
80 #define CFG_SYS_BOOTMAPSZ (CFG_SYS_SDRAM_BASE + (CFG_SYS_SDRAM_SIZE << 20))
110 #define CFG_SYS_CACHE_ACR1 (CFG_SYS_SDRAM_BASE | \
H A DM5282EVB.h65 * Please note that CFG_SYS_SDRAM_BASE _must_ start at 0
67 #define CFG_SYS_SDRAM_BASE 0x00000000 macro
78 #define CFG_SYS_BOOTMAPSZ (CFG_SYS_SDRAM_BASE + (CFG_SYS_SDRAM_SIZE << 20))
98 #define CFG_SYS_CACHE_ACR0 (CFG_SYS_SDRAM_BASE | \
H A DM53017EVB.h67 * Please note that CFG_SYS_SDRAM_BASE _must_ start at 0
69 #define CFG_SYS_SDRAM_BASE 0x40000000 macro
82 #define CFG_SYS_BOOTMAPSZ (CFG_SYS_SDRAM_BASE + (CFG_SYS_SDRAM_SIZE << 20))
110 #define CFG_SYS_CACHE_ACR0 (CFG_SYS_SDRAM_BASE | \
H A DM5249EVB.h53 * Please note that CFG_SYS_SDRAM_BASE _must_ start at 0
55 #define CFG_SYS_SDRAM_BASE 0x00000000 macro
68 #define CFG_SYS_BOOTMAPSZ (CFG_SYS_SDRAM_BASE + (CFG_SYS_SDRAM_SIZE << 20))
91 #define CFG_SYS_CACHE_ACR1 (CFG_SYS_SDRAM_BASE | \
H A Dastro_mcf5373l.h126 #define CFG_SYS_SDRAM_BASE 0x40000000 macro
163 #define CFG_SYS_BOOTMAPSZ (CFG_SYS_SDRAM_BASE + \
181 #define CFG_SYS_CACHE_ACR0 (CFG_SYS_SDRAM_BASE | \
H A DM5329EVB.h61 * Please note that CFG_SYS_SDRAM_BASE _must_ start at 0
63 #define CFG_SYS_SDRAM_BASE 0x40000000 macro
76 #define CFG_SYS_BOOTMAPSZ (CFG_SYS_SDRAM_BASE + (CFG_SYS_SDRAM_SIZE << 20))
110 #define CFG_SYS_CACHE_ACR0 (CFG_SYS_SDRAM_BASE | \
H A Dcolibri_vf.h80 #define CFG_SYS_SDRAM_BASE PHYS_SDRAM macro
H A Dcm_fx6.h24 #define CFG_SYS_SDRAM_BASE PHYS_SDRAM_1 macro
H A Dcorvus.h35 #define CFG_SYS_SDRAM_BASE ATMEL_BASE_CS6 macro
H A Ddisplay5.h281 #define CFG_SYS_SDRAM_BASE PHYS_SDRAM macro
H A Dls1012a_common.h15 #define CFG_SYS_SDRAM_BASE CFG_SYS_DDR_SDRAM_BASE macro
H A Dimx8qm_rom7720.h111 #define CFG_SYS_SDRAM_BASE 0x80000000 macro
H A Dls1028a_common.h17 #define CFG_SYS_SDRAM_BASE CFG_SYS_DDR_SDRAM_BASE macro
/u-boot/board/mediatek/mt8518/
H A Dmt8518_ap1.c18 gd->bd->bi_boot_params = CFG_SYS_SDRAM_BASE + 0x100;
/u-boot/board/mscc/servalt/
H A Dservalt.c25 gd->bd->bi_boot_params = CFG_SYS_SDRAM_BASE;
/u-boot/board/imgtec/boston/
H A Dddr.c30 if (gd->ram_top < CFG_SYS_SDRAM_BASE) {
/u-boot/arch/arm/mach-at91/arm926ejs/
H A Dlowlevel_init.S204 .word CFG_SYS_SDRAM_BASE
208 .word CFG_SYS_SDRAM_BASE
210 .word CFG_SYS_SDRAM_BASE
212 .word CFG_SYS_SDRAM_BASE
214 .word CFG_SYS_SDRAM_BASE
216 .word CFG_SYS_SDRAM_BASE
218 .word CFG_SYS_SDRAM_BASE
220 .word CFG_SYS_SDRAM_BASE
222 .word CFG_SYS_SDRAM_BASE
226 .word CFG_SYS_SDRAM_BASE
[all...]
/u-boot/board/freescale/m5235evb/
H A Dm5235evb.c64 SDRAMC_DARCn_BA(CFG_SYS_SDRAM_BASE) |
83 *(u32 *) (CFG_SYS_SDRAM_BASE) = 0xA5A59696;
98 *(u32 *) (CFG_SYS_SDRAM_BASE + 0x400) = 0xA5A59696;
/u-boot/drivers/ram/rockchip/
H A Dsdram_common.c225 writel(0, CFG_SYS_SDRAM_BASE);
226 test_addr = (void __iomem *)(CFG_SYS_SDRAM_BASE +
230 (readl(CFG_SYS_SDRAM_BASE) == 0))
250 test_addr = (void __iomem *)(CFG_SYS_SDRAM_BASE +
252 writel(0, CFG_SYS_SDRAM_BASE);
255 (readl(CFG_SYS_SDRAM_BASE) == 0))
273 test_addr = (void __iomem *)(CFG_SYS_SDRAM_BASE +
275 writel(0, CFG_SYS_SDRAM_BASE);
278 (readl(CFG_SYS_SDRAM_BASE) == 0))
342 writel(0, CFG_SYS_SDRAM_BASE);
[all...]
/u-boot/board/ti/ks2_evm/
H A Dboard.c49 gd->ram_size = get_ram_size((long *)CFG_SYS_SDRAM_BASE,
74 gd->bd->bi_boot_params = CFG_SYS_SDRAM_BASE + 0x100;
123 start[0] -= CFG_SYS_SDRAM_BASE;
177 initrd_start -= CFG_SYS_SDRAM_BASE;
181 initrd_end -= CFG_SYS_SDRAM_BASE;
224 *reserve_start -= CFG_SYS_SDRAM_BASE;
/u-boot/arch/arm/mach-mvebu/alleycat5/
H A Dcpu.c27 .phys = CFG_SYS_SDRAM_BASE,
28 .virt = CFG_SYS_SDRAM_BASE,
141 gd->bd->bi_dram[0].start = CFG_SYS_SDRAM_BASE;
/u-boot/board/armltd/integrator/
H A Dintegrator.c140 gd->bd->bi_dram[0].start = CFG_SYS_SDRAM_BASE;
163 gd->ram_size = get_ram_size((long *) CFG_SYS_SDRAM_BASE +
168 gd->ram_size = get_ram_size((long *) CFG_SYS_SDRAM_BASE +

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