193787Sdes// SPDX-License-Identifier: GPL-2.0+ 293787Sdes/* 393787Sdes * Copyright (C) 2018 Marvell International Ltd. 493787Sdes */ 593787Sdes 693787Sdes#include <common.h> 793787Sdes#include <dm.h> 893787Sdes#include <fdtdec.h> 993787Sdes#include <linux/libfdt.h> 1093787Sdes#include <asm/io.h> 1193787Sdes#include <asm/system.h> 1293787Sdes#include <asm/arch/cpu.h> 1393787Sdes#include <linux/sizes.h> 1493787Sdes#include <asm/armv8/mmu.h> 1593787Sdes#include "soc.h" 1693787Sdes 1793787SdesDECLARE_GLOBAL_DATA_PTR; 1893787Sdes 1993787Sdes#define AC5_PTE_BLOCK_DEVICE \ 2093787Sdes (PTE_BLOCK_MEMTYPE(MT_DEVICE_NGNRNE) | \ 2193787Sdes PTE_BLOCK_NON_SHARE | \ 2293787Sdes PTE_BLOCK_PXN | PTE_BLOCK_UXN) 2393787Sdes 2493787Sdesstatic struct mm_region ac5_mem_map[] = { 2593787Sdes { 2693787Sdes /* RAM */ 2793787Sdes .phys = CFG_SYS_SDRAM_BASE, 2893787Sdes .virt = CFG_SYS_SDRAM_BASE, 2993787Sdes .attrs = PTE_BLOCK_MEMTYPE(MT_NORMAL) | 3093787Sdes PTE_BLOCK_INNER_SHARE 3193787Sdes }, 3293787Sdes { 3393787Sdes /* MMIO regions */ 3493787Sdes .phys = 0x00000000, 3593787Sdes .virt = 0xa0000000, 3693787Sdes .size = 0x100000, 3793787Sdes .attrs = AC5_PTE_BLOCK_DEVICE, 3893787Sdes }, 3993787Sdes { 4093787Sdes /* MMIO regions */ 4193787Sdes .phys = 0x100000, 4293787Sdes .virt = 0x100000, 4393787Sdes .size = 0x3ff00000, 4493787Sdes .attrs = AC5_PTE_BLOCK_DEVICE, 4593787Sdes }, 4693787Sdes { 4793787Sdes .phys = 0x7F000000, 4893787Sdes .virt = 0x7F000000, 4993787Sdes .size = SZ_8M, 5093787Sdes .attrs = AC5_PTE_BLOCK_DEVICE, 5193787Sdes }, 5293787Sdes { 5393787Sdes .phys = 0x7F800000, 5493787Sdes .virt = 0x7F800000, 5593787Sdes .size = SZ_4M, 5693787Sdes .attrs = AC5_PTE_BLOCK_DEVICE, 5793787Sdes }, 5893787Sdes { 5993787Sdes .phys = 0x7FC00000, 6093787Sdes .virt = 0x7FC00000, 6193787Sdes .size = SZ_512K, 6293787Sdes .attrs = AC5_PTE_BLOCK_DEVICE, 6393787Sdes }, 6493787Sdes { 6593787Sdes .phys = 0x7FC80000, 6693787Sdes .virt = 0x7FC80000, 6793787Sdes .size = SZ_512K, 6893787Sdes .attrs = AC5_PTE_BLOCK_DEVICE, 6993787Sdes }, 7093787Sdes { 7193787Sdes .phys = 0x7FD00000, 7293787Sdes .virt = 0x7FD00000, 7393787Sdes .size = SZ_512K, 7493787Sdes .attrs = AC5_PTE_BLOCK_DEVICE, 7593787Sdes }, 7693787Sdes /* ATF region 0x7FE00000-0x7FE20000 not mapped */ 7793787Sdes { 7893787Sdes .phys = 0x7FE80000, 7993787Sdes .virt = 0x7FE80000, 8093787Sdes .size = SZ_512K, 8193787Sdes .attrs = AC5_PTE_BLOCK_DEVICE, 8293787Sdes }, 8393787Sdes { 8493787Sdes .phys = 0x7FFF0000, 8593787Sdes .virt = 0x7FFF0000, 8693787Sdes .size = SZ_1M, 8793787Sdes .attrs = AC5_PTE_BLOCK_DEVICE, 8893787Sdes }, 8993787Sdes { 9093787Sdes .phys = 0x80000000, 9193787Sdes .virt = 0x80000000, 9293787Sdes .size = SZ_2G, 9393787Sdes .attrs = AC5_PTE_BLOCK_DEVICE, 9493787Sdes }, 9593787Sdes { 9693787Sdes 0, 9793787Sdes } 9893787Sdes}; 9993787Sdes 10093787Sdesstruct mm_region *mem_map = ac5_mem_map; 10193787Sdes 10293787Sdesvoid reset_cpu(void) 10393787Sdes{ 10493787Sdes} 10593787Sdes 10693787Sdesint print_cpuinfo(void) 10793787Sdes{ 10893787Sdes soc_print_device_info(); 10993787Sdes soc_print_clock_info(); 11093787Sdes 11193787Sdes return 0; 11293787Sdes} 11393787Sdes 11493787Sdesint alleycat5_dram_init(void) 11593787Sdes{ 11693787Sdes#define SCRATCH_PAD_REG 0x80010018 11793787Sdes int ret; 11893787Sdes 11993787Sdes /* override DDR_FW size if DTS is set with size */ 12093787Sdes ret = fdtdec_setup_mem_size_base(); 12193787Sdes if (ret == -EINVAL) 12293787Sdes gd->ram_size = readl(SCRATCH_PAD_REG) * 4ULL; 12393787Sdes 12493787Sdes /* if DRAM size == 0, print error message */ 12593787Sdes if (gd->ram_size == 0) { 12693787Sdes pr_err("DRAM size not initialized - check DRAM configuration\n"); 12793787Sdes printf("\n Using temporary DRAM size of 512MB.\n\n"); 12893787Sdes gd->ram_size = SZ_512M; 12993787Sdes } 13093787Sdes 13193787Sdes ac5_mem_map[0].size = gd->ram_size; 13293787Sdes 13393787Sdes return 0; 13493787Sdes} 13593787Sdes 13693787Sdesint alleycat5_dram_init_banksize(void) 13793787Sdes{ 13893787Sdes /* 13993787Sdes * Config single DRAM bank 14093787Sdes */ 14193787Sdes gd->bd->bi_dram[0].start = CFG_SYS_SDRAM_BASE; 14293787Sdes gd->bd->bi_dram[0].size = gd->ram_size; 14393787Sdes 144 return 0; 145} 146 147int timer_init(void) 148{ 149 return 0; 150} 151 152/* 153 * get_ref_clk 154 * 155 * return: reference clock in MHz 156 */ 157u32 get_ref_clk(void) 158{ 159 return 25; 160} 161