1// SPDX-License-Identifier: GPL-2.0+
2/*
3 * (C) Copyright 2000-2003
4 * Wolfgang Denk, DENX Software Engineering, wd@denx.de.
5 *
6 * Copyright (C) 2004-2007, 2012 Freescale Semiconductor, Inc.
7 * TsiChung Liew (Tsi-Chung.Liew@freescale.com)
8 */
9
10#include <config.h>
11#include <common.h>
12#include <init.h>
13#include <asm/global_data.h>
14#include <asm/immap.h>
15#include <asm/io.h>
16
17DECLARE_GLOBAL_DATA_PTR;
18
19int checkboard(void)
20{
21	puts("Board: ");
22	puts("Freescale M5235 EVB\n");
23	return 0;
24};
25
26int dram_init(void)
27{
28	sdram_t *sdram = (sdram_t *)(MMAP_SDRAM);
29	gpio_t *gpio = (gpio_t *)(MMAP_GPIO);
30	u32 dramsize, i, dramclk;
31
32	/*
33	 * When booting from external Flash, the port-size is less than
34	 * the port-size of SDRAM.  In this case it is necessary to enable
35	 * Data[15:0] on Port Address/Data.
36	 */
37	out_8(&gpio->par_ad,
38		GPIO_PAR_AD_ADDR23 | GPIO_PAR_AD_ADDR22 | GPIO_PAR_AD_ADDR21 |
39		GPIO_PAR_AD_DATAL);
40
41	/* Initialize PAR to enable SDRAM signals */
42	out_8(&gpio->par_sdram,
43		GPIO_PAR_SDRAM_SDWE | GPIO_PAR_SDRAM_SCAS |
44		GPIO_PAR_SDRAM_SRAS | GPIO_PAR_SDRAM_SCKE |
45		GPIO_PAR_SDRAM_SDCS(3));
46
47	dramsize = CFG_SYS_SDRAM_SIZE * 0x100000;
48	for (i = 0x13; i < 0x20; i++) {
49		if (dramsize == (1 << i))
50			break;
51	}
52	i--;
53
54	if (!(in_be32(&sdram->dacr0) & SDRAMC_DARCn_RE)) {
55		dramclk = gd->bus_clk / (CONFIG_SYS_HZ * CONFIG_SYS_HZ);
56
57		/* Initialize DRAM Control Register: DCR */
58		out_be16(&sdram->dcr, SDRAMC_DCR_RTIM_9CLKS |
59			SDRAMC_DCR_RTIM_6CLKS |
60			SDRAMC_DCR_RC((15 * dramclk) >> 4));
61
62		/* Initialize DACR0 */
63		out_be32(&sdram->dacr0,
64			SDRAMC_DARCn_BA(CFG_SYS_SDRAM_BASE) |
65			SDRAMC_DARCn_CASL_C1 | SDRAMC_DARCn_CBM_CMD20 |
66			SDRAMC_DARCn_PS_32);
67		asm("nop");
68
69		/* Initialize DMR0 */
70		out_be32(&sdram->dmr0,
71			((dramsize - 1) & 0xFFFC0000) | SDRAMC_DMRn_V);
72		asm("nop");
73
74		/* Set IP (bit 3) in DACR */
75		setbits_be32(&sdram->dacr0, SDRAMC_DARCn_IP);
76
77		/* Wait 30ns to allow banks to precharge */
78		for (i = 0; i < 5; i++) {
79			asm("nop");
80		}
81
82		/* Write to this block to initiate precharge */
83		*(u32 *) (CFG_SYS_SDRAM_BASE) = 0xA5A59696;
84
85		/*  Set RE (bit 15) in DACR */
86		setbits_be32(&sdram->dacr0, SDRAMC_DARCn_RE);
87
88		/* Wait for at least 8 auto refresh cycles to occur */
89		for (i = 0; i < 0x2000; i++) {
90			asm("nop");
91		}
92
93		/* Finish the configuration by issuing the MRS. */
94		setbits_be32(&sdram->dacr0, SDRAMC_DARCn_IMRS);
95		asm("nop");
96
97		/* Write to the SDRAM Mode Register */
98		*(u32 *) (CFG_SYS_SDRAM_BASE + 0x400) = 0xA5A59696;
99	}
100
101	gd->ram_size = dramsize;
102
103	return 0;
104};
105
106int testdram(void)
107{
108	/* TODO: XXX XXX XXX */
109	printf("DRAM test not implemented!\n");
110
111	return (0);
112}
113