1// SPDX-License-Identifier: GPL-2.0+
2/*
3 * Keystone : Board initialization
4 *
5 * (C) Copyright 2014
6 *     Texas Instruments Incorporated, <www.ti.com>
7 */
8
9#include <common.h>
10#include <asm/global_data.h>
11#include "board.h"
12#include <env.h>
13#include <hang.h>
14#include <image.h>
15#include <init.h>
16#include <spl.h>
17#include <exports.h>
18#include <fdt_support.h>
19#include <asm/arch/ddr3.h>
20#include <asm/arch/psc_defs.h>
21#include <asm/arch/clock.h>
22#include <asm/ti-common/ti-aemif.h>
23#include <asm/ti-common/keystone_net.h>
24
25DECLARE_GLOBAL_DATA_PTR;
26
27#if defined(CONFIG_TI_AEMIF)
28static struct aemif_config aemif_configs[] = {
29	{			/* CS0 */
30		.mode		= AEMIF_MODE_NAND,
31		.wr_setup	= 0xf,
32		.wr_strobe	= 0x3f,
33		.wr_hold	= 7,
34		.rd_setup	= 0xf,
35		.rd_strobe	= 0x3f,
36		.rd_hold	= 7,
37		.turn_around	= 3,
38		.width		= AEMIF_WIDTH_8,
39	},
40};
41#endif
42
43int dram_init(void)
44{
45	u32 ddr3_size;
46
47	ddr3_size = ddr3_init();
48
49	gd->ram_size = get_ram_size((long *)CFG_SYS_SDRAM_BASE,
50				    CFG_MAX_RAM_BANK_SIZE);
51#if defined(CONFIG_TI_AEMIF)
52	if (!(board_is_k2g_ice() || board_is_k2g_i1()))
53		aemif_init(ARRAY_SIZE(aemif_configs), aemif_configs);
54#endif
55
56	if (!(board_is_k2g_ice() || board_is_k2g_i1())) {
57		if (ddr3_size)
58			ddr3_init_ecc(KS2_DDR3A_EMIF_CTRL_BASE, ddr3_size);
59		else
60			ddr3_init_ecc(KS2_DDR3A_EMIF_CTRL_BASE,
61				      gd->ram_size >> 30);
62	}
63
64	return 0;
65}
66
67struct legacy_img_hdr *spl_get_load_buffer(ssize_t offset, size_t size)
68{
69	return (struct legacy_img_hdr *)(CONFIG_TEXT_BASE);
70}
71
72int board_init(void)
73{
74	gd->bd->bi_boot_params = CFG_SYS_SDRAM_BASE + 0x100;
75	return 0;
76}
77
78#ifdef CONFIG_SPL_BUILD
79void spl_board_init(void)
80{
81	spl_init_keystone_plls();
82	preloader_console_init();
83}
84
85u32 spl_boot_device(void)
86{
87#if defined(CONFIG_SPL_SPI_LOAD)
88	return BOOT_DEVICE_SPI;
89#else
90	puts("Unknown boot device\n");
91	hang();
92#endif
93}
94#endif
95
96#ifdef CONFIG_OF_BOARD_SETUP
97int ft_board_setup(void *blob, struct bd_info *bd)
98{
99	int lpae;
100	char *env;
101	char *endp;
102	int nbanks;
103	u64 size[2];
104	u64 start[2];
105	u32 ddr3a_size;
106
107	env = env_get("mem_lpae");
108	lpae = env && simple_strtol(env, NULL, 0);
109
110	ddr3a_size = 0;
111	if (lpae) {
112		ddr3a_size = ddr3_get_size();
113		if ((ddr3a_size != 8) && (ddr3a_size != 4))
114			ddr3a_size = 0;
115	}
116
117	nbanks = 1;
118	start[0] = bd->bi_dram[0].start;
119	size[0]  = bd->bi_dram[0].size;
120
121	/* adjust memory start address for LPAE */
122	if (lpae) {
123		start[0] -= CFG_SYS_SDRAM_BASE;
124		start[0] += CFG_SYS_LPAE_SDRAM_BASE;
125	}
126
127	if ((size[0] == 0x80000000) && (ddr3a_size != 0)) {
128		size[1] = ((u64)ddr3a_size - 2) << 30;
129		start[1] = 0x880000000;
130		nbanks++;
131	}
132
133	/* reserve memory at start of bank */
134	env = env_get("mem_reserve_head");
135	if (env) {
136		start[0] += ustrtoul(env, &endp, 0);
137		size[0] -= ustrtoul(env, &endp, 0);
138	}
139
140	env = env_get("mem_reserve");
141	if (env)
142		size[0] -= ustrtoul(env, &endp, 0);
143
144	fdt_fixup_memory_banks(blob, start, size, nbanks);
145
146	return 0;
147}
148
149void ft_board_setup_ex(void *blob, struct bd_info *bd)
150{
151	int lpae;
152	u64 size;
153	char *env;
154	u64 *reserve_start;
155	int unitrd_fixup = 0;
156
157	env = env_get("mem_lpae");
158	lpae = env && simple_strtol(env, NULL, 0);
159	env = env_get("uinitrd_fixup");
160	unitrd_fixup = env && simple_strtol(env, NULL, 0);
161
162	/* Fix up the initrd */
163	if (lpae && unitrd_fixup) {
164		int nodeoffset;
165		int err;
166		u64 *prop1, *prop2;
167		u64 initrd_start, initrd_end;
168
169		nodeoffset = fdt_path_offset(blob, "/chosen");
170		if (nodeoffset >= 0) {
171			prop1 = (u64 *)fdt_getprop(blob, nodeoffset,
172					    "linux,initrd-start", NULL);
173			prop2 = (u64 *)fdt_getprop(blob, nodeoffset,
174					    "linux,initrd-end", NULL);
175			if (prop1 && prop2) {
176				initrd_start = __be64_to_cpu(*prop1);
177				initrd_start -= CFG_SYS_SDRAM_BASE;
178				initrd_start += CFG_SYS_LPAE_SDRAM_BASE;
179				initrd_start = __cpu_to_be64(initrd_start);
180				initrd_end = __be64_to_cpu(*prop2);
181				initrd_end -= CFG_SYS_SDRAM_BASE;
182				initrd_end += CFG_SYS_LPAE_SDRAM_BASE;
183				initrd_end = __cpu_to_be64(initrd_end);
184
185				err = fdt_delprop(blob, nodeoffset,
186						  "linux,initrd-start");
187				if (err < 0)
188					puts("error deleting initrd-start\n");
189
190				err = fdt_delprop(blob, nodeoffset,
191						  "linux,initrd-end");
192				if (err < 0)
193					puts("error deleting initrd-end\n");
194
195				err = fdt_setprop(blob, nodeoffset,
196						  "linux,initrd-start",
197						  &initrd_start,
198						  sizeof(initrd_start));
199				if (err < 0)
200					puts("error adding initrd-start\n");
201
202				err = fdt_setprop(blob, nodeoffset,
203						  "linux,initrd-end",
204						  &initrd_end,
205						  sizeof(initrd_end));
206				if (err < 0)
207					puts("error adding linux,initrd-end\n");
208			}
209		}
210	}
211
212	if (lpae) {
213		/*
214		 * the initrd and other reserved memory areas are
215		 * embedded in in the DTB itslef. fix up these addresses
216		 * to 36 bit format
217		 */
218		reserve_start = (u64 *)((char *)blob +
219				       fdt_off_mem_rsvmap(blob));
220		while (1) {
221			*reserve_start = __cpu_to_be64(*reserve_start);
222			size = __cpu_to_be64(*(reserve_start + 1));
223			if (size) {
224				*reserve_start -= CFG_SYS_SDRAM_BASE;
225				*reserve_start +=
226					CFG_SYS_LPAE_SDRAM_BASE;
227				*reserve_start =
228					__cpu_to_be64(*reserve_start);
229			} else {
230				break;
231			}
232			reserve_start += 2;
233		}
234	}
235
236	ddr3_check_ecc_int(KS2_DDR3A_EMIF_CTRL_BASE);
237}
238#endif /* CONFIG_OF_BOARD_SETUP */
239
240#if defined(CONFIG_DTB_RESELECT)
241int __weak embedded_dtb_select(void)
242{
243	return 0;
244}
245#endif
246