1// SPDX-License-Identifier: GPL-2.0+
2/*
3 * Copyright (C) 2018 Marvell International Ltd.
4 */
5
6#include <common.h>
7#include <dm.h>
8#include <fdtdec.h>
9#include <linux/libfdt.h>
10#include <asm/io.h>
11#include <asm/system.h>
12#include <asm/arch/cpu.h>
13#include <linux/sizes.h>
14#include <asm/armv8/mmu.h>
15#include "soc.h"
16
17DECLARE_GLOBAL_DATA_PTR;
18
19#define AC5_PTE_BLOCK_DEVICE \
20	(PTE_BLOCK_MEMTYPE(MT_DEVICE_NGNRNE) | \
21			 PTE_BLOCK_NON_SHARE | \
22			 PTE_BLOCK_PXN | PTE_BLOCK_UXN)
23
24static struct mm_region ac5_mem_map[] = {
25	{
26		/* RAM */
27		.phys = CFG_SYS_SDRAM_BASE,
28		.virt = CFG_SYS_SDRAM_BASE,
29		.attrs = PTE_BLOCK_MEMTYPE(MT_NORMAL) |
30			 PTE_BLOCK_INNER_SHARE
31	},
32	{
33		/* MMIO regions */
34		.phys = 0x00000000,
35		.virt = 0xa0000000,
36		.size = 0x100000,
37		.attrs = AC5_PTE_BLOCK_DEVICE,
38	},
39	{
40		/* MMIO regions */
41		.phys = 0x100000,
42		.virt = 0x100000,
43		.size = 0x3ff00000,
44		.attrs = AC5_PTE_BLOCK_DEVICE,
45	},
46	{
47		.phys = 0x7F000000,
48		.virt = 0x7F000000,
49		.size = SZ_8M,
50		.attrs = AC5_PTE_BLOCK_DEVICE,
51	},
52	{
53		.phys = 0x7F800000,
54		.virt = 0x7F800000,
55		.size = SZ_4M,
56		.attrs = AC5_PTE_BLOCK_DEVICE,
57	},
58	{
59		.phys = 0x7FC00000,
60		.virt = 0x7FC00000,
61		.size = SZ_512K,
62		.attrs = AC5_PTE_BLOCK_DEVICE,
63	},
64	{
65		.phys = 0x7FC80000,
66		.virt = 0x7FC80000,
67		.size = SZ_512K,
68		.attrs = AC5_PTE_BLOCK_DEVICE,
69	},
70	{
71		.phys = 0x7FD00000,
72		.virt = 0x7FD00000,
73		.size = SZ_512K,
74		.attrs = AC5_PTE_BLOCK_DEVICE,
75	},
76	/* ATF region 0x7FE00000-0x7FE20000 not mapped */
77	{
78		.phys = 0x7FE80000,
79		.virt = 0x7FE80000,
80		.size = SZ_512K,
81		.attrs = AC5_PTE_BLOCK_DEVICE,
82	},
83	{
84		.phys = 0x7FFF0000,
85		.virt = 0x7FFF0000,
86		.size = SZ_1M,
87		.attrs = AC5_PTE_BLOCK_DEVICE,
88	},
89	{
90		.phys = 0x80000000,
91		.virt = 0x80000000,
92		.size = SZ_2G,
93		.attrs = AC5_PTE_BLOCK_DEVICE,
94	},
95	{
96		0,
97	}
98};
99
100struct mm_region *mem_map = ac5_mem_map;
101
102void reset_cpu(void)
103{
104}
105
106int print_cpuinfo(void)
107{
108	soc_print_device_info();
109	soc_print_clock_info();
110
111	return 0;
112}
113
114int alleycat5_dram_init(void)
115{
116#define SCRATCH_PAD_REG		0x80010018
117	int ret;
118
119	/* override DDR_FW size if DTS is set with size */
120	ret = fdtdec_setup_mem_size_base();
121	if (ret == -EINVAL)
122		gd->ram_size = readl(SCRATCH_PAD_REG) * 4ULL;
123
124	/* if DRAM size == 0, print error message */
125	if (gd->ram_size == 0) {
126		pr_err("DRAM size not initialized - check DRAM configuration\n");
127		printf("\n Using temporary DRAM size of 512MB.\n\n");
128		gd->ram_size = SZ_512M;
129	}
130
131	ac5_mem_map[0].size = gd->ram_size;
132
133	return 0;
134}
135
136int alleycat5_dram_init_banksize(void)
137{
138	/*
139	 * Config single DRAM bank
140	 */
141	gd->bd->bi_dram[0].start = CFG_SYS_SDRAM_BASE;
142	gd->bd->bi_dram[0].size = gd->ram_size;
143
144	return 0;
145}
146
147int timer_init(void)
148{
149	return 0;
150}
151
152/*
153 * get_ref_clk
154 *
155 * return: reference clock in MHz
156 */
157u32 get_ref_clk(void)
158{
159	return 25;
160}
161