Searched refs:CFG_SYS_SDRAM_BASE (Results 126 - 150 of 556) sorted by relevance

1234567891011>>

/u-boot/include/configs/
H A Drk322x_common.h14 #define CFG_SYS_SDRAM_BASE 0x60000000 macro
H A Drk3368_common.h13 #define CFG_SYS_SDRAM_BASE 0 macro
H A Drk3066_common.h13 #define CFG_SYS_SDRAM_BASE 0x60000000 macro
H A Drk3288_common.h15 #define CFG_SYS_SDRAM_BASE 0 macro
H A Drk3036_common.h12 #define CFG_SYS_SDRAM_BASE 0x60000000 macro
H A Drk3188_common.h13 #define CFG_SYS_SDRAM_BASE 0x60000000 macro
H A Dmt7621.h11 #define CFG_SYS_SDRAM_BASE 0x80000000 macro
H A Ds5pc210_universal.h17 #define CFG_SYS_SDRAM_BASE 0x40000000 macro
18 #define PHYS_SDRAM_1 CFG_SYS_SDRAM_BASE
H A Dodroid.h21 #define CFG_SYS_SDRAM_BASE 0x40000000 macro
23 #define PHYS_SDRAM_1 CFG_SYS_SDRAM_BASE
H A Dstmark2.h57 * Please note that CFG_SYS_SDRAM_BASE _must_ start at 0
59 #define CFG_SYS_SDRAM_BASE 0x40000000 macro
72 #define CFG_SYS_BOOTMAPSZ (CFG_SYS_SDRAM_BASE + \
86 #define CFG_SYS_CACHE_ACR2 (CFG_SYS_SDRAM_BASE | \
H A DM5208EVBE.h53 * Please note that CFG_SYS_SDRAM_BASE _must_ start at 0
55 #define CFG_SYS_SDRAM_BASE 0x40000000 macro
68 #define CFG_SYS_BOOTMAPSZ (CFG_SYS_SDRAM_BASE + (CFG_SYS_SDRAM_SIZE << 20))
93 #define CFG_SYS_CACHE_ACR0 (CFG_SYS_SDRAM_BASE | \
H A DM5275EVB.h72 * Please note that CFG_SYS_SDRAM_BASE _must_ start at 0
74 #define CFG_SYS_SDRAM_BASE 0x00000000 macro
83 #define CFG_SYS_BOOTMAPSZ (CFG_SYS_SDRAM_BASE + (CFG_SYS_SDRAM_SIZE << 20))
100 #define CFG_SYS_CACHE_ACR0 (CFG_SYS_SDRAM_BASE | \
H A DM5235EVB.h64 * Please note that CFG_SYS_SDRAM_BASE _must_ start at 0
66 #define CFG_SYS_SDRAM_BASE 0x00000000 macro
75 #define CFG_SYS_BOOTMAPSZ (CFG_SYS_SDRAM_BASE + (CFG_SYS_SDRAM_SIZE << 20))
103 #define CFG_SYS_CACHE_ACR0 (CFG_SYS_SDRAM_BASE | \
H A DM5272C3.h62 * Please note that CFG_SYS_SDRAM_BASE _must_ start at 0
64 #define CFG_SYS_SDRAM_BASE 0x00000000 macro
73 #define CFG_SYS_BOOTMAPSZ (CFG_SYS_SDRAM_BASE + (CFG_SYS_SDRAM_SIZE << 20))
91 #define CFG_SYS_CACHE_ACR0 (CFG_SYS_SDRAM_BASE | \
H A Ds5p_goni.h17 #define CFG_SYS_SDRAM_BASE 0x30000000 macro
108 #define PHYS_SDRAM_1 CFG_SYS_SDRAM_BASE /* OneDRAM Bank #0 */
H A Dimx93_var_som.h14 #define CFG_SYS_SDRAM_BASE 0x80000000 macro
30 #define CFG_SYS_SDRAM_BASE 0x80000000 macro
H A Dbk4r1.h202 #define CFG_SYS_SDRAM_BASE PHYS_SDRAM macro
H A Dimx8qxp_mek.h105 #define CFG_SYS_SDRAM_BASE 0x80000000 macro
H A Dhsdk-4xd.h25 #define CFG_SYS_SDRAM_BASE CFG_SYS_DDR_SDRAM_BASE macro
H A Dhsdk.h24 #define CFG_SYS_SDRAM_BASE CFG_SYS_DDR_SDRAM_BASE macro
H A Dhikey960.h19 #define CFG_SYS_SDRAM_BASE PHYS_SDRAM_1 macro
/u-boot/board/ea/ea-lpc3250devkitv2/
H A Dea-lpc3250devkitv2.c32 gd->bd->bi_boot_params = CFG_SYS_SDRAM_BASE + 0x2000;
39 gd->ram_size = get_ram_size((void *)CFG_SYS_SDRAM_BASE, SZ_64M);
/u-boot/board/freescale/m5282evb/
H A Dm5282evb.c43 | MCFSDRAMC_DACR_BASE(CFG_SYS_SDRAM_BASE)
65 *(u32 *)(CFG_SYS_SDRAM_BASE) = 0xA5A59696;
82 *(u32 *)(CFG_SYS_SDRAM_BASE + 0x400) = 0xA5A59696;
/u-boot/board/gardena/smart-gateway-at91sam/
H A Dboard.c48 gd->bd->bi_boot_params = CFG_SYS_SDRAM_BASE + 0x100;
55 gd->ram_size = get_ram_size((void *)CFG_SYS_SDRAM_BASE,
/u-boot/board/Marvell/octeontx2_cn913x/
H A Dboard.c37 gd->bd->bi_boot_params = CFG_SYS_SDRAM_BASE + 0x100;

Completed in 124 milliseconds

1234567891011>>