1/* SPDX-License-Identifier: GPL-2.0+ */
2/*
3 * Copyright 2022 NXP
4 * Copyright 2023 Variscite Ltd.
5 */
6
7#ifndef __IMX93_VAR_SOM_H
8#define __IMX93_VAR_SOM_H
9
10#include <linux/sizes.h>
11#include <linux/stringify.h>
12#include <asm/arch/imx-regs.h>
13
14#define CFG_SYS_SDRAM_BASE           0x80000000
15#define CFG_SYS_UBOOT_BASE	\
16	(QSPI0_AMBA_BASE + CONFIG_SYS_MMCSD_RAW_MODE_U_BOOT_SECTOR * 512)
17
18#define BOOT_TARGET_DEVICES(func) \
19	func(MMC, mmc, 0) \
20	func(MMC, mmc, 1)
21
22#include <config_distro_bootcmd.h>
23
24/* Initial environment variables */
25#define CFG_EXTRA_ENV_SETTINGS BOOTENV
26
27#define CFG_SYS_INIT_RAM_ADDR        0x80000000
28#define CFG_SYS_INIT_RAM_SIZE        0x200000
29
30#define CFG_SYS_SDRAM_BASE           0x80000000
31#define PHYS_SDRAM                      0x80000000
32#define PHYS_SDRAM_SIZE			0x80000000 /* 2GB DDR */
33
34#define DEFAULT_SDRAM_SIZE		(512 * SZ_1M) /* 512MB Minimum DDR4, see get_dram_size */
35#define VAR_EEPROM_DRAM_START           (PHYS_SDRAM + (DEFAULT_SDRAM_SIZE >> 1))
36#define VAR_SOM_EEPROM_I2C_NAME "i2c@42530000"
37#define VAR_CARRIER_EEPROM_I2C_NAME "i2c@44340000"
38
39#define CFG_SYS_FSL_USDHC_NUM 2
40
41/* Using ULP WDOG for reset */
42#define WDOG_BASE_ADDR          WDG3_BASE_ADDR
43
44#if defined(CONFIG_CMD_NET)
45#define PHY_ANEG_TIMEOUT 20000
46#endif
47
48#endif
49