1/* SPDX-License-Identifier: GPL-2.0+ */ 2/* 3 * Configuation settings for the Motorola MC5272C3 board. 4 * 5 * (C) Copyright 2003 Josef Baumgartner <josef.baumgartner@telex.de> 6 */ 7 8/* 9 * board/config.h - configuration options, board specific 10 */ 11 12#ifndef _M5272C3_H 13#define _M5272C3_H 14 15/* 16 * High Level Configuration Options 17 * (easy to change) 18 */ 19 20#define CFG_SYS_UART_PORT (0) 21 22/* Configuration for environment 23 * Environment is embedded in u-boot in the second sector of the flash 24 */ 25 26#define LDS_BOARD_TEXT \ 27 . = DEFINED(env_offset) ? env_offset : .; \ 28 env/embedded.o(.text); 29 30#define CFG_EXTRA_ENV_SETTINGS \ 31 "netdev=eth0\0" \ 32 "loadaddr=10000\0" \ 33 "u-boot=u-boot.bin\0" \ 34 "load=tftp ${loadaddr) ${u-boot}\0" \ 35 "upd=run load; run prog\0" \ 36 "prog=prot off ffe00000 ffe3ffff;" \ 37 "era ffe00000 ffe3ffff;" \ 38 "cp.b ${loadaddr} ffe00000 ${filesize};"\ 39 "save\0" \ 40 "" 41 42#define CFG_SYS_CLK 66000000 43 44/* 45 * Low Level Configuration Settings 46 * (address mappings, register initial values, etc.) 47 * You should know what you are doing if you make changes here. 48 */ 49#define CFG_SYS_MBAR 0x10000000 /* Register Base Addrs */ 50#define CFG_SYS_SCR 0x0003 51#define CFG_SYS_SPR 0xffff 52 53/*----------------------------------------------------------------------- 54 * Definitions for initial stack pointer and data area (in DPRAM) 55 */ 56#define CFG_SYS_INIT_RAM_ADDR 0x20000000 57#define CFG_SYS_INIT_RAM_SIZE 0x1000 /* Size of used area in internal SRAM */ 58 59/*----------------------------------------------------------------------- 60 * Start addresses for the final memory configuration 61 * (Set up by the startup code) 62 * Please note that CFG_SYS_SDRAM_BASE _must_ start at 0 63 */ 64#define CFG_SYS_SDRAM_BASE 0x00000000 65#define CFG_SYS_SDRAM_SIZE 4 /* SDRAM size in MB */ 66#define CFG_SYS_FLASH_BASE 0xffe00000 67 68/* 69 * For booting Linux, the board info and command line data 70 * have to be in the first 8 MB of memory, since this is 71 * the maximum mapped by the Linux kernel during initialization ?? 72 */ 73#define CFG_SYS_BOOTMAPSZ (CFG_SYS_SDRAM_BASE + (CFG_SYS_SDRAM_SIZE << 20)) 74 75/* 76 * FLASH organization 77 */ 78#ifdef CONFIG_SYS_FLASH_CFI 79# define CFG_SYS_FLASH_SIZE 0x800000 /* Max size that the board might have */ 80#endif 81 82/*----------------------------------------------------------------------- 83 * Cache Configuration 84 */ 85 86#define ICACHE_STATUS (CFG_SYS_INIT_RAM_ADDR + \ 87 CFG_SYS_INIT_RAM_SIZE - 8) 88#define DCACHE_STATUS (CFG_SYS_INIT_RAM_ADDR + \ 89 CFG_SYS_INIT_RAM_SIZE - 4) 90#define CFG_SYS_ICACHE_INV (CF_CACR_CINV | CF_CACR_INVI) 91#define CFG_SYS_CACHE_ACR0 (CFG_SYS_SDRAM_BASE | \ 92 CF_ADDRMASK(CFG_SYS_SDRAM_SIZE) | \ 93 CF_ACR_EN | CF_ACR_SM_ALL) 94#define CFG_SYS_CACHE_ICACR (CF_CACR_CENB | CF_CACR_CINV | \ 95 CF_CACR_DISD | CF_CACR_INVI | \ 96 CF_CACR_CEIB | CF_CACR_DCM | \ 97 CF_CACR_EUSP) 98 99/*----------------------------------------------------------------------- 100 * Port configuration 101 */ 102#define CFG_SYS_PACNT 0x00000000 103#define CFG_SYS_PADDR 0x0000 104#define CFG_SYS_PADAT 0x0000 105#define CFG_SYS_PBCNT 0x55554155 /* Ethernet/UART configuration */ 106#define CFG_SYS_PBDDR 0x0000 107#define CFG_SYS_PBDAT 0x0000 108#define CFG_SYS_PDCNT 0x00000000 109 110 111#endif /* _M5272C3_H */ 112