1/* SPDX-License-Identifier: GPL-2.0+ */
2/*
3 * Configuation settings for the Freescale MCF5208EVBe.
4 *
5 * Copyright (C) 2004-2008 Freescale Semiconductor, Inc.
6 * TsiChung Liew (Tsi-Chung.Liew@freescale.com)
7 */
8
9#ifndef _M5208EVBE_H
10#define _M5208EVBE_H
11
12/*
13 * High Level Configuration Options
14 * (easy to change)
15 */
16#define CFG_SYS_UART_PORT		(0)
17
18/* I2C */
19
20#define CFG_EXTRA_ENV_SETTINGS		\
21	"netdev=eth0\0"				\
22	"loadaddr=40010000\0"			\
23	"u-boot=u-boot.bin\0"			\
24	"load=tftp ${loadaddr) ${u-boot}\0"	\
25	"upd=run load; run prog\0"		\
26	"prog=prot off 0 3ffff;"		\
27	"era 0 3ffff;"				\
28	"cp.b ${loadaddr} 0 ${filesize};"	\
29	"save\0"				\
30	""
31
32#define CFG_PRAM		512	/* 512 KB */
33
34#define CFG_SYS_CLK		166666666	/* CPU Core Clock */
35#define CFG_SYS_PLL_ODR	0x36
36#define CFG_SYS_PLL_FDR	0x7D
37
38#define CFG_SYS_MBAR		0xFC000000
39
40/*
41 * Low Level Configuration Settings
42 * (address mappings, register initial values, etc.)
43 * You should know what you are doing if you make changes here.
44 */
45/* Definitions for initial stack pointer and data area (in DPRAM) */
46#define CFG_SYS_INIT_RAM_ADDR	0x80000000
47#define CFG_SYS_INIT_RAM_SIZE		0x4000	/* Size of used area in internal SRAM */
48#define CFG_SYS_INIT_RAM_CTRL	0x221
49
50/*
51 * Start addresses for the final memory configuration
52 * (Set up by the startup code)
53 * Please note that CFG_SYS_SDRAM_BASE _must_ start at 0
54 */
55#define CFG_SYS_SDRAM_BASE		0x40000000
56#define CFG_SYS_SDRAM_SIZE		32	/* SDRAM size in MB */
57#define CFG_SYS_SDRAM_CFG1		0x43711630
58#define CFG_SYS_SDRAM_CFG2		0x56670000
59#define CFG_SYS_SDRAM_CTRL		0xE1002000
60#define CFG_SYS_SDRAM_EMOD		0x80010000
61#define CFG_SYS_SDRAM_MODE		0x00CD0000
62
63/*
64 * For booting Linux, the board info and command line data
65 * have to be in the first 8 MB of memory, since this is
66 * the maximum mapped by the Linux kernel during initialization ??
67 */
68#define CFG_SYS_BOOTMAPSZ		(CFG_SYS_SDRAM_BASE + (CFG_SYS_SDRAM_SIZE << 20))
69
70/* FLASH organization */
71#ifdef CONFIG_SYS_FLASH_CFI
72#	define CFG_SYS_FLASH_SIZE		0x800000	/* Max size that the board might have */
73#endif
74
75#define CFG_SYS_FLASH_BASE		CFG_SYS_CS0_BASE
76
77/*
78 * Configuration for environment
79 * Environment is embedded in u-boot in the second sector of the flash
80 */
81
82#define LDS_BOARD_TEXT \
83	. = DEFINED(env_offset) ? env_offset : .; \
84	env/embedded.o(.text*);
85
86/* Cache Configuration */
87
88#define ICACHE_STATUS			(CFG_SYS_INIT_RAM_ADDR + \
89					 CFG_SYS_INIT_RAM_SIZE - 8)
90#define DCACHE_STATUS			(CFG_SYS_INIT_RAM_ADDR + \
91					 CFG_SYS_INIT_RAM_SIZE - 4)
92#define CFG_SYS_ICACHE_INV		(CF_CACR_CINV | CF_CACR_INVI)
93#define CFG_SYS_CACHE_ACR0		(CFG_SYS_SDRAM_BASE | \
94					 CF_ADDRMASK(CFG_SYS_SDRAM_SIZE) | \
95					 CF_ACR_EN | CF_ACR_SM_ALL)
96#define CFG_SYS_CACHE_ICACR		(CF_CACR_CENB | CF_CACR_CINV | \
97					 CF_CACR_DISD | CF_CACR_INVI | \
98					 CF_CACR_CEIB | CF_CACR_DCM | \
99					 CF_CACR_EUSP)
100
101/* Chipselect bank definitions */
102/*
103 * CS0 - NOR Flash
104 * CS1 - Available
105 * CS2 - Available
106 * CS3 - Available
107 * CS4 - Available
108 * CS5 - Available
109 */
110#define CFG_SYS_CS0_BASE		0
111#define CFG_SYS_CS0_MASK		0x007F0001
112#define CFG_SYS_CS0_CTRL		0x00001FA0
113
114
115#endif				/* _M5208EVBE_H */
116