1// SPDX-License-Identifier: GPL-2.0+ 2/* 3 * (C) Copyright 2000-2003 4 * Wolfgang Denk, DENX Software Engineering, wd@denx.de. 5 */ 6 7#include <common.h> 8#include <init.h> 9#include <asm/global_data.h> 10#include <asm/immap.h> 11 12DECLARE_GLOBAL_DATA_PTR; 13 14int checkboard (void) 15{ 16 puts ("Board: Freescale M5282EVB Evaluation Board\n"); 17 return 0; 18} 19 20int dram_init(void) 21{ 22 u32 dramsize, i, dramclk; 23 24 dramsize = CFG_SYS_SDRAM_SIZE * 0x100000; 25 for (i = 0x13; i < 0x20; i++) { 26 if (dramsize == (1 << i)) 27 break; 28 } 29 i--; 30 31 if (!(MCFSDRAMC_DACR0 & MCFSDRAMC_DACR_RE)) 32 { 33 dramclk = gd->bus_clk / (CONFIG_SYS_HZ * CONFIG_SYS_HZ); 34 35 /* Initialize DRAM Control Register: DCR */ 36 MCFSDRAMC_DCR = (0 37 | MCFSDRAMC_DCR_RTIM_6 38 | MCFSDRAMC_DCR_RC((15 * dramclk)>>4)); 39 asm("nop"); 40 41 /* Initialize DACR0 */ 42 MCFSDRAMC_DACR0 = (0 43 | MCFSDRAMC_DACR_BASE(CFG_SYS_SDRAM_BASE) 44 | MCFSDRAMC_DACR_CASL(1) 45 | MCFSDRAMC_DACR_CBM(3) 46 | MCFSDRAMC_DACR_PS_32); 47 asm("nop"); 48 49 /* Initialize DMR0 */ 50 MCFSDRAMC_DMR0 = (0 51 | ((dramsize - 1) & 0xFFFC0000) 52 | MCFSDRAMC_DMR_V); 53 asm("nop"); 54 55 /* Set IP (bit 3) in DACR */ 56 MCFSDRAMC_DACR0 |= MCFSDRAMC_DACR_IP; 57 asm("nop"); 58 59 /* Wait 30ns to allow banks to precharge */ 60 for (i = 0; i < 5; i++) { 61 asm ("nop"); 62 } 63 64 /* Write to this block to initiate precharge */ 65 *(u32 *)(CFG_SYS_SDRAM_BASE) = 0xA5A59696; 66 asm("nop"); 67 68 /* Set RE (bit 15) in DACR */ 69 MCFSDRAMC_DACR0 |= MCFSDRAMC_DACR_RE; 70 asm("nop"); 71 72 /* Wait for at least 8 auto refresh cycles to occur */ 73 for (i = 0; i < 2000; i++) { 74 asm(" nop"); 75 } 76 77 /* Finish the configuration by issuing the IMRS. */ 78 MCFSDRAMC_DACR0 |= MCFSDRAMC_DACR_IMRS; 79 asm("nop"); 80 81 /* Write to the SDRAM Mode Register */ 82 *(u32 *)(CFG_SYS_SDRAM_BASE + 0x400) = 0xA5A59696; 83 } 84 gd->ram_size = dramsize; 85 86 return 0; 87} 88