Searched refs:c7 (Results 26 - 50 of 85) sorted by relevance

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/netgear-R7000-V1.0.7.12_1.2.5/components/opensource/linux/linux-2.6.36/arch/arm/mm/
H A Dproc-feroceon.S82 mcr p15, 0, r0, c7, c10, 4 @ drain WB
103 mcr p15, 0, ip, c7, c7, 0 @ invalidate I,D caches
104 mcr p15, 0, ip, c7, c10, 4 @ drain WB
106 mcr p15, 0, ip, c8, c7, 0 @ invalidate I & D TLBs
122 mcr p15, 0, r0, c7, c10, 4 @ Drain write buffer
123 mcr p15, 0, r0, c7, c0, 4 @ Wait for interrupt
148 2: mcr p15, 0, ip, c7, c14, 2 @ clean + invalidate D set/way
156 mcrne p15, 0, ip, c7, c5, 0 @ invalidate I cache
157 mcrne p15, 0, ip, c7, c1
[all...]
H A Dproc-xscale.S94 1: mcr p15, 0, \rd, c7, c2, 5 @ allocate D cache line
96 mcr p15, 0, \rd, c7, c2, 5 @ allocate D cache line
98 mcr p15, 0, \rd, c7, c2, 5 @ allocate D cache line
100 mcr p15, 0, \rd, c7, c2, 5 @ allocate D cache line
157 mcr p15, 0, ip, c7, c7, 0 @ invalidate I,D caches & BTB
161 mcr p15, 0, ip, c8, c7, 0 @ invalidate I & D TLBs
178 mcr p14, 0, r0, c7, c0, 0 @ Go to IDLE
203 mcrne p15, 0, ip, c7, c5, 0 @ Invalidate I cache & BTB
204 mcrne p15, 0, ip, c7, c1
[all...]
H A Dproc-v6.S73 mcr p15, 0, r1, c7, c10, 4 @ DWB - WFI may enter a low-power mode
74 mcr p15, 0, r1, c7, c0, 4 @ wait for interrupt
79 1: mcr p15, 0, r0, c7, c10, 1 @ clean D entry
101 mcr p15, 0, r2, c7, c5, 6 @ flush BTAC/BTB
102 mcr p15, 0, r2, c7, c10, 4 @ drain write buffer
165 mcr p15, 0, r0, c7, c14, 0 @ clean+invalidate D cache
166 mcr p15, 0, r0, c7, c5, 0 @ invalidate I cache
167 mcr p15, 0, r0, c7, c15, 0 @ clean+invalidate cache
168 mcr p15, 0, r0, c7, c10, 4 @ drain write buffer
170 mcr p15, 0, r0, c8, c7,
[all...]
H A Dproc-sa1100.S77 mcr p15, 0, ip, c7, c7, 0 @ invalidate I,D caches
78 mcr p15, 0, ip, c7, c10, 4 @ drain WB
80 mcr p15, 0, ip, c8, c7, 0 @ invalidate I & D TLBs
129 1: mcr p15, 0, r0, c7, c10, 1 @ clean D entry
151 mcr p15, 0, ip, c8, c7, 0 @ invalidate I & D TLBs
167 mcr p15, 0, r0, c7, c10, 1 @ clean D entry
168 mcr p15, 0, r0, c7, c10, 4 @ drain WB
177 mcr p15, 0, r0, c7, c7
[all...]
H A Dabort-ev7.S42 mcr p15, 0, r0, c7, c8, 0 @ Retranslate FAR
44 mrc p15, 0, r2, c7, c4, 0 @ Read the PAR
H A Dcache-v3.S45 mcreq p15, 0, ip, c7, c0, 0 @ flush ID cache
96 mcr p15, 0, r0, c7, c0, 0 @ flush ID cache
H A Dcache-v7.S64 mcr p15, 0, r11, c7, c14, 2 @ clean & invalidate by set/way
98 mcr p15, 0, r0, c7, c1, 0 @ invalidate I-cache inner shareable
100 mcr p15, 0, r0, c7, c5, 0 @ I+BTB cache invalidate
169 USER( mcr p15, 0, r0, c7, c11, 1 ) @ clean D line to the point of unification
171 USER( mcr p15, 0, r0, c7, c5, 1 ) @ invalidate I line
178 mcr p15, 0, r0, c7, c1, 6 @ invalidate BTB Inner Shareable
180 mcr p15, 0, r0, c7, c5, 6 @ invalidate BTB
212 mcr p15, 0, r0, c7, c14, 1 @ clean & invalidate D line / unified line
235 mcrne p15, 0, r0, c7, c14, 1 @ clean & invalidate D / U line
239 mcrne p15, 0, r1, c7, c1
[all...]
H A Dtlb-v4wb.S38 mcr p15, 0, r3, c7, c10, 4 @ drain WB
60 mcr p15, 0, r3, c7, c10, 4 @ drain WB
H A Dtlb-v4wbi.S37 mcr p15, 0, r3, c7, c10, 4 @ drain WB
51 mcr p15, 0, r3, c7, c10, 4 @ drain WB
H A Dtlb-v4.S40 1: mcr p15, 0, r0, c8, c7, 1 @ invalidate TLB entry
H A Dproc-macros.S154 mcr p15, 0, r0, c7, c10, 1 @ flush_pte
237 mcr p15, 0, r0, c7, c10, 1 @ clean L1 D line
238 mcr p15, 0, ip, c7, c10, 4 @ data write barrier
/netgear-R7000-V1.0.7.12_1.2.5/ap/gpl/iserver/libav-0.8.8/libavcodec/sh4/
H A Didct_sh4.c33 #define c7 0.27589937928294311353 /* sqrt(2)*cos(7*pi/16) */ macro
43 c1, c3, c5, c7,
44 c3,-c7,-c1,-c5,
45 c5,-c1, c7, c3,
46 c7,-c5, c3,-c1
55 #undef c7 macro
/netgear-R7000-V1.0.7.12_1.2.5/components/opensource/linux/linux-2.6.36/arch/arm/boot/compressed/
H A Dhead-xscale.S26 mcr p15, 0, r0, c7, c10, 4 @ drain WB
27 mcr p15, 0, r0, c7, c7, 0 @ flush I & D caches
H A Dhead.S358 mcr p15, 0, r0, c6, c7, 0 @ PR7 Area Setting
359 mcr p15, 0, r0, c6, c7, 1
371 mcr p15, 0, r0, c7, c10, 4 @ drain write buffer
372 mcr p15, 0, r0, c7, c5, 0 @ flush(inval) I-Cache
373 mcr p15, 0, r0, c7, c6, 0 @ flush(inval) D-Cache
382 mcr p15, 0, r0, c7, c5, 0 @ flush(inval) I-Cache
383 mcr p15, 0, r0, c7, c6, 0 @ flush(inval) D-Cache
388 mcr p15, 0, r0, c6, c7, 0 @ PR7 Area Setting
398 mcr p15, 0, r0, c7, c0, 0 @ invalidate whole cache v3
411 mcr p15, 0, r0, c7, c
[all...]
H A Dhead-shark.S57 mcr p15, 0, r0, c7, c7 @ flush I,D caches on v4
58 mcr p15, 0, r0, c7, c10, 4 @ drain write buffer on v4
59 mcr p15, 0, r0, c8, c7 @ flush I,D TLBs on v4
/netgear-R7000-V1.0.7.12_1.2.5/components/opensource/linux/linux-2.6.36/arch/arm/mach-s3c64xx/
H A Dsleep.S118 mcr p15, 0, r0, c7, c14, 0 @ clean+invalidate D cache
119 mcr p15, 0, r0, c7, c5, 0 @ invalidate I cache
120 mcr p15, 0, r0, c7, c15, 0 @ clean+invalidate cache
121 mcr p15, 0, r0, c7, c10, 4 @ drain write buffer
122 @@mcr p15, 0, r0, c8, c7, 0 @ invalidate I + D TLBs
123 @@mcr p15, 0, r0, c7, c7, 0 @ Invalidate I + D caches
137 mcr p15, 0, r0, c7, c5, 4
/netgear-R7000-V1.0.7.12_1.2.5/components/opensource/linux/linux-2.6.36/arch/arm/mach-omap2/
H A Dsleep24xx.S53 mcr p15, 0, r0, c7, c0, 4 @ wait for interrupt
62 mcr p15, 0, r3, c7, c10, 4 @ memory barrier, hope SDR/DDR finished
70 mcr p15, 0, r3, c7, c0, 4 @ wait for interrupt
H A Dsleep34xx.S170 mcr p15, 0, r0, c7, c10, 4 @ data write barrier
171 mcr p15, 0, r0, c7, c10, 5 @ data memory barrier
212 mcr p15, 0, r1, c7, c10, 4
213 mcr p15, 0, r1, c7, c10, 5
272 mcr p15, 0, r0, c7, c10, 4 @ data write barrier
273 mcr p15, 0, r0, c7, c10, 5 @ data memory barrier
283 mcr p15, 0, r0, c7, c10, 4 @ data write barrier
284 mcr p15, 0, r0, c7, c10, 5 @ data memory barrier
298 mcr p15, 0, r0, c7, c10, 4 @ data write barrier
299 mcr p15, 0, r0, c7, c1
[all...]
/netgear-R7000-V1.0.7.12_1.2.5/ap/gpl/iserver/libav-0.8.8/libavcodec/x86/
H A Didct_mmx.c77 #define mmxext_table(c1,c2,c3,c4,c5,c6,c7) { c4, c2, -c4, -c2, \
80 c5, c7, c3, -c7, \
84 c7, c3, c7, -c5 }
203 #define mmx_table(c1,c2,c3,c4,c5,c6,c7) { c4, c2, c4, c6, \
205 c1, c3, c3, -c7, \
206 c5, c7, -c1, -c5, \
209 c5, -c1, c7, -c5, \
210 c7, c
[all...]
/netgear-R7000-V1.0.7.12_1.2.5/components/opensource/linux/linux-2.6.36/arch/arm/mach-pxa/
H A Dsleep.S92 mcr p14, 0, r0, c7, c0, 0 @ enter sleep
111 mcr p15, 0, r1, c7, c7, 0 @ invalidate I & D caches, BTB
112 mcr p15, 0, r1, c7, c10, 4 @ drain write (&fill) buffer
113 mcr p15, 0, r1, c7, c5, 4 @ flush prefetch buffer
114 mcr p15, 0, r1, c8, c7, 0 @ invalidate I & D TLBs
312 mcr p14, 0, r1, c7, c0, 0 @ PWRMODE
339 mcr p15, 0, r1, c8, c7, 0 @ invalidate I & D TLBs
340 mcr p15, 0, r1, c7, c7,
[all...]
H A Dstandby.S30 1: mcr p14, 0, r2, c7, c0, 0 @ put the system into Standby
64 mcr p14, 0, r0, c7, c0, 0
/netgear-R7000-V1.0.7.12_1.2.5/components/opensource/linux/linux-2.6.36/arch/arm/mach-tegra/
H A Dheadsmp.S41 mcr p15, 0, r5, c7, c6, 2
/netgear-R7000-V1.0.7.12_1.2.5/ap/gpl/timemachine/db-4.7.25.NC/java/src/com/sleepycat/bind/tuple/
H A DTupleInput.java432 long c7 = readFast();
434 if ((c1 | c2 | c3 | c4 | c5 | c6 | c7 | c8) < 0) {
438 (c5 << 24) | (c6 << 16) | (c7 << 8) | c8);
/netgear-R7000-V1.0.7.12_1.2.5/components/opensource/linux/linux-2.6.36/arch/arm/plat-s3c24xx/
H A Dsleep.S130 mcr p15, 0, r1, c8, c7, 0 @@ invalidate I & D TLBs
131 mcr p15, 0, r1, c7, c7, 0 @@ invalidate I & D caches
/netgear-R7000-V1.0.7.12_1.2.5/components/opensource/linux/linux-2.6.36/arch/arm/mach-sa1100/
H A Dsleep.S170 mcr p15, 0, r1, c8, c7, 0 @ flush I+D TLBs
171 mcr p15, 0, r1, c7, c7, 0 @ flush I&D cache

Completed in 108 milliseconds

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