Lines Matching refs:c7
82 mcr p15, 0, r0, c7, c10, 4 @ drain WB
103 mcr p15, 0, ip, c7, c7, 0 @ invalidate I,D caches
104 mcr p15, 0, ip, c7, c10, 4 @ drain WB
106 mcr p15, 0, ip, c8, c7, 0 @ invalidate I & D TLBs
122 mcr p15, 0, r0, c7, c10, 4 @ Drain write buffer
123 mcr p15, 0, r0, c7, c0, 4 @ Wait for interrupt
148 2: mcr p15, 0, ip, c7, c14, 2 @ clean + invalidate D set/way
156 mcrne p15, 0, ip, c7, c5, 0 @ invalidate I cache
157 mcrne p15, 0, ip, c7, c10, 4 @ drain WB
176 mcr p15, 0, r0, c7, c14, 1 @ clean and invalidate D entry
177 mcrne p15, 0, r0, c7, c5, 1 @ invalidate I entry
179 mcr p15, 0, r0, c7, c14, 1 @ clean and invalidate D entry
180 mcrne p15, 0, r0, c7, c5, 1 @ invalidate I entry
186 mcrne p15, 0, ip, c7, c10, 4 @ drain WB
215 1: mcr p15, 0, r0, c7, c10, 1 @ clean D entry
216 mcr p15, 0, r0, c7, c5, 1 @ invalidate I entry
220 mcr p15, 0, r0, c7, c10, 4 @ drain WB
235 1: mcr p15, 0, r0, c7, c14, 1 @ clean+invalidate D entry
240 mcr p15, 0, r0, c7, c5, 0 @ invalidate I cache
241 mcr p15, 0, r0, c7, c10, 4 @ drain WB
254 mcr p15, 0, r0, c7, c5, 0 @ invalidate I cache
255 mcr p15, 0, r0, c7, c10, 4 @ drain WB
275 mcrne p15, 0, r0, c7, c10, 1 @ clean D entry
277 mcrne p15, 0, r1, c7, c10, 1 @ clean D entry
278 1: mcr p15, 0, r0, c7, c6, 1 @ invalidate D entry
282 mcr p15, 0, r0, c7, c10, 4 @ drain WB
289 mcrne p15, 0, r0, c7, c10, 1 @ clean D entry
291 mcrne p15, 0, r1, c7, c10, 1 @ clean D entry
314 1: mcr p15, 0, r0, c7, c10, 1 @ clean D entry
318 mcr p15, 0, r0, c7, c10, 4 @ drain WB
331 mcr p15, 0, r0, c7, c10, 4 @ drain WB
345 1: mcr p15, 0, r0, c7, c14, 1 @ clean+invalidate D entry
349 mcr p15, 0, r0, c7, c10, 4 @ drain WB
362 mcr p15, 0, r0, c7, c10, 4 @ drain WB
432 1: mcr p15, 0, r0, c7, c10, 1 @ clean D entry
443 mcr p15, 0, r0, c7, c10, 4 @ drain WB
468 mcreq p15, 0, ip, c7, c5, 0 @ invalidate I cache
469 mcreq p15, 0, ip, c7, c10, 4 @ drain WB
472 mcr p15, 0, ip, c8, c7, 0 @ invalidate I & D TLBs
488 mcr p15, 0, r0, c7, c10, 1 @ clean D entry
493 mcr p15, 0, r0, c7, c10, 4 @ drain WB
502 mcr p15, 0, r0, c7, c7 @ invalidate I,D caches on v4
503 mcr p15, 0, r0, c7, c10, 4 @ drain write buffer on v4
505 mcr p15, 0, r0, c8, c7 @ invalidate I,D TLBs on v4