Lines Matching refs:c7
358 mcr p15, 0, r0, c6, c7, 0 @ PR7 Area Setting
359 mcr p15, 0, r0, c6, c7, 1
371 mcr p15, 0, r0, c7, c10, 4 @ drain write buffer
372 mcr p15, 0, r0, c7, c5, 0 @ flush(inval) I-Cache
373 mcr p15, 0, r0, c7, c6, 0 @ flush(inval) D-Cache
382 mcr p15, 0, r0, c7, c5, 0 @ flush(inval) I-Cache
383 mcr p15, 0, r0, c7, c6, 0 @ flush(inval) D-Cache
388 mcr p15, 0, r0, c6, c7, 0 @ PR7 Area Setting
398 mcr p15, 0, r0, c7, c0, 0 @ invalidate whole cache v3
411 mcr p15, 0, r0, c7, c0, 0 @ invalidate whole cache v3
458 mcr p15, 0, r0, c7, c10, 4 @ drain write buffer
459 mcr p15, 0, r0, c8, c7, 0 @ flush I,D TLBs
468 mcr p15, 0, r0, c8, c7, 0 @ flush I,D TLBs
479 mcr p15, 0, r0, c7, c10, 4 @ drain write buffer
481 mcrne p15, 0, r0, c8, c7, 0 @ flush I,D TLBs
500 mcr p15, 0, r0, c7, c5, 4 @ ISB
507 mcr p15, 0, r0, c7, c7, 0 @ Invalidate whole cache
508 mcr p15, 0, r0, c7, c10, 4 @ drain write buffer
509 mcr p15, 0, r0, c8, c7, 0 @ flush UTLB
514 mcr p15, 0, r0, c8, c7, 0 @ flush UTLB
521 mcr p15, 0, r0, c7, c0, 0 @ invalidate whole cache v3
796 mcr p15, 0, r0, c7, c10, 4 @ drain write buffer
797 mcr p15, 0, r0, c7, c6, 0 @ flush D-Cache
798 mcr p15, 0, r0, c7, c5, 0 @ flush I-Cache
806 mcr p15, 0, r0, c7, c0, 0 @ invalidate whole cache v3
815 mcr p15, 0, r0, c7, c7 @ invalidate whole cache v4
816 mcr p15, 0, r0, c8, c7 @ invalidate whole TLB v4
832 mcr p15, 0, r0, c8, c7, 0 @ invalidate whole TLB
834 mcr p15, 0, r0, c7, c5, 6 @ invalidate BTC
835 mcr p15, 0, r0, c7, c10, 4 @ DSB
836 mcr p15, 0, r0, c7, c5, 4 @ ISB
850 mcr p15, 0, r0, c7, c0, 0 @ invalidate whole cache v3
870 mcr p15, 0, ip, c7, c6, 0 @ invalidate D cache
873 2: mcr p15, 0, r3, c7, c14, 2 @ clean & invalidate D index
880 mcrne p15, 0, ip, c7, c5, 0 @ invalidate I cache
881 mcr p15, 0, ip, c7, c10, 4 @ drain WB
886 mcr p15, 0, r1, c7, c14, 0 @ clean and invalidate D cache
887 mcr p15, 0, r1, c7, c5, 0 @ flush I cache
888 mcr p15, 0, r1, c7, c10, 4 @ drain WB
893 mcr p15, 0, r1, c7, c14, 0 @ clean+invalidate D
894 mcr p15, 0, r1, c7, c5, 0 @ invalidate I+BTB
895 mcr p15, 0, r1, c7, c15, 0 @ clean+invalidate unified
896 mcr p15, 0, r1, c7, c10, 4 @ drain WB
904 mcr p15, 0, r10, c7, c14, 0 @ clean+invalidate D
907 mcr p15, 0, r10, c7, c10, 5 @ DMB
921 mcr p15, 0, r10, c7, c5, 4 @ isb to sych the new cssr&csidr
939 mcr p15, 0, r11, c7, c14, 2 @ clean & invalidate by set/way
953 mcr p15, 0, r10, c7, c10, 4 @ DSB
954 mcr p15, 0, r10, c7, c5, 0 @ invalidate I+BTB
955 mcr p15, 0, r10, c7, c10, 4 @ DSB
956 mcr p15, 0, r10, c7, c5, 4 @ ISB
960 1: mrc p15, 0, r15, c7, c14, 3 @ test,clean,invalidate D cache
962 mcr p15, 0, r0, c7, c5, 0 @ flush I cache
963 mcr p15, 0, r0, c7, c10, 4 @ drain WB
993 mcr p15, 0, r1, c7, c5, 0 @ flush I cache
994 mcr p15, 0, r1, c7, c6, 0 @ flush D cache
995 mcr p15, 0, r1, c7, c10, 4 @ drain WB
1001 mcr p15, 0, r1, c7, c0, 0 @ invalidate whole cache v3