Searched refs:writel_relaxed (Results 176 - 200 of 698) sorted by relevance

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/linux-master/drivers/irqchip/
H A Dirq-al-fic.c60 writel_relaxed(control, fic->base + AL_FIC_CONTROL);
131 writel_relaxed(BIT(data->hwirq), fic->base + AL_FIC_SET_CAUSE);
214 writel_relaxed(0xFFFFFFFF, fic->base + AL_FIC_MASK);
217 writel_relaxed(0, fic->base + AL_FIC_CAUSE);
219 writel_relaxed(control, fic->base + AL_FIC_CONTROL);
H A Dirq-sun6i-r.c86 writel_relaxed(SUN6I_NMI_BIT, base + SUN6I_IRQ_PENDING(0));
139 writel_relaxed(nmi_src_type, base + SUN6I_NMI_CTRL);
279 writel_relaxed(buf[i], base + SUN6I_IRQ_ENABLE(i));
282 writel_relaxed(buf[i], base + SUN6I_MUX_ENABLE(i));
292 writel_relaxed(SUN6I_NMI_BIT, base + SUN6I_IRQ_ENABLE(0));
294 writel_relaxed(0, base + SUN6I_IRQ_ENABLE(i));
/linux-master/drivers/clk/imx/
H A Dclk-pllv4.c200 writel_relaxed(val, pll->base + pll->cfg_offset);
202 writel_relaxed(mfn, pll->base + pll->num_offset);
203 writel_relaxed(mfd, pll->base + pll->denom_offset);
215 writel_relaxed(val, pll->base);
227 writel_relaxed(val, pll->base);
/linux-master/drivers/mailbox/
H A Drockchip-mailbox.c72 writel_relaxed(msg->cmd, mb->mbox_base + MAILBOX_A2B_CMD(chans->idx));
73 writel_relaxed(msg->rx_size, mb->mbox_base +
84 writel_relaxed((1 << mb->mbox.num_chans) - 1,
96 writel_relaxed(0, mb->mbox_base + MAILBOX_B2A_INTEN);
116 writel_relaxed(1 << idx,
H A Darm_mhuv2.c255 writel_relaxed(_regval, _regptr); \
265 writel_relaxed(BIT(priv->doorbell),
275 writel_relaxed(BIT(priv->doorbell),
283 writel_relaxed(BIT(priv->doorbell),
306 writel_relaxed(BIT(priv->doorbell),
335 writel_relaxed(0xFFFFFFFF, &mhu->recv->ch_wn[i].mask_clear);
345 writel_relaxed(0xFFFFFFFF, &mhu->recv->ch_wn[i].mask_set);
379 writel_relaxed(0xFFFFFFFF, &mhu->recv->ch_wn[idx].stat_clear);
393 writel_relaxed(0x1, &mhu->send->ch_wn[i].int_clr);
394 writel_relaxed(
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H A Dplatform_mhu.c59 writel_relaxed(val, mlink->rx_reg + INTR_CLR_OFS);
77 writel_relaxed(*arg, mlink->tx_reg + INTR_SET_OFS);
89 writel_relaxed(val, mlink->tx_reg + INTR_CLR_OFS);
H A Darm_mhu.c53 writel_relaxed(val, mlink->rx_reg + INTR_CLR_OFS);
71 writel_relaxed(*arg, mlink->tx_reg + INTR_SET_OFS);
83 writel_relaxed(val, mlink->tx_reg + INTR_CLR_OFS);
/linux-master/drivers/hwtracing/coresight/
H A Dcoresight-stm.c155 writel_relaxed(drvdata->stmhebsr, drvdata->base + STMHEBSR);
156 writel_relaxed(drvdata->stmheter, drvdata->base + STMHETER);
157 writel_relaxed(drvdata->stmheer, drvdata->base + STMHEER);
158 writel_relaxed(0x01 | /* Enable HW event tracing */
169 writel_relaxed(0x10,
171 writel_relaxed(drvdata->stmspscr, drvdata->base + STMSPSCR);
172 writel_relaxed(drvdata->stmsper, drvdata->base + STMSPER);
187 writel_relaxed(0xFFF, drvdata->base + STMSYNCR);
188 writel_relaxed((drvdata->traceid << 16 | /* trace id */
223 writel_relaxed(
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/linux-master/sound/soc/sti/
H A Duniperif.h22 writel_relaxed(((readl_relaxed(ip->base + offset) & \
25 writel_relaxed((((value) & mask) << shift), ip->base + offset)
36 writel_relaxed(value, ip->base + UNIPERIF_SOFT_RST_OFFSET(ip))
58 writel_relaxed(value, ip->base + UNIPERIF_FIFO_DATA_OFFSET(ip))
68 writel_relaxed(value, ip->base + \
75 writel_relaxed(value, ip->base + UNIPERIF_CHANNEL_STA_REG0_OFFSET(ip))
81 writel_relaxed(value, ip->base + UNIPERIF_CHANNEL_STA_REG1_OFFSET(ip))
87 writel_relaxed(value, ip->base + UNIPERIF_CHANNEL_STA_REG2_OFFSET(ip))
93 writel_relaxed(value, ip->base + UNIPERIF_CHANNEL_STA_REG3_OFFSET(ip))
99 writel_relaxed(valu
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/linux-master/drivers/gpio/
H A Dgpio-zynq.c292 writel_relaxed(state, gpio->base_addr + reg_offset);
326 writel_relaxed(reg, gpio->base_addr + ZYNQ_GPIO_DIRM_OFFSET(bank_num));
358 writel_relaxed(reg, gpio->base_addr + ZYNQ_GPIO_DIRM_OFFSET(bank_num));
363 writel_relaxed(reg, gpio->base_addr + ZYNQ_GPIO_OUTEN_OFFSET(bank_num));
415 writel_relaxed(BIT(bank_pin_num),
439 writel_relaxed(BIT(bank_pin_num),
459 writel_relaxed(BIT(bank_pin_num),
549 writel_relaxed(int_type,
551 writel_relaxed(int_pol,
553 writel_relaxed(int_an
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H A Dgpio-spear-spics.c76 writel_relaxed(tmp, spics->base + spics->perip_cfg);
100 writel_relaxed(tmp, spics->base + spics->perip_cfg);
114 writel_relaxed(tmp, spics->base + spics->perip_cfg);
/linux-master/drivers/iommu/
H A Dmtk_iommu_v1.c163 writel_relaxed(F_INVLD_EN1 | F_INVLD_EN0,
165 writel_relaxed(F_ALL_INVLD, data->base + REG_MMU_INVALIDATE);
175 writel_relaxed(F_INVLD_EN1 | F_INVLD_EN0,
177 writel_relaxed(iova & F_MMU_FAULT_VA_MSK,
179 writel_relaxed((iova + size - 1) & F_MMU_FAULT_VA_MSK,
181 writel_relaxed(F_MMU_INV_RANGE, data->base + REG_MMU_INVALIDATE);
191 writel_relaxed(0, data->base + REG_MMU_CPE_DONE);
225 writel_relaxed(regval, data->base + REG_MMU_INT_CONTROL);
552 writel_relaxed(regval, data->base + REG_MMU_CTRL_REG);
562 writel_relaxed(regva
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/linux-master/drivers/pci/controller/dwc/
H A Dpcie-qcom-ep.c385 writel_relaxed(val, pcie_ep->parf + PARF_BDF_TO_SID_CFG);
392 writel_relaxed(val, pcie_ep->parf + PARF_DEBUG_INT_EN);
395 writel_relaxed(PARF_DEVICE_TYPE_EP, pcie_ep->parf + PARF_DEVICE_TYPE);
400 writel_relaxed(val, pcie_ep->parf + PARF_PM_CTRL);
405 writel_relaxed(val, pcie_ep->parf + PARF_AXI_MSTR_RD_HALT_NO_WRITES);
410 writel_relaxed(val, pcie_ep->parf + PARF_AXI_MSTR_WR_ADDR_HALT);
415 writel_relaxed(val, pcie_ep->parf + PARF_Q2A_FLUSH);
428 writel_relaxed(val, pcie_ep->parf + PARF_SYS_CTRL);
435 writel_relaxed(val, pcie_ep->parf + PARF_DB_CTRL);
440 writel_relaxed(va
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/linux-master/drivers/clk/mxs/
H A Dclk-ref.c35 writel_relaxed(1 << ((ref->idx + 1) * 8 - 1), ref->reg + CLR);
44 writel_relaxed(1 << ((ref->idx + 1) * 8 - 1), ref->reg + SET);
106 writel_relaxed(val, ref->reg);
/linux-master/drivers/usb/host/
H A Dohci-sa1111.c135 writel_relaxed(usb_rst | USB_RESET_FORCEIFRESET | USB_RESET_FORCEHCRESET,
145 writel_relaxed(usb_rst, dev->mapbase + USB_RESET);
161 writel_relaxed(usb_rst | USB_RESET_FORCEIFRESET | USB_RESET_FORCEHCRESET,
/linux-master/drivers/memory/tegra/
H A Dmc.h131 writel_relaxed(value, mc->bcast_ch_regs + offset);
133 writel_relaxed(value, mc->ch_regs[ch] + offset);
144 writel_relaxed(value, mc->regs + offset);
/linux-master/drivers/clk/
H A Dclk-apple-nco.c83 writel_relaxed(val | CTRL_ENABLE, chan->base + REG_CTRL);
92 writel_relaxed(val & ~CTRL_ENABLE, chan->base + REG_CTRL);
175 writel_relaxed(div, chan->base + REG_DIV);
176 writel_relaxed(inc1, chan->base + REG_INC1);
177 writel_relaxed(inc2, chan->base + REG_INC2);
180 writel_relaxed(1 << 31, chan->base + REG_ACCINIT);
/linux-master/drivers/staging/media/rkvdec/
H A Drkvdec-vp9.c421 writel_relaxed(RKVDEC_VP9_FRAMEWIDTH(ref_buf->vp9.width) |
425 writel_relaxed(vb2_dma_contig_plane_dma_addr(&ref_buf->base.vb.vb2_buf, 0),
435 writel_relaxed(RKVDEC_HOR_Y_VIRSTRIDE(aligned_pitch / 16) |
438 writel_relaxed(RKVDEC_VP9_REF_YSTRIDE(y_len / 16),
444 writel_relaxed(RKVDEC_VP9_REF_YUVSTRIDE(yuv_len / 16),
487 writel_relaxed(val, rkvdec->regs + RKVDEC_VP9_SEGID_GRP(segid));
550 writel_relaxed(RKVDEC_MODE(RKVDEC_MODE_VP9),
563 writel_relaxed(RKVDEC_Y_HOR_VIRSTRIDE(aligned_pitch / 16) |
566 writel_relaxed(RKVDEC_Y_VIRSTRIDE(y_len / 16),
568 writel_relaxed(RKVDEC_YUV_VIRSTRID
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/linux-master/drivers/dma/
H A Dk3dma.c140 writel_relaxed(val, phy->base + CX_CFG);
144 writel_relaxed(val, phy->base + CX_CFG);
155 writel_relaxed(val, d->base + INT_TC1_RAW);
156 writel_relaxed(val, d->base + INT_TC2_RAW);
157 writel_relaxed(val, d->base + INT_ERR1_RAW);
158 writel_relaxed(val, d->base + INT_ERR2_RAW);
163 writel_relaxed(hw->lli, phy->base + CX_LLI);
164 writel_relaxed(hw->count, phy->base + CX_CNT0);
165 writel_relaxed(hw->saddr, phy->base + CX_SRC);
166 writel_relaxed(h
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/linux-master/drivers/dma/qcom/
H A Dbam_dma.c432 writel_relaxed(val, bam_addr(bdev, 0, BAM_CTRL));
434 writel_relaxed(val, bam_addr(bdev, 0, BAM_CTRL));
441 writel_relaxed(val, bam_addr(bdev, 0, BAM_CTRL));
444 writel_relaxed(DEFAULT_CNT_THRSHLD,
448 writel_relaxed(BAM_CNFG_BITS_DEFAULT, bam_addr(bdev, 0, BAM_CNFG_BITS));
451 writel_relaxed(BAM_ERROR_EN | BAM_HRESP_ERR_EN,
455 writel_relaxed(BAM_IRQ_MSK, bam_addr(bdev, 0, BAM_IRQ_SRCS_MSK_EE));
471 writel_relaxed(1, bam_addr(bdev, bchan->id, BAM_P_RST));
472 writel_relaxed(0, bam_addr(bdev, bchan->id, BAM_P_RST));
501 writel_relaxed(ALIG
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/linux-master/drivers/pwm/
H A Dpwm-microchip-core.c88 writel_relaxed(channel_enable, mchp_core_pwm->base + reg_offset);
180 writel_relaxed(posedge, mchp_core_pwm->base + MCHPCOREPWM_POSEDGE(pwm->hwpwm));
181 writel_relaxed(negedge, mchp_core_pwm->base + MCHPCOREPWM_NEGEDGE(pwm->hwpwm));
348 writel_relaxed(prescale, mchp_core_pwm->base + MCHPCOREPWM_PRESCALE);
349 writel_relaxed(period_steps, mchp_core_pwm->base + MCHPCOREPWM_PERIOD);
484 writel_relaxed(1U, mchp_core_pwm->base + MCHPCOREPWM_SYNC_UPD);
/linux-master/drivers/clocksource/
H A Darm_global_timer.c108 writel_relaxed(ctrl, gt_base + GT_CONTROL);
109 writel_relaxed(lower_32_bits(counter), gt_base + GT_COMP0);
110 writel_relaxed(upper_32_bits(counter), gt_base + GT_COMP1);
113 writel_relaxed(delta, gt_base + GT_AUTO_INC);
118 writel_relaxed(ctrl, gt_base + GT_CONTROL);
167 writel_relaxed(GT_INT_STATUS_EVENT_FLAG, gt_base + GT_INT_STATUS);
/linux-master/drivers/watchdog/
H A Drti_wdt.c93 writel_relaxed(timer_margin, wdt->base + RTIDWDPRLD);
105 writel_relaxed(RTIWWDRX_NMI, wdt->base + RTIWWDRXCTRL);
108 writel_relaxed(RTIWWDSIZE_50P, wdt->base + RTIWWDSIZECTRL);
113 writel_relaxed(WDENABLE_KEY, wdt->base + RTIDWDCTRL);
122 writel_relaxed(WDKEY_SEQ0, wdt->base + RTIWDKEY);
124 writel_relaxed(WDKEY_SEQ1, wdt->base + RTIWDKEY);
/linux-master/drivers/clk/hisilicon/
H A Dclkgate-separated.c42 writel_relaxed(reg, sclk->enable);
59 writel_relaxed(reg, sclk->enable + CLKGATE_SEPERATED_DISABLE);
/linux-master/arch/arm/mach-mediatek/
H A Dplatsmp.c69 writel_relaxed(mtk_smp_info->core_keys[cpu-1],
119 writel_relaxed(__pa_symbol(secondary_startup_arm),

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