1// SPDX-License-Identifier: GPL-2.0-only 2/* 3 * IOMMU API for MTK architected m4u v1 implementations 4 * 5 * Copyright (c) 2015-2016 MediaTek Inc. 6 * Author: Honghui Zhang <honghui.zhang@mediatek.com> 7 * 8 * Based on driver/iommu/mtk_iommu.c 9 */ 10#include <linux/bug.h> 11#include <linux/clk.h> 12#include <linux/component.h> 13#include <linux/device.h> 14#include <linux/dma-mapping.h> 15#include <linux/err.h> 16#include <linux/interrupt.h> 17#include <linux/io.h> 18#include <linux/iommu.h> 19#include <linux/iopoll.h> 20#include <linux/list.h> 21#include <linux/module.h> 22#include <linux/of_address.h> 23#include <linux/of_irq.h> 24#include <linux/of_platform.h> 25#include <linux/platform_device.h> 26#include <linux/slab.h> 27#include <linux/spinlock.h> 28#include <asm/barrier.h> 29#include <asm/dma-iommu.h> 30#include <dt-bindings/memory/mtk-memory-port.h> 31#include <dt-bindings/memory/mt2701-larb-port.h> 32#include <soc/mediatek/smi.h> 33 34#define REG_MMU_PT_BASE_ADDR 0x000 35 36#define F_ALL_INVLD 0x2 37#define F_MMU_INV_RANGE 0x1 38#define F_INVLD_EN0 BIT(0) 39#define F_INVLD_EN1 BIT(1) 40 41#define F_MMU_FAULT_VA_MSK 0xfffff000 42#define MTK_PROTECT_PA_ALIGN 128 43 44#define REG_MMU_CTRL_REG 0x210 45#define F_MMU_CTRL_COHERENT_EN BIT(8) 46#define REG_MMU_IVRP_PADDR 0x214 47#define REG_MMU_INT_CONTROL 0x220 48#define F_INT_TRANSLATION_FAULT BIT(0) 49#define F_INT_MAIN_MULTI_HIT_FAULT BIT(1) 50#define F_INT_INVALID_PA_FAULT BIT(2) 51#define F_INT_ENTRY_REPLACEMENT_FAULT BIT(3) 52#define F_INT_TABLE_WALK_FAULT BIT(4) 53#define F_INT_TLB_MISS_FAULT BIT(5) 54#define F_INT_PFH_DMA_FIFO_OVERFLOW BIT(6) 55#define F_INT_MISS_DMA_FIFO_OVERFLOW BIT(7) 56 57#define F_MMU_TF_PROTECT_SEL(prot) (((prot) & 0x3) << 5) 58#define F_INT_CLR_BIT BIT(12) 59 60#define REG_MMU_FAULT_ST 0x224 61#define REG_MMU_FAULT_VA 0x228 62#define REG_MMU_INVLD_PA 0x22C 63#define REG_MMU_INT_ID 0x388 64#define REG_MMU_INVALIDATE 0x5c0 65#define REG_MMU_INVLD_START_A 0x5c4 66#define REG_MMU_INVLD_END_A 0x5c8 67 68#define REG_MMU_INV_SEL 0x5d8 69#define REG_MMU_STANDARD_AXI_MODE 0x5e8 70 71#define REG_MMU_DCM 0x5f0 72#define F_MMU_DCM_ON BIT(1) 73#define REG_MMU_CPE_DONE 0x60c 74#define F_DESC_VALID 0x2 75#define F_DESC_NONSEC BIT(3) 76#define MT2701_M4U_TF_LARB(TF) (6 - (((TF) >> 13) & 0x7)) 77#define MT2701_M4U_TF_PORT(TF) (((TF) >> 8) & 0xF) 78/* MTK generation one iommu HW only support 4K size mapping */ 79#define MT2701_IOMMU_PAGE_SHIFT 12 80#define MT2701_IOMMU_PAGE_SIZE (1UL << MT2701_IOMMU_PAGE_SHIFT) 81#define MT2701_LARB_NR_MAX 3 82 83/* 84 * MTK m4u support 4GB iova address space, and only support 4K page 85 * mapping. So the pagetable size should be exactly as 4M. 86 */ 87#define M2701_IOMMU_PGT_SIZE SZ_4M 88 89struct mtk_iommu_v1_suspend_reg { 90 u32 standard_axi_mode; 91 u32 dcm_dis; 92 u32 ctrl_reg; 93 u32 int_control0; 94}; 95 96struct mtk_iommu_v1_data { 97 void __iomem *base; 98 int irq; 99 struct device *dev; 100 struct clk *bclk; 101 phys_addr_t protect_base; /* protect memory base */ 102 struct mtk_iommu_v1_domain *m4u_dom; 103 104 struct iommu_device iommu; 105 struct dma_iommu_mapping *mapping; 106 struct mtk_smi_larb_iommu larb_imu[MTK_LARB_NR_MAX]; 107 108 struct mtk_iommu_v1_suspend_reg reg; 109}; 110 111struct mtk_iommu_v1_domain { 112 spinlock_t pgtlock; /* lock for page table */ 113 struct iommu_domain domain; 114 u32 *pgt_va; 115 dma_addr_t pgt_pa; 116 struct mtk_iommu_v1_data *data; 117}; 118 119static int mtk_iommu_v1_bind(struct device *dev) 120{ 121 struct mtk_iommu_v1_data *data = dev_get_drvdata(dev); 122 123 return component_bind_all(dev, &data->larb_imu); 124} 125 126static void mtk_iommu_v1_unbind(struct device *dev) 127{ 128 struct mtk_iommu_v1_data *data = dev_get_drvdata(dev); 129 130 component_unbind_all(dev, &data->larb_imu); 131} 132 133static struct mtk_iommu_v1_domain *to_mtk_domain(struct iommu_domain *dom) 134{ 135 return container_of(dom, struct mtk_iommu_v1_domain, domain); 136} 137 138static const int mt2701_m4u_in_larb[] = { 139 LARB0_PORT_OFFSET, LARB1_PORT_OFFSET, 140 LARB2_PORT_OFFSET, LARB3_PORT_OFFSET 141}; 142 143static inline int mt2701_m4u_to_larb(int id) 144{ 145 int i; 146 147 for (i = ARRAY_SIZE(mt2701_m4u_in_larb) - 1; i >= 0; i--) 148 if ((id) >= mt2701_m4u_in_larb[i]) 149 return i; 150 151 return 0; 152} 153 154static inline int mt2701_m4u_to_port(int id) 155{ 156 int larb = mt2701_m4u_to_larb(id); 157 158 return id - mt2701_m4u_in_larb[larb]; 159} 160 161static void mtk_iommu_v1_tlb_flush_all(struct mtk_iommu_v1_data *data) 162{ 163 writel_relaxed(F_INVLD_EN1 | F_INVLD_EN0, 164 data->base + REG_MMU_INV_SEL); 165 writel_relaxed(F_ALL_INVLD, data->base + REG_MMU_INVALIDATE); 166 wmb(); /* Make sure the tlb flush all done */ 167} 168 169static void mtk_iommu_v1_tlb_flush_range(struct mtk_iommu_v1_data *data, 170 unsigned long iova, size_t size) 171{ 172 int ret; 173 u32 tmp; 174 175 writel_relaxed(F_INVLD_EN1 | F_INVLD_EN0, 176 data->base + REG_MMU_INV_SEL); 177 writel_relaxed(iova & F_MMU_FAULT_VA_MSK, 178 data->base + REG_MMU_INVLD_START_A); 179 writel_relaxed((iova + size - 1) & F_MMU_FAULT_VA_MSK, 180 data->base + REG_MMU_INVLD_END_A); 181 writel_relaxed(F_MMU_INV_RANGE, data->base + REG_MMU_INVALIDATE); 182 183 ret = readl_poll_timeout_atomic(data->base + REG_MMU_CPE_DONE, 184 tmp, tmp != 0, 10, 100000); 185 if (ret) { 186 dev_warn(data->dev, 187 "Partial TLB flush timed out, falling back to full flush\n"); 188 mtk_iommu_v1_tlb_flush_all(data); 189 } 190 /* Clear the CPE status */ 191 writel_relaxed(0, data->base + REG_MMU_CPE_DONE); 192} 193 194static irqreturn_t mtk_iommu_v1_isr(int irq, void *dev_id) 195{ 196 struct mtk_iommu_v1_data *data = dev_id; 197 struct mtk_iommu_v1_domain *dom = data->m4u_dom; 198 u32 int_state, regval, fault_iova, fault_pa; 199 unsigned int fault_larb, fault_port; 200 201 /* Read error information from registers */ 202 int_state = readl_relaxed(data->base + REG_MMU_FAULT_ST); 203 fault_iova = readl_relaxed(data->base + REG_MMU_FAULT_VA); 204 205 fault_iova &= F_MMU_FAULT_VA_MSK; 206 fault_pa = readl_relaxed(data->base + REG_MMU_INVLD_PA); 207 regval = readl_relaxed(data->base + REG_MMU_INT_ID); 208 fault_larb = MT2701_M4U_TF_LARB(regval); 209 fault_port = MT2701_M4U_TF_PORT(regval); 210 211 /* 212 * MTK v1 iommu HW could not determine whether the fault is read or 213 * write fault, report as read fault. 214 */ 215 if (report_iommu_fault(&dom->domain, data->dev, fault_iova, 216 IOMMU_FAULT_READ)) 217 dev_err_ratelimited(data->dev, 218 "fault type=0x%x iova=0x%x pa=0x%x larb=%d port=%d\n", 219 int_state, fault_iova, fault_pa, 220 fault_larb, fault_port); 221 222 /* Interrupt clear */ 223 regval = readl_relaxed(data->base + REG_MMU_INT_CONTROL); 224 regval |= F_INT_CLR_BIT; 225 writel_relaxed(regval, data->base + REG_MMU_INT_CONTROL); 226 227 mtk_iommu_v1_tlb_flush_all(data); 228 229 return IRQ_HANDLED; 230} 231 232static void mtk_iommu_v1_config(struct mtk_iommu_v1_data *data, 233 struct device *dev, bool enable) 234{ 235 struct mtk_smi_larb_iommu *larb_mmu; 236 unsigned int larbid, portid; 237 struct iommu_fwspec *fwspec = dev_iommu_fwspec_get(dev); 238 int i; 239 240 for (i = 0; i < fwspec->num_ids; ++i) { 241 larbid = mt2701_m4u_to_larb(fwspec->ids[i]); 242 portid = mt2701_m4u_to_port(fwspec->ids[i]); 243 larb_mmu = &data->larb_imu[larbid]; 244 245 dev_dbg(dev, "%s iommu port: %d\n", 246 enable ? "enable" : "disable", portid); 247 248 if (enable) 249 larb_mmu->mmu |= MTK_SMI_MMU_EN(portid); 250 else 251 larb_mmu->mmu &= ~MTK_SMI_MMU_EN(portid); 252 } 253} 254 255static int mtk_iommu_v1_domain_finalise(struct mtk_iommu_v1_data *data) 256{ 257 struct mtk_iommu_v1_domain *dom = data->m4u_dom; 258 259 spin_lock_init(&dom->pgtlock); 260 261 dom->pgt_va = dma_alloc_coherent(data->dev, M2701_IOMMU_PGT_SIZE, 262 &dom->pgt_pa, GFP_KERNEL); 263 if (!dom->pgt_va) 264 return -ENOMEM; 265 266 writel(dom->pgt_pa, data->base + REG_MMU_PT_BASE_ADDR); 267 268 dom->data = data; 269 270 return 0; 271} 272 273static struct iommu_domain *mtk_iommu_v1_domain_alloc_paging(struct device *dev) 274{ 275 struct mtk_iommu_v1_domain *dom; 276 277 dom = kzalloc(sizeof(*dom), GFP_KERNEL); 278 if (!dom) 279 return NULL; 280 281 return &dom->domain; 282} 283 284static void mtk_iommu_v1_domain_free(struct iommu_domain *domain) 285{ 286 struct mtk_iommu_v1_domain *dom = to_mtk_domain(domain); 287 struct mtk_iommu_v1_data *data = dom->data; 288 289 dma_free_coherent(data->dev, M2701_IOMMU_PGT_SIZE, 290 dom->pgt_va, dom->pgt_pa); 291 kfree(to_mtk_domain(domain)); 292} 293 294static int mtk_iommu_v1_attach_device(struct iommu_domain *domain, struct device *dev) 295{ 296 struct mtk_iommu_v1_data *data = dev_iommu_priv_get(dev); 297 struct mtk_iommu_v1_domain *dom = to_mtk_domain(domain); 298 struct dma_iommu_mapping *mtk_mapping; 299 int ret; 300 301 /* Only allow the domain created internally. */ 302 mtk_mapping = data->mapping; 303 if (mtk_mapping->domain != domain) 304 return 0; 305 306 if (!data->m4u_dom) { 307 data->m4u_dom = dom; 308 ret = mtk_iommu_v1_domain_finalise(data); 309 if (ret) { 310 data->m4u_dom = NULL; 311 return ret; 312 } 313 } 314 315 mtk_iommu_v1_config(data, dev, true); 316 return 0; 317} 318 319static int mtk_iommu_v1_identity_attach(struct iommu_domain *identity_domain, 320 struct device *dev) 321{ 322 struct mtk_iommu_v1_data *data = dev_iommu_priv_get(dev); 323 324 mtk_iommu_v1_config(data, dev, false); 325 return 0; 326} 327 328static struct iommu_domain_ops mtk_iommu_v1_identity_ops = { 329 .attach_dev = mtk_iommu_v1_identity_attach, 330}; 331 332static struct iommu_domain mtk_iommu_v1_identity_domain = { 333 .type = IOMMU_DOMAIN_IDENTITY, 334 .ops = &mtk_iommu_v1_identity_ops, 335}; 336 337static int mtk_iommu_v1_map(struct iommu_domain *domain, unsigned long iova, 338 phys_addr_t paddr, size_t pgsize, size_t pgcount, 339 int prot, gfp_t gfp, size_t *mapped) 340{ 341 struct mtk_iommu_v1_domain *dom = to_mtk_domain(domain); 342 unsigned long flags; 343 unsigned int i; 344 u32 *pgt_base_iova = dom->pgt_va + (iova >> MT2701_IOMMU_PAGE_SHIFT); 345 u32 pabase = (u32)paddr; 346 347 spin_lock_irqsave(&dom->pgtlock, flags); 348 for (i = 0; i < pgcount; i++) { 349 if (pgt_base_iova[i]) 350 break; 351 pgt_base_iova[i] = pabase | F_DESC_VALID | F_DESC_NONSEC; 352 pabase += MT2701_IOMMU_PAGE_SIZE; 353 } 354 355 spin_unlock_irqrestore(&dom->pgtlock, flags); 356 357 *mapped = i * MT2701_IOMMU_PAGE_SIZE; 358 mtk_iommu_v1_tlb_flush_range(dom->data, iova, *mapped); 359 360 return i == pgcount ? 0 : -EEXIST; 361} 362 363static size_t mtk_iommu_v1_unmap(struct iommu_domain *domain, unsigned long iova, 364 size_t pgsize, size_t pgcount, 365 struct iommu_iotlb_gather *gather) 366{ 367 struct mtk_iommu_v1_domain *dom = to_mtk_domain(domain); 368 unsigned long flags; 369 u32 *pgt_base_iova = dom->pgt_va + (iova >> MT2701_IOMMU_PAGE_SHIFT); 370 size_t size = pgcount * MT2701_IOMMU_PAGE_SIZE; 371 372 spin_lock_irqsave(&dom->pgtlock, flags); 373 memset(pgt_base_iova, 0, pgcount * sizeof(u32)); 374 spin_unlock_irqrestore(&dom->pgtlock, flags); 375 376 mtk_iommu_v1_tlb_flush_range(dom->data, iova, size); 377 378 return size; 379} 380 381static phys_addr_t mtk_iommu_v1_iova_to_phys(struct iommu_domain *domain, dma_addr_t iova) 382{ 383 struct mtk_iommu_v1_domain *dom = to_mtk_domain(domain); 384 unsigned long flags; 385 phys_addr_t pa; 386 387 spin_lock_irqsave(&dom->pgtlock, flags); 388 pa = *(dom->pgt_va + (iova >> MT2701_IOMMU_PAGE_SHIFT)); 389 pa = pa & (~(MT2701_IOMMU_PAGE_SIZE - 1)); 390 spin_unlock_irqrestore(&dom->pgtlock, flags); 391 392 return pa; 393} 394 395static const struct iommu_ops mtk_iommu_v1_ops; 396 397/* 398 * MTK generation one iommu HW only support one iommu domain, and all the client 399 * sharing the same iova address space. 400 */ 401static int mtk_iommu_v1_create_mapping(struct device *dev, 402 const struct of_phandle_args *args) 403{ 404 struct iommu_fwspec *fwspec = dev_iommu_fwspec_get(dev); 405 struct mtk_iommu_v1_data *data; 406 struct platform_device *m4updev; 407 struct dma_iommu_mapping *mtk_mapping; 408 int ret; 409 410 if (args->args_count != 1) { 411 dev_err(dev, "invalid #iommu-cells(%d) property for IOMMU\n", 412 args->args_count); 413 return -EINVAL; 414 } 415 416 if (!fwspec) { 417 ret = iommu_fwspec_init(dev, &args->np->fwnode, &mtk_iommu_v1_ops); 418 if (ret) 419 return ret; 420 fwspec = dev_iommu_fwspec_get(dev); 421 } else if (dev_iommu_fwspec_get(dev)->ops != &mtk_iommu_v1_ops) { 422 return -EINVAL; 423 } 424 425 if (!dev_iommu_priv_get(dev)) { 426 /* Get the m4u device */ 427 m4updev = of_find_device_by_node(args->np); 428 if (WARN_ON(!m4updev)) 429 return -EINVAL; 430 431 dev_iommu_priv_set(dev, platform_get_drvdata(m4updev)); 432 } 433 434 ret = iommu_fwspec_add_ids(dev, args->args, 1); 435 if (ret) 436 return ret; 437 438 data = dev_iommu_priv_get(dev); 439 mtk_mapping = data->mapping; 440 if (!mtk_mapping) { 441 /* MTK iommu support 4GB iova address space. */ 442 mtk_mapping = arm_iommu_create_mapping(&platform_bus_type, 443 0, 1ULL << 32); 444 if (IS_ERR(mtk_mapping)) 445 return PTR_ERR(mtk_mapping); 446 447 data->mapping = mtk_mapping; 448 } 449 450 return 0; 451} 452 453static struct iommu_device *mtk_iommu_v1_probe_device(struct device *dev) 454{ 455 struct iommu_fwspec *fwspec = dev_iommu_fwspec_get(dev); 456 struct of_phandle_args iommu_spec; 457 struct mtk_iommu_v1_data *data; 458 int err, idx = 0, larbid, larbidx; 459 struct device_link *link; 460 struct device *larbdev; 461 462 /* 463 * In the deferred case, free the existed fwspec. 464 * Always initialize the fwspec internally. 465 */ 466 if (fwspec) { 467 iommu_fwspec_free(dev); 468 fwspec = dev_iommu_fwspec_get(dev); 469 } 470 471 while (!of_parse_phandle_with_args(dev->of_node, "iommus", 472 "#iommu-cells", 473 idx, &iommu_spec)) { 474 475 err = mtk_iommu_v1_create_mapping(dev, &iommu_spec); 476 of_node_put(iommu_spec.np); 477 if (err) 478 return ERR_PTR(err); 479 480 /* dev->iommu_fwspec might have changed */ 481 fwspec = dev_iommu_fwspec_get(dev); 482 idx++; 483 } 484 485 data = dev_iommu_priv_get(dev); 486 487 /* Link the consumer device with the smi-larb device(supplier) */ 488 larbid = mt2701_m4u_to_larb(fwspec->ids[0]); 489 if (larbid >= MT2701_LARB_NR_MAX) 490 return ERR_PTR(-EINVAL); 491 492 for (idx = 1; idx < fwspec->num_ids; idx++) { 493 larbidx = mt2701_m4u_to_larb(fwspec->ids[idx]); 494 if (larbid != larbidx) { 495 dev_err(dev, "Can only use one larb. Fail@larb%d-%d.\n", 496 larbid, larbidx); 497 return ERR_PTR(-EINVAL); 498 } 499 } 500 501 larbdev = data->larb_imu[larbid].dev; 502 if (!larbdev) 503 return ERR_PTR(-EINVAL); 504 505 link = device_link_add(dev, larbdev, 506 DL_FLAG_PM_RUNTIME | DL_FLAG_STATELESS); 507 if (!link) 508 dev_err(dev, "Unable to link %s\n", dev_name(larbdev)); 509 510 return &data->iommu; 511} 512 513static void mtk_iommu_v1_probe_finalize(struct device *dev) 514{ 515 struct dma_iommu_mapping *mtk_mapping; 516 struct mtk_iommu_v1_data *data; 517 int err; 518 519 data = dev_iommu_priv_get(dev); 520 mtk_mapping = data->mapping; 521 522 err = arm_iommu_attach_device(dev, mtk_mapping); 523 if (err) 524 dev_err(dev, "Can't create IOMMU mapping - DMA-OPS will not work\n"); 525} 526 527static void mtk_iommu_v1_release_device(struct device *dev) 528{ 529 struct iommu_fwspec *fwspec = dev_iommu_fwspec_get(dev); 530 struct mtk_iommu_v1_data *data; 531 struct device *larbdev; 532 unsigned int larbid; 533 534 data = dev_iommu_priv_get(dev); 535 larbid = mt2701_m4u_to_larb(fwspec->ids[0]); 536 larbdev = data->larb_imu[larbid].dev; 537 device_link_remove(dev, larbdev); 538} 539 540static int mtk_iommu_v1_hw_init(const struct mtk_iommu_v1_data *data) 541{ 542 u32 regval; 543 int ret; 544 545 ret = clk_prepare_enable(data->bclk); 546 if (ret) { 547 dev_err(data->dev, "Failed to enable iommu bclk(%d)\n", ret); 548 return ret; 549 } 550 551 regval = F_MMU_CTRL_COHERENT_EN | F_MMU_TF_PROTECT_SEL(2); 552 writel_relaxed(regval, data->base + REG_MMU_CTRL_REG); 553 554 regval = F_INT_TRANSLATION_FAULT | 555 F_INT_MAIN_MULTI_HIT_FAULT | 556 F_INT_INVALID_PA_FAULT | 557 F_INT_ENTRY_REPLACEMENT_FAULT | 558 F_INT_TABLE_WALK_FAULT | 559 F_INT_TLB_MISS_FAULT | 560 F_INT_PFH_DMA_FIFO_OVERFLOW | 561 F_INT_MISS_DMA_FIFO_OVERFLOW; 562 writel_relaxed(regval, data->base + REG_MMU_INT_CONTROL); 563 564 /* protect memory,hw will write here while translation fault */ 565 writel_relaxed(data->protect_base, 566 data->base + REG_MMU_IVRP_PADDR); 567 568 writel_relaxed(F_MMU_DCM_ON, data->base + REG_MMU_DCM); 569 570 if (devm_request_irq(data->dev, data->irq, mtk_iommu_v1_isr, 0, 571 dev_name(data->dev), (void *)data)) { 572 writel_relaxed(0, data->base + REG_MMU_PT_BASE_ADDR); 573 clk_disable_unprepare(data->bclk); 574 dev_err(data->dev, "Failed @ IRQ-%d Request\n", data->irq); 575 return -ENODEV; 576 } 577 578 return 0; 579} 580 581static const struct iommu_ops mtk_iommu_v1_ops = { 582 .identity_domain = &mtk_iommu_v1_identity_domain, 583 .domain_alloc_paging = mtk_iommu_v1_domain_alloc_paging, 584 .probe_device = mtk_iommu_v1_probe_device, 585 .probe_finalize = mtk_iommu_v1_probe_finalize, 586 .release_device = mtk_iommu_v1_release_device, 587 .device_group = generic_device_group, 588 .pgsize_bitmap = MT2701_IOMMU_PAGE_SIZE, 589 .owner = THIS_MODULE, 590 .default_domain_ops = &(const struct iommu_domain_ops) { 591 .attach_dev = mtk_iommu_v1_attach_device, 592 .map_pages = mtk_iommu_v1_map, 593 .unmap_pages = mtk_iommu_v1_unmap, 594 .iova_to_phys = mtk_iommu_v1_iova_to_phys, 595 .free = mtk_iommu_v1_domain_free, 596 } 597}; 598 599static const struct of_device_id mtk_iommu_v1_of_ids[] = { 600 { .compatible = "mediatek,mt2701-m4u", }, 601 {} 602}; 603MODULE_DEVICE_TABLE(of, mtk_iommu_v1_of_ids); 604 605static const struct component_master_ops mtk_iommu_v1_com_ops = { 606 .bind = mtk_iommu_v1_bind, 607 .unbind = mtk_iommu_v1_unbind, 608}; 609 610static int mtk_iommu_v1_probe(struct platform_device *pdev) 611{ 612 struct device *dev = &pdev->dev; 613 struct mtk_iommu_v1_data *data; 614 struct resource *res; 615 struct component_match *match = NULL; 616 void *protect; 617 int larb_nr, ret, i; 618 619 data = devm_kzalloc(dev, sizeof(*data), GFP_KERNEL); 620 if (!data) 621 return -ENOMEM; 622 623 data->dev = dev; 624 625 /* Protect memory. HW will access here while translation fault.*/ 626 protect = devm_kcalloc(dev, 2, MTK_PROTECT_PA_ALIGN, 627 GFP_KERNEL | GFP_DMA); 628 if (!protect) 629 return -ENOMEM; 630 data->protect_base = ALIGN(virt_to_phys(protect), MTK_PROTECT_PA_ALIGN); 631 632 res = platform_get_resource(pdev, IORESOURCE_MEM, 0); 633 data->base = devm_ioremap_resource(dev, res); 634 if (IS_ERR(data->base)) 635 return PTR_ERR(data->base); 636 637 data->irq = platform_get_irq(pdev, 0); 638 if (data->irq < 0) 639 return data->irq; 640 641 data->bclk = devm_clk_get(dev, "bclk"); 642 if (IS_ERR(data->bclk)) 643 return PTR_ERR(data->bclk); 644 645 larb_nr = of_count_phandle_with_args(dev->of_node, 646 "mediatek,larbs", NULL); 647 if (larb_nr < 0) 648 return larb_nr; 649 650 for (i = 0; i < larb_nr; i++) { 651 struct device_node *larbnode; 652 struct platform_device *plarbdev; 653 654 larbnode = of_parse_phandle(dev->of_node, "mediatek,larbs", i); 655 if (!larbnode) 656 return -EINVAL; 657 658 if (!of_device_is_available(larbnode)) { 659 of_node_put(larbnode); 660 continue; 661 } 662 663 plarbdev = of_find_device_by_node(larbnode); 664 if (!plarbdev) { 665 of_node_put(larbnode); 666 return -ENODEV; 667 } 668 if (!plarbdev->dev.driver) { 669 of_node_put(larbnode); 670 return -EPROBE_DEFER; 671 } 672 data->larb_imu[i].dev = &plarbdev->dev; 673 674 component_match_add_release(dev, &match, component_release_of, 675 component_compare_of, larbnode); 676 } 677 678 platform_set_drvdata(pdev, data); 679 680 ret = mtk_iommu_v1_hw_init(data); 681 if (ret) 682 return ret; 683 684 ret = iommu_device_sysfs_add(&data->iommu, &pdev->dev, NULL, 685 dev_name(&pdev->dev)); 686 if (ret) 687 goto out_clk_unprepare; 688 689 ret = iommu_device_register(&data->iommu, &mtk_iommu_v1_ops, dev); 690 if (ret) 691 goto out_sysfs_remove; 692 693 ret = component_master_add_with_match(dev, &mtk_iommu_v1_com_ops, match); 694 if (ret) 695 goto out_dev_unreg; 696 return ret; 697 698out_dev_unreg: 699 iommu_device_unregister(&data->iommu); 700out_sysfs_remove: 701 iommu_device_sysfs_remove(&data->iommu); 702out_clk_unprepare: 703 clk_disable_unprepare(data->bclk); 704 return ret; 705} 706 707static void mtk_iommu_v1_remove(struct platform_device *pdev) 708{ 709 struct mtk_iommu_v1_data *data = platform_get_drvdata(pdev); 710 711 iommu_device_sysfs_remove(&data->iommu); 712 iommu_device_unregister(&data->iommu); 713 714 clk_disable_unprepare(data->bclk); 715 devm_free_irq(&pdev->dev, data->irq, data); 716 component_master_del(&pdev->dev, &mtk_iommu_v1_com_ops); 717} 718 719static int __maybe_unused mtk_iommu_v1_suspend(struct device *dev) 720{ 721 struct mtk_iommu_v1_data *data = dev_get_drvdata(dev); 722 struct mtk_iommu_v1_suspend_reg *reg = &data->reg; 723 void __iomem *base = data->base; 724 725 reg->standard_axi_mode = readl_relaxed(base + 726 REG_MMU_STANDARD_AXI_MODE); 727 reg->dcm_dis = readl_relaxed(base + REG_MMU_DCM); 728 reg->ctrl_reg = readl_relaxed(base + REG_MMU_CTRL_REG); 729 reg->int_control0 = readl_relaxed(base + REG_MMU_INT_CONTROL); 730 return 0; 731} 732 733static int __maybe_unused mtk_iommu_v1_resume(struct device *dev) 734{ 735 struct mtk_iommu_v1_data *data = dev_get_drvdata(dev); 736 struct mtk_iommu_v1_suspend_reg *reg = &data->reg; 737 void __iomem *base = data->base; 738 739 writel_relaxed(data->m4u_dom->pgt_pa, base + REG_MMU_PT_BASE_ADDR); 740 writel_relaxed(reg->standard_axi_mode, 741 base + REG_MMU_STANDARD_AXI_MODE); 742 writel_relaxed(reg->dcm_dis, base + REG_MMU_DCM); 743 writel_relaxed(reg->ctrl_reg, base + REG_MMU_CTRL_REG); 744 writel_relaxed(reg->int_control0, base + REG_MMU_INT_CONTROL); 745 writel_relaxed(data->protect_base, base + REG_MMU_IVRP_PADDR); 746 return 0; 747} 748 749static const struct dev_pm_ops mtk_iommu_v1_pm_ops = { 750 SET_SYSTEM_SLEEP_PM_OPS(mtk_iommu_v1_suspend, mtk_iommu_v1_resume) 751}; 752 753static struct platform_driver mtk_iommu_v1_driver = { 754 .probe = mtk_iommu_v1_probe, 755 .remove_new = mtk_iommu_v1_remove, 756 .driver = { 757 .name = "mtk-iommu-v1", 758 .of_match_table = mtk_iommu_v1_of_ids, 759 .pm = &mtk_iommu_v1_pm_ops, 760 } 761}; 762module_platform_driver(mtk_iommu_v1_driver); 763 764MODULE_DESCRIPTION("IOMMU API for MediaTek M4U v1 implementations"); 765MODULE_LICENSE("GPL v2"); 766