Searched refs:uint32_t (Results 676 - 700 of 3113) sorted by relevance

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/linux-master/drivers/scsi/csiostor/
H A Dcsio_hw_chip.h121 int (*chip_set_mem_win)(struct csio_hw *, uint32_t);
123 uint32_t (*chip_flash_cfg_addr)(struct csio_hw *);
124 int (*chip_mc_read)(struct csio_hw *, int, uint32_t,
126 int (*chip_edc_read)(struct csio_hw *, int, uint32_t,
129 u32, uint32_t *, int);
/linux-master/include/xen/interface/io/
H A Dkbdif.h276 * keycode - uint32_t, KEY_* from linux/input.h
282 uint32_t keycode;
473 uint32_t major; /* length of the major axis, pixels */
474 uint32_t minor; /* length of the minor axis, pixels */
539 uint32_t in_cons, in_prod;
540 uint32_t out_cons, out_prod;
H A Dblkif.h198 uint32_t _pad1; /* offsetof(blkif_request,u.rw.id) == 8 */
210 uint32_t _pad2; /* offsetof(blkif_req..,u.discard.id)==8*/
222 uint32_t _pad3; /* offsetof(blkif_req..,u.other.id)==8*/
231 uint32_t _pad1; /* offsetof(blkif_...,u.indirect.id) == 8 */
239 uint32_t _pad3; /* make it 64 byte aligned */
/linux-master/drivers/gpu/drm/vmwgfx/
H A Dvmwgfx_fence.h98 uint32_t seqno,
103 uint32_t sequence,
105 uint32_t *p_handle);
124 uint32_t *tv_sec,
125 uint32_t *tv_usec,
/linux-master/tools/testing/selftests/kvm/include/x86_64/
H A Dapic.h68 static inline uint32_t get_bsp_flag(void)
73 static inline uint32_t xapic_read_reg(unsigned int reg)
75 return ((volatile uint32_t *)APIC_DEFAULT_GPA)[reg >> 2];
78 static inline void xapic_write_reg(unsigned int reg, uint32_t val)
80 ((volatile uint32_t *)APIC_DEFAULT_GPA)[reg >> 2] = val;
/linux-master/drivers/md/
H A Ddm-cache-metadata.h93 uint32_t hint, bool hint_valid);
103 uint32_t read_hits;
104 uint32_t read_misses;
105 uint32_t write_hits;
106 uint32_t write_misses;
/linux-master/drivers/gpu/drm/amd/display/dc/hwss/dce112/
H A Ddce112_hwseq.c38 uint32_t crtc;
71 uint32_t addr;
72 uint32_t value = 0;
73 uint32_t chunk_int = 0;
74 uint32_t chunk_mul = 0;
/linux-master/drivers/staging/media/atomisp/pci/runtime/isys/interface/
H A Dia_css_isys.h53 uint32_t isys_stream_id);
68 uint32_t isys_stream_id);
115 uint32_t isys_stream_id);
145 uint32_t *start_addr);
148 uint32_t *start_addr);
/linux-master/arch/powerpc/include/asm/
H A Dhvsi.h75 ssize_t (*get_chars)(uint32_t termno, u8 *buf, size_t count);
76 ssize_t (*put_chars)(uint32_t termno, const u8 *buf, size_t count);
77 uint32_t termno;
83 ssize_t (*get_chars)(uint32_t termno, u8 *buf,
85 ssize_t (*put_chars)(uint32_t termno, const u8 *buf,
/linux-master/drivers/gpu/drm/amd/amdgpu/
H A Dathub_v3_0.c37 static uint32_t athub_v3_0_get_cg_cntl(struct amdgpu_device *adev)
39 uint32_t data;
55 static void athub_v3_0_set_cg_cntl(struct amdgpu_device *adev, uint32_t data)
74 uint32_t def, data;
91 uint32_t def, data;
H A Dsdma_v4_4.c36 static uint32_t sdma_v4_4_get_reg_offset(struct amdgpu_device *adev,
37 uint32_t instance,
38 uint32_t offset)
40 uint32_t sdma_base = adev->reg_offset[SDMA0_HWIP][0][0];
167 uint32_t reg_offset,
168 uint32_t value,
169 uint32_t instance,
170 uint32_t *sec_count)
172 uint32_t i;
173 uint32_t sec_cn
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H A Damdgpu.h126 uint32_t num_gpu;
127 uint32_t num_dgpu;
128 uint32_t num_apu;
152 uint32_t period; /* maxCycles = (1 << period), the number of cycles before a timeout */
414 uint32_t default_mclk;
415 uint32_t default_sclk;
416 uint32_t default_dispclk;
417 uint32_t current_dispclk;
418 uint32_t dp_extclk;
419 uint32_t max_pixel_cloc
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H A Ddf_v3_6.c46 uint32_t ficaa_val)
49 uint32_t ficadl_val, ficadh_val;
69 static void df_v3_6_set_fica(struct amdgpu_device *adev, uint32_t ficaa_val,
70 uint32_t ficadl_val, uint32_t ficadh_val)
97 uint32_t lo_addr, uint32_t *lo_val,
98 uint32_t hi_addr, uint32_t *hi_val)
119 static void df_v3_6_perfmon_wreg(struct amdgpu_device *adev, uint32_t lo_add
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H A Damdgpu_psp.h100 uint32_t ring_size;
101 uint32_t ring_wptr;
132 int (*mem_training)(struct psp_context *psp, uint32_t ops);
133 uint32_t (*ring_get_wptr)(struct psp_context *psp);
134 void (*ring_set_wptr)(struct psp_context *psp, uint32_t value);
136 int (*read_usbc_pd_fw)(struct psp_context *psp, uint32_t *fw_ver);
145 int (*fn_ta_invoke)(struct psp_context *psp, uint32_t ta_cmd_id);
160 uint32_t num_nodes;
165 uint32_t fw_version;
166 uint32_t feature_versio
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/linux-master/drivers/gpu/drm/amd/include/
H A Damdgpu_reg_state.h63 uint32_t value;
64 uint32_t pad;
106 uint32_t sub_bus_number_latency;
107 uint32_t pcie_corr_err_status;
108 uint32_t pcie_uncorr_err_status;
/linux-master/include/drm/ttm/
H A Dttm_tt.h99 uint32_t page_flags;
101 uint32_t num_pages;
158 uint32_t page_flags, enum ttm_caching caching,
161 uint32_t page_flags, enum ttm_caching caching);
250 uint32_t page_flags);
/linux-master/include/keys/
H A Dtrusted_tpm.h13 #define LOAD32(buffer, offset) (ntohl(*(uint32_t *)&buffer[offset]))
14 #define LOAD32N(buffer, offset) (*(uint32_t *)&buffer[offset])
20 uint32_t handle;
35 const uint32_t command,
41 int oiap(struct tpm_buf *tb, uint32_t *handle, unsigned char *nonce);
/linux-master/drivers/gpu/drm/amd/display/dc/link/protocols/
H A Dlink_ddc.c61 uint32_t count)
75 static uint32_t i2c_payloads_get_count(struct i2c_payloads *p)
92 uint32_t address,
93 uint32_t len,
97 uint32_t payload_size = EDID_SEGMENT_SIZE;
98 uint32_t pos;
215 static uint32_t defer_delay_converter_wa(
217 uint32_t defer_delay)
251 uint32_t link_get_aux_defer_delay(struct ddc_service *ddc)
253 uint32_t defer_dela
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/linux-master/drivers/video/fbdev/geode/
H A Dlxfb.h42 uint32_t gp[GP_REG_COUNT];
43 uint32_t dc[DC_REG_COUNT];
47 uint32_t dc_pal[DC_PAL_COUNT];
48 uint32_t vp_pal[VP_PAL_COUNT];
49 uint32_t hcoeff[DC_HFILT_COUNT * 2];
50 uint32_t vcoeff[DC_VFILT_COUNT];
51 uint32_t vp_coeff[VP_COEFF_SIZE / 4];
376 static inline uint32_t read_gp(struct lxfb_par *par, int reg)
381 static inline void write_gp(struct lxfb_par *par, int reg, uint32_t val)
386 static inline uint32_t read_d
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/linux-master/drivers/gpu/drm/amd/display/dc/dcn10/
H A Ddcn10_ipp.h179 IPP_DCN10_REG_FIELD_LIST(uint32_t);
183 uint32_t CURSOR_SETTINS;
184 uint32_t CURSOR_SETTINGS;
185 uint32_t CNVC_SURFACE_PIXEL_FORMAT;
186 uint32_t CURSOR0_CONTROL;
187 uint32_t CURSOR0_COLOR0;
188 uint32_t CURSOR0_COLOR1;
189 uint32_t FORMAT_CONTROL;
190 uint32_t CURSOR_SURFACE_ADDRESS_HIGH;
191 uint32_t CURSOR_SURFACE_ADDRES
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H A Ddcn10_opp.h54 uint32_t FMT_BIT_DEPTH_CONTROL; \
55 uint32_t FMT_CONTROL; \
56 uint32_t FMT_DITHER_RAND_R_SEED; \
57 uint32_t FMT_DITHER_RAND_G_SEED; \
58 uint32_t FMT_DITHER_RAND_B_SEED; \
59 uint32_t FMT_CLAMP_CNTL; \
60 uint32_t FMT_DYNAMIC_EXP_CNTL; \
61 uint32_t FMT_MAP420_MEMORY_CONTROL; \
62 uint32_t OPPBUF_CONTROL; \
63 uint32_t OPPBUF_CONTROL
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/linux-master/drivers/gpu/drm/amd/pm/legacy-dpm/
H A Dsi_dpm.h284 uint32_t value[SMC_EVERGREEN_MC_REGISTER_ARRAY_SIZE];
301 uint32_t value[SMC_NISLANDS_MC_REGISTER_ARRAY_SIZE];
367 uint32_t vCG_SPLL_FUNC_CNTL;
368 uint32_t vCG_SPLL_FUNC_CNTL_2;
369 uint32_t vCG_SPLL_FUNC_CNTL_3;
370 uint32_t vCG_SPLL_SPREAD_SPECTRUM;
371 uint32_t vCG_SPLL_SPREAD_SPECTRUM_2;
372 uint32_t sclk_value;
379 uint32_t vMPLL_AD_FUNC_CNTL;
380 uint32_t vMPLL_AD_FUNC_CNTL_
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/linux-master/include/drm/
H A Ddrm_crtc.h437 uint32_t handle, uint32_t width, uint32_t height);
459 uint32_t handle, uint32_t width, uint32_t height,
494 uint32_t size,
579 uint32_t flags,
598 uint32_t flags, uint32_t targe
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/linux-master/drivers/gpu/drm/amd/display/dc/dce112/
H A Ddce112_compressor.c64 static const uint32_t dce11_one_lpt_channel_max_resolution = 2560 * 1600;
98 static uint32_t lpt_size_alignment(struct dce112_compressor *cp110)
105 static uint32_t lpt_memory_control_config(struct dce112_compressor *cp110,
106 uint32_t lpt_control)
270 uint32_t source_view_width,
271 uint32_t source_view_height)
283 static uint32_t align_to_chunks_number_per_line(
285 uint32_t pixels)
295 uint32_t addr = mmFBC_STATUS;
296 uint32_t valu
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/linux-master/drivers/hid/intel-ish-hid/ipc/
H A Dipc.c30 static inline uint32_t ish_reg_read(const struct ishtp_device *dev,
48 uint32_t value)
63 static inline uint32_t _ish_read_fw_sts_reg(struct ishtp_device *dev)
79 uint32_t pisr_val = 0;
106 uint32_t doorbell_val;
132 uint32_t host_comm_val;
139 uint32_t host_pimr_val;
163 uint32_t ish_status = _ish_read_fw_sts_reg(dev);
177 uint32_t host_status = ish_reg_read(dev, IPC_REG_HOST_COMM);
191 uint32_t host_statu
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