Searched refs:lanes (Results 76 - 100 of 281) sorted by relevance

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/linux-master/drivers/net/ethernet/netronome/nfp/nfpcore/
H A Dnfp_nsp_eth.c146 dst->lanes = FIELD_GET(NSP_ETH_PORT_LANES, port);
153 dst->speed = dst->lanes * rate;
210 table->ports[i].port_lanes += table->ports[j].lanes;
429 * Enable or disable PHY module (this usually means setting the TX lanes
726 * by number of lanes this subport is spanning (i.e. 10000 for 40G, 25000 for
752 * @lanes: Desired lanes per port
754 * Set number of lanes in the port.
759 int __nfp_eth_set_split(struct nfp_nsp *nsp, unsigned int lanes) argument
762 lanes, NSP_ETH_CTRL_SET_LANE
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/linux-master/drivers/media/platform/cadence/
H A Dcdns-csi2tx.c115 u8 lanes[CSI2TX_LANES_MAX]; member in struct:csi2tx_priv
249 /* Enable our (clock and data) lanes */
252 reg |= CSI2TX_DPHY_CFG_LANE_ENABLE(csi2tx->lanes[i] - 1);
271 /* Put our lanes (clock and data) out of reset */
274 reg |= CSI2TX_DPHY_CFG_LANE_RESET(csi2tx->lanes[i] - 1);
287 /* Put our lanes (clock and data) out of reset */
467 dev_err(&pdev->dev, "Invalid number of lanes: %u\n",
522 "Current configuration uses more lanes than supported\n");
536 memcpy(csi2tx->lanes, v4l2_ep.bus.mipi_csi2.data_lanes,
537 sizeof(csi2tx->lanes));
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/linux-master/drivers/media/pci/intel/
H A Dipu-bridge.c75 .data_lanes = "data-lanes",
292 if (ssdb.lanes > IPU_MAX_LANES) {
293 dev_err(ADEV_DEV(adev), "Number of lanes in SSDB is invalid\n");
298 sensor->lanes = ssdb.lanes;
336 sensor->lanes);
347 sensor->lanes);
379 bridge->data_lanes, sensor->lanes);
392 bridge->data_lanes, sensor->lanes);
/linux-master/drivers/gpu/drm/i915/display/
H A Dintel_audio.c429 unsigned int link_clk, lanes; local
440 lanes = crtc_state->lane_count;
443 "h_active = %u link_clk = %u : lanes = %u vdsc_bpp = " BPP_X16_FMT " cdclk = %u\n",
444 h_active, link_clk, lanes, BPP_X16_ARGS(vdsc_bppx16), cdclk);
446 if (WARN_ON(!link_clk || !pixel_clk || !lanes || !vdsc_bppx16 || !cdclk))
450 link_clks_required = DIV_ROUND_UP(192000 * h_total, 1000 * pixel_clk) * (48 / lanes + 2);
459 mul_u32_u32(link_clk * lanes * 16, fec_coeff));
472 unsigned int link_clk, lanes; local
478 lanes = crtc_state->lane_count;
481 (pixel_clk * (48 / lanes
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/linux-master/drivers/gpu/drm/nouveau/nvkm/engine/disp/
H A Dg94.c68 const u32 shift = sor->func->dp->lanes[ln] * 8;
110 mask |= 1 << sor->func->dp->lanes[i];
142 .lanes = { 2, 1, 0, 3},
H A Doutp.h113 int (*drive)(struct nvkm_outp *, u8 lanes, u8 pe[4], u8 vs[4]);
H A Dga102.c74 .lanes = { 0, 1, 2, 3 },
/linux-master/drivers/phy/qualcomm/
H A Dphy-qcom-qmp-ufs.c913 int lanes; member in struct:qmp_phy_cfg
1008 .lanes = 1,
1031 .lanes = 2,
1065 .lanes = 2,
1099 .lanes = 2,
1133 .lanes = 2,
1160 .lanes = 1,
1187 .lanes = 1,
1214 .lanes = 2,
1248 .lanes
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H A Dphy-qcom-qmp-pcie.c2353 int lanes; member in struct:qmp_phy_cfg
2564 .lanes = 1,
2589 .lanes = 1,
2618 .lanes = 1,
2645 .lanes = 1,
2672 .lanes = 1,
2695 .lanes = 1,
2732 .lanes = 2,
2769 .lanes = 1,
2796 .lanes
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/linux-master/drivers/media/i2c/ccs/
H A Dccs-quirk.c196 sensor->pll.op_lanes = sensor->pll.csi2.lanes;
/linux-master/drivers/pci/controller/
H A Dpci-tegra.c368 unsigned int lanes; member in struct:tegra_pcie_port
917 /* initialize internal PHY, enable up to 16 PCIE lanes */
920 /* override IDDQ to 1 on all 4 lanes */
997 for (i = 0; i < port->lanes; i++) {
1014 for (i = 0; i < port->lanes; i++) {
1346 port->phys = devm_kcalloc(dev, sizeof(phy), port->lanes, GFP_KERNEL);
1350 for (i = 0; i < port->lanes; i++) {
1404 for (i = 0; i < port->lanes; i++) {
1855 static int tegra_pcie_get_xbar_config(struct tegra_pcie *pcie, u32 lanes, argument
1862 switch (lanes) {
2117 u32 lanes = 0, mask = 0; local
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/linux-master/drivers/phy/amlogic/
H A Dphy-meson-g12a-mipi-dphy-analog.c78 switch (priv->config.lanes) {
/linux-master/drivers/ufs/host/
H A Dufshcd-pci.c142 static int ufs_intel_set_lanes(struct ufs_hba *hba, u32 lanes) argument
147 pwr_info.lane_rx = lanes;
148 pwr_info.lane_tx = lanes;
151 dev_err(hba->dev, "%s: Setting %u lanes, err = %d\n",
152 __func__, lanes, ret);
/linux-master/drivers/edac/
H A Dppc4xx_edac.c424 unsigned int lane, lanes; local
437 for (lanes = 0, lane = first_lane; lane < lane_count; lane++) {
441 (lanes++ ? ", " : ""), lane);
452 n = snprintf(buffer, size, "%s; ", lanes ? "" : "None");
/linux-master/drivers/gpu/drm/bridge/
H A Dti-sn65dsi83.c308 ctx->dsi->lanes / 2, 40000U, 500000U), 5000U);
316 dsi_div /= ctx->dsi->lanes;
404 /* Set number of DSI lanes and LVDS link config. */
407 REG_DSI_LANE_CHA_DSI_LANES(~(ctx->dsi->lanes - 1)) |
655 dsi->lanes = dsi_lanes;
/linux-master/drivers/gpu/drm/panel/
H A Dpanel-mantix-mlaf057we51.c282 dsi->lanes = 4;
318 mipi_dsi_pixel_format_to_bpp(dsi->format), dsi->lanes);
H A Dpanel-sitronix-st7703.c70 unsigned int lanes; member in struct:st7703_panel_desc
156 .lanes = 4,
175 0x33, /* VC_main = 0, Lane_Number = 3 (4 lanes) */
339 .lanes = 4,
430 .lanes = 4,
518 .lanes = 4,
608 .lanes = 4,
694 .lanes = 2,
904 dsi->lanes = ctx->desc->lanes;
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/linux-master/drivers/phy/rockchip/
H A Dphy-rockchip-dphy-rx0.c198 GENMASK(priv->config.lanes - 1, 0));
243 dev_dbg(priv->dev, "lanes %d - data_rate_mbps %llu\n",
244 config->lanes, data_rate_mbps);
/linux-master/drivers/gpu/drm/meson/
H A Dmeson_dw_mipi_dsi.c159 unsigned long mode_flags, u32 lanes, u32 format,
170 bpp, mipi_dsi->dsi_device->lanes,
158 dw_mipi_dsi_get_lane_mbps(void *priv_data, const struct drm_display_mode *mode, unsigned long mode_flags, u32 lanes, u32 format, unsigned int *lane_mbps) argument
/linux-master/drivers/media/i2c/
H A Dccs-pll.c485 * Take scaling factor and number of VT lanes into account as well.
496 pll->csi2.lanes : 1)
682 / PHY_CONST_DIV / pll->csi2.lanes / l)
761 (pll->csi2.lanes * l << op_pix_ddr(pll->flags))) {
762 dev_dbg(dev, "op_pix_clk_div not an integer (bpp %u, op lanes %u, lanes %u, l %u)\n",
763 pll->bits_per_pixel, pll->op_lanes, pll->csi2.lanes, l);
778 1 : pll->csi2.lanes);
787 pll->csi2.lanes : 1) * PHY_CONST_DIV,
H A Dimx219.c336 /* Two or Four lanes */
337 u8 lanes; member in struct:imx219
460 return (imx219->lanes == 2) ? IMX219_PIXEL_RATE : IMX219_PIXEL_RATE_4LANE;
489 (imx219->lanes == 2) ? imx219_link_freq_menu :
667 imx219->lanes == 2 ? IMX219_CSI_2_LANE_MODE :
692 dev_err(&client->dev, "%s failed to configure lanes\n", __func__);
1056 /* Check the number of MIPI CSI2 data lanes */
1060 "only 2 or 4 data lanes are currently supported\n");
1063 imx219->lanes = ep_cfg.bus.mipi_csi2.num_data_lanes;
1073 (ep_cfg.link_frequencies[0] != ((imx219->lanes
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H A Dtc358743.c533 /* Mute video so that all data lanes go to LSP11 state.
683 unsigned lanes = tc358743_num_csi_lanes_needed(sd); local
687 state->csi_lanes_in_use = lanes;
691 if (lanes < 1)
693 if (lanes < 1)
695 if (lanes < 2)
697 if (lanes < 3)
699 if (lanes < 4)
713 ((lanes > 0) ? MASK_CLM_HSTXVREGEN : 0x0) |
714 ((lanes >
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/linux-master/drivers/phy/tegra/
H A Dxusb-tegra124.c438 usb2->base.soc = &pad->soc->lanes[index];
662 .lanes = tegra124_usb2_lanes,
687 ulpi->base.soc = &pad->soc->lanes[index];
797 .lanes = tegra124_ulpi_lanes,
823 hsic->base.soc = &pad->soc->lanes[index];
1013 .lanes = tegra124_hsic_lanes,
1043 pcie->base.soc = &pad->soc->lanes[index];
1201 .lanes = tegra124_pcie_lanes,
1221 sata->base.soc = &pad->soc->lanes[index];
1397 .lanes
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/linux-master/drivers/thunderbolt/
H A Dusb4.c1626 * @lanes: Which lanes to run (must match the port capabilities). Can be
1636 int usb4_port_hw_margin(struct tb_port *port, unsigned int lanes, argument
1643 val = lanes;
1669 * @lanes: Which lanes to run (must match the port capabilities). Can be
1679 int usb4_port_sw_margin(struct tb_port *port, unsigned int lanes, bool timing, argument
1685 val = lanes;
2550 * usb4_dp_port_nrd() - Read non-reduced rate and lanes
2553 * @lanes
2559 usb4_dp_port_nrd(struct tb_port *port, int *rate, int *lanes) argument
2615 usb4_dp_port_set_nrd(struct tb_port *port, int rate, int lanes) argument
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/linux-master/drivers/gpu/drm/tegra/
H A Dsor.c646 static int tegra_sor_power_up_lanes(struct tegra_sor *sor, unsigned int lanes) argument
657 if (lanes <= 2)
664 if (lanes <= 1)
669 if (lanes == 0)
702 /* power down all lanes */
729 static void tegra_sor_dp_precharge(struct tegra_sor *sor, unsigned int lanes) argument
733 /* pre-charge all used lanes */
736 if (lanes <= 2)
743 if (lanes <= 1)
748 if (lanes
878 unsigned int rate, lanes; local
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