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697bef6c |
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01-Aug-2023 |
Sakari Ailus <sakari.ailus@linux.intel.com> |
media: ccs-pll: Initialise best_div to avoid a compiler warning Initialise best_div local variable to avoid a compiler warning. The warning was harmless though. Reported-by: Hans Verkuil <hverkuil-cisco@xs4all.nl> Signed-off-by: Sakari Ailus <sakari.ailus@linux.intel.com> Signed-off-by: Hans Verkuil <hverkuil-cisco@xs4all.nl>
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ca59318b |
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07-Dec-2020 |
Sakari Ailus <sakari.ailus@linux.intel.com> |
media: Revert "media: ccs-pll: Fix MODULE_LICENSE" This reverts commit b3c0115e34adcabe12fce8845e24ca6f04c1554e. As per Documentation/process/license-rules.rst "GPL v2" exists only for historical reasons and has the same meaning as "GPL". So revert this patch. Signed-off-by: Sakari Ailus <sakari.ailus@linux.intel.com> Signed-off-by: Mauro Carvalho Chehab <mchehab+huawei@kernel.org>
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8a75e8dc |
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26-Nov-2020 |
Sakari Ailus <sakari.ailus@linux.intel.com> |
media: ccs-pll: Switch from standard integer types to kernel ones The preferred integer types in the kernel are the Linux specific ones, switch from standard C types to u32 and alike. The patch has been produced with the following Coccinelle spatch, with few alignment adjustments: @@ typedef uint32_t; typedef u32; @@ - uint32_t + u32 @@ typedef uint16_t; typedef u16; @@ - uint16_t + u16 @@ typedef uint8_t; typedef u8; @@ - uint8_t + u8 Signed-off-by: Sakari Ailus <sakari.ailus@linux.intel.com> Signed-off-by: Mauro Carvalho Chehab <mchehab+huawei@kernel.org>
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ff474acc |
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11-Dec-2020 |
Sakari Ailus <sakari.ailus@linux.intel.com> |
media: ccs-pll: Fix link frequency for C-PHY The highest fundamental frequency signal for C-PHY is half of the symbol rate which is similar to D-PHY. Take this into account in ccs-pll. Also remove the outdated comment. Fixes: 8030aa4f9c51 ("media: ccs-pll: Add C-PHY support") Signed-off-by: Sakari Ailus <sakari.ailus@linux.intel.com> Signed-off-by: Mauro Carvalho Chehab <mchehab+huawei@kernel.org>
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bd189aac |
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23-Sep-2020 |
Sakari Ailus <sakari.ailus@linux.intel.com> |
media: ccs-pll: Print pixel rates Print pixel rates on CSI-2 bus as well as in pixel array as the variation allowed in PLL capabilities makes this non-trivial to figure out otherwise. Signed-off-by: Sakari Ailus <sakari.ailus@linux.intel.com> Signed-off-by: Mauro Carvalho Chehab <mchehab+huawei@kernel.org>
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900c33e8 |
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24-Aug-2020 |
Sakari Ailus <sakari.ailus@linux.intel.com> |
media: ccs-pll: Add support for DDR OP system and pixel clocks Add support for dual data rate operational system and pixel clocks. This is implemented using two PLL flags. Signed-off-by: Sakari Ailus <sakari.ailus@linux.intel.com> Signed-off-by: Mauro Carvalho Chehab <mchehab+huawei@kernel.org>
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b41f2708 |
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16-Sep-2020 |
Sakari Ailus <sakari.ailus@linux.intel.com> |
media: ccs: Dual PLL support Add support for sensors that either require dual PLL or support single or dual PLL but use dual PLL as default. Use sensor default configuration for sensors that support both modes. Signed-off-by: Sakari Ailus <sakari.ailus@linux.intel.com> Signed-off-by: Mauro Carvalho Chehab <mchehab+huawei@kernel.org>
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6c7469e4 |
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15-Sep-2020 |
Sakari Ailus <sakari.ailus@linux.intel.com> |
media: ccs-pll: Add trivial dual PLL support Add support for sensors that have separate VT and OP domain PLLs. This support is trivial in the sense that it aims for the same VT pixel rate than that on the CSI-2 bus. The vast majority of sensors is better supported by higher frequencies in VT domain in binned and possibly scaled configurations. Signed-off-by: Sakari Ailus <sakari.ailus@linux.intel.com> Signed-off-by: Mauro Carvalho Chehab <mchehab+huawei@kernel.org>
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9ec6e5b1 |
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15-Sep-2020 |
Sakari Ailus <sakari.ailus@linux.intel.com> |
media: ccs-pll: Separate VT divisor limit calculation from the rest Separate VT divisor limit calculation from the rest of the VT PLL branch calculation. This way it can be used for dual PLL support as well. Signed-off-by: Sakari Ailus <sakari.ailus@linux.intel.com> Signed-off-by: Mauro Carvalho Chehab <mchehab+huawei@kernel.org>
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36154b68 |
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15-Sep-2020 |
Sakari Ailus <sakari.ailus@linux.intel.com> |
media: ccs-pll: Fix VT post-PLL divisor calculation The PLL calculator only searched even total divisor values apart from one, but this is wrong: the total divisor is odd in cases where system divisor is one. Fix this by including odd total PLL values where system divisor is one to the search. Signed-off-by: Sakari Ailus <sakari.ailus@linux.intel.com> Signed-off-by: Mauro Carvalho Chehab <mchehab+huawei@kernel.org>
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594f1e93 |
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15-Sep-2020 |
Sakari Ailus <sakari.ailus@linux.intel.com> |
media: ccs-pll: Make VT divisors 16-bit Make VT divisors 16-bit unsigned numbers. They don't need 32 bits after all. Signed-off-by: Sakari Ailus <sakari.ailus@linux.intel.com> Signed-off-by: Mauro Carvalho Chehab <mchehab+huawei@kernel.org>
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f25d3962 |
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15-Sep-2020 |
Sakari Ailus <sakari.ailus@linux.intel.com> |
media: ccs-pll: Rework bounds checks Refactor bounds checks so that the caller can decide what to check. This allows doing the checks early, when the values are available. This also adds front OP PLL configuration and limits. Signed-off-by: Sakari Ailus <sakari.ailus@linux.intel.com> Signed-off-by: Mauro Carvalho Chehab <mchehab+huawei@kernel.org>
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fadfe884 |
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09-Sep-2020 |
Sakari Ailus <sakari.ailus@linux.intel.com> |
media: ccs-pll: Print relevant information on PLL tree Print information on PLL tree configuration based on the flags. This also adds support for printing dual PLL trees, and better separates between OP and VT PLL trees. Signed-off-by: Sakari Ailus <sakari.ailus@linux.intel.com> Signed-off-by: Mauro Carvalho Chehab <mchehab+huawei@kernel.org>
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a38836b2 |
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04-Sep-2020 |
Sakari Ailus <sakari.ailus@linux.intel.com> |
media: ccs-pll: Better separate OP and VT sub-tree calculation Better separate OP PLL branch calculation from VT branch calculation. Signed-off-by: Sakari Ailus <sakari.ailus@linux.intel.com> Signed-off-by: Mauro Carvalho Chehab <mchehab+huawei@kernel.org>
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38c94eb8 |
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28-Aug-2020 |
Sakari Ailus <sakari.ailus@linux.intel.com> |
media: ccs-pll: Check for derating and overrating, support non-derating sensors Some sensors support derating (VT domain speed faster than OP) or overrating (VT domain speed slower than OP). While this was supported for the driver, the hardware support for the feature was never verified. Do that now, and for those devices without that support, VT and OP speeds have to match. Signed-off-by: Sakari Ailus <sakari.ailus@linux.intel.com> Signed-off-by: Mauro Carvalho Chehab <mchehab+huawei@kernel.org>
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3e2db036 |
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25-Aug-2020 |
Sakari Ailus <sakari.ailus@linux.intel.com> |
media: ccs-pll: Split off VT subtree calculation Split off the VT sub clock tree calculation from the rest, into its own function. Also call the op_pll_fr argument pll_fr, since soon these may not be OP tree values. This paves way for additional features in the future such as dual PLL support. Signed-off-by: Sakari Ailus <sakari.ailus@linux.intel.com> Signed-off-by: Mauro Carvalho Chehab <mchehab+huawei@kernel.org>
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8030aa4f |
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03-Jul-2020 |
Sakari Ailus <sakari.ailus@linux.intel.com> |
media: ccs-pll: Add C-PHY support Add C-PHY support for the CCS PLL calculator. Signed-off-by: Sakari Ailus <sakari.ailus@linux.intel.com> Signed-off-by: Mauro Carvalho Chehab <mchehab+huawei@kernel.org>
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d7172c0e |
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03-Aug-2020 |
Sakari Ailus <sakari.ailus@linux.intel.com> |
media: ccs-pll: Add sanity checks Add sanity checks for fields that could cause division by zero. Signed-off-by: Sakari Ailus <sakari.ailus@linux.intel.com> Signed-off-by: Mauro Carvalho Chehab <mchehab+huawei@kernel.org>
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9490a227 |
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07-Aug-2020 |
Sakari Ailus <sakari.ailus@linux.intel.com> |
media: ccs-pll: Add support flexible OP PLL pixel clock divider Flexible OP PLL pixel clock divider allows a higher OP pixel clock than what the bus can transfer. This generally makes it easier to select pixel clock dividers. This changes how the pixel rate on the bus and minimum VT divisor are calculated, as the pixel rate is no longer directly determined by the OP pixel clock and the number of the lanes. Also add a sanity check for sensors that do not support flexible OP PLL pixel clock divider. This could have caused the PLL calculator to come up with an invalid configuration for those devices. Signed-off-by: Sakari Ailus <sakari.ailus@linux.intel.com> Signed-off-by: Mauro Carvalho Chehab <mchehab+huawei@kernel.org>
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c4c0b222 |
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07-Aug-2020 |
Sakari Ailus <sakari.ailus@linux.intel.com> |
media: ccs-pll: Support two cycles per pixel on OP domain The l parameter defines the number of clock cycles to process a single pixel per OP lane. It is calculated based on a new register op_bits_per_lane. Signed-off-by: Sakari Ailus <sakari.ailus@linux.intel.com> Signed-off-by: Mauro Carvalho Chehab <mchehab+huawei@kernel.org>
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4e1e8d24 |
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23-Jun-2020 |
Sakari Ailus <sakari.ailus@linux.intel.com> |
media: ccs-pll: Add support for extended input PLL clock divider CCS allows odd PLL dividers other than 1, granted that the corresponding capability bit is set. Support this both in the PLL calculator and the CCS driver. Signed-off-by: Sakari Ailus <sakari.ailus@linux.intel.com> Signed-off-by: Mauro Carvalho Chehab <mchehab+huawei@kernel.org>
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ae502e08 |
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17-Jun-2020 |
Sakari Ailus <sakari.ailus@linux.intel.com> |
media: ccs-pll: Add support for decoupled OP domain calculation Add support for decoupled OP domain clock calculation. This means that the number of VT and OP domain clocks are no longer dependent on the number of CSI-2 lanes in the lane speed mode. The support also replaces the existing quirk flag to calculate OP domain clocks per lane. Also support decoupled OP domain calculation in the CCS driver. Signed-off-by: Sakari Ailus <sakari.ailus@linux.intel.com> Signed-off-by: Mauro Carvalho Chehab <mchehab+huawei@kernel.org>
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cac8f5d2 |
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21-Jun-2020 |
Sakari Ailus <sakari.ailus@linux.intel.com> |
media: ccs-pll: Add support for lane speed model CCS PLL includes a capability to calculate the VT clocks on per-lane basis. Add support for this feature. Move calculation of the pixel rate on the CSI-2 bus early in the function as everything needed to calculate it is already available. Signed-off-by: Sakari Ailus <sakari.ailus@linux.intel.com> Signed-off-by: Mauro Carvalho Chehab <mchehab+huawei@kernel.org>
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e583e654 |
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25-Aug-2020 |
Sakari Ailus <sakari.ailus@linux.intel.com> |
media: ccs-pll: Use explicit 32-bit unsigned type Use uint32_t instead of unsigned int for a variable that contains explicitly 32-bit numbers. Signed-off-by: Sakari Ailus <sakari.ailus@linux.intel.com> Signed-off-by: Mauro Carvalho Chehab <mchehab+huawei@kernel.org>
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82ab97c8 |
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07-Jul-2020 |
Sakari Ailus <sakari.ailus@linux.intel.com> |
media: ccs-pll: Fix check for PLL multiplier upper bound The additional multiplier (for higher VT timing) of the PLL multiplier was checked against the upper limit but the result was rounded up, possibly producing too high additional multiplier. Round down instead to keep within hardware limits. Signed-off-by: Sakari Ailus <sakari.ailus@linux.intel.com> Signed-off-by: Mauro Carvalho Chehab <mchehab+huawei@kernel.org>
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c64cf71d |
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07-Jul-2020 |
Sakari Ailus <sakari.ailus@linux.intel.com> |
media: ccs-pll: Fix comment on check against maximum PLL multiplier The comment is about minimum PLL multiplier but the related check really deals with the maximum PLL multiplier. Signed-off-by: Sakari Ailus <sakari.ailus@linux.intel.com> Signed-off-by: Mauro Carvalho Chehab <mchehab+huawei@kernel.org>
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482e75e7 |
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07-Jul-2020 |
Sakari Ailus <sakari.ailus@linux.intel.com> |
media: ccs-pll: Avoid overflow in pre-PLL divisor lower bound search The external clock frequency times the PLL multiplier may exceed the value range of 32-bit unsigned integers. Instead perform the same calculation y using two divisions. The result has some potential to be different, but that's ok: this number is used to limit the range of pre-PLL divisors to find optimal values. So the effect of the rare case of a different result here would mean an invalid pre-PLL divisor is tried. That will be found out a little later in any case. Also guard against dividing by zero if the external clock frequency is higher than the maximum OP PLL output clock --- a rather improbable case. Signed-off-by: Sakari Ailus <sakari.ailus@linux.intel.com> Signed-off-by: Mauro Carvalho Chehab <mchehab+huawei@kernel.org>
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fe52ece8 |
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07-Jul-2020 |
Sakari Ailus <sakari.ailus@linux.intel.com> |
media: ccs-pll: Fix condition for pre-PLL divider lower bound The lower bound of the pre-PLL divider was calculated based on OP SYS clock frequency which is also affected by the OP SYS clock divider. This is wrong. The right clock frequency is that of the PLL output clock. Signed-off-by: Sakari Ailus <sakari.ailus@linux.intel.com> Signed-off-by: Mauro Carvalho Chehab <mchehab+huawei@kernel.org>
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cab27256 |
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26-Jun-2020 |
Sakari Ailus <sakari.ailus@linux.intel.com> |
media: ccs-pll: Begin calculation from OP system clock frequency The OP system clock frequency defines the CSI-2 bus clock frequency, not the PLL output clock frequency. Both values were overwritten in the end, but the wrong limit value was used for the OP system clock frequency, possibly leading to too high frequencies being used. Also remove now duplicated calculation of OP system clock frequency later in the PLL calculator. Signed-off-by: Sakari Ailus <sakari.ailus@linux.intel.com> Signed-off-by: Mauro Carvalho Chehab <mchehab+huawei@kernel.org>
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47b6eaf3 |
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21-Jun-2020 |
Sakari Ailus <sakari.ailus@linux.intel.com> |
media: ccs-pll: Differentiate between CSI-2 D-PHY and C-PHY Differentiate between CSI-2 D-PHY and C-PHY. This does not yet include support for C-PHY. Signed-off-by: Sakari Ailus <sakari.ailus@linux.intel.com> Signed-off-by: Mauro Carvalho Chehab <mchehab+huawei@kernel.org>
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6aadbff9 |
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18-Jun-2020 |
Sakari Ailus <sakari.ailus@linux.intel.com> |
media: ccs-pll: Remove parallel bus support The parallel bus PLL calculation has no users. Remove it. Signed-off-by: Sakari Ailus <sakari.ailus@linux.intel.com> Signed-off-by: Mauro Carvalho Chehab <mchehab+huawei@kernel.org>
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9c1a0d9e |
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01-Sep-2020 |
Sakari Ailus <sakari.ailus@linux.intel.com> |
media: ccs-pll: End search if there are no better values available The VT divisor search can be ended if we've already found the value that corresponds exactly the total divisor, as there are no better (lower) values available. Signed-off-by: Sakari Ailus <sakari.ailus@linux.intel.com> Signed-off-by: Mauro Carvalho Chehab <mchehab+huawei@kernel.org>
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9454432a |
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01-Sep-2020 |
Sakari Ailus <sakari.ailus@linux.intel.com> |
media: ccs-pll: Use correct VT divisor for calculating VT SYS divisor Use the correct video timing divisor to calculate the SYS divisor. Instead of the current value, the minimum was used. This could have resulted in a too low SYS divisor. Signed-off-by: Sakari Ailus <sakari.ailus@linux.intel.com> Signed-off-by: Mauro Carvalho Chehab <mchehab+huawei@kernel.org>
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415ddd99 |
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05-Jun-2020 |
Sakari Ailus <sakari.ailus@linux.intel.com> |
media: ccs-pll: Split limits and PLL configuration into front and back parts The CCS spec supports a lot of variation in the PLL. Split the PLL in front and back parts to better prepare for supporting it. Also use CCS compliant naming for IP and OP PLL frequencies (i.e. include "clk" in the name). Signed-off-by: Sakari Ailus <sakari.ailus@linux.intel.com> Signed-off-by: Mauro Carvalho Chehab <mchehab+huawei@kernel.org>
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c3833a22 |
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25-Jun-2020 |
Sakari Ailus <sakari.ailus@linux.intel.com> |
media: ccs-pll: Don't use div_u64 to divide a 32-bit number pll->pll_op_clk_freq is a 32-bit number. It does not need div_u64 to divide it. Signed-off-by: Sakari Ailus <sakari.ailus@linux.intel.com> Signed-off-by: Mauro Carvalho Chehab <mchehab+huawei@kernel.org>
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7389d01c |
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24-Jun-2020 |
Sakari Ailus <sakari.ailus@linux.intel.com> |
media: ccs: Change my e-mail address Use my @linux.intel.com e-mail address in the CCS driver. Signed-off-by: Sakari Ailus <sakari.ailus@linux.intel.com> Signed-off-by: Mauro Carvalho Chehab <mchehab+huawei@kernel.org>
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b3c0115e |
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02-Oct-2020 |
Sakari Ailus <sakari.ailus@linux.intel.com> |
media: ccs-pll: Fix MODULE_LICENSE Change MODULE_LICENSE to "GPL v2" as indicated by the SPDX tag. Signed-off-by: Sakari Ailus <sakari.ailus@linux.intel.com> Signed-off-by: Mauro Carvalho Chehab <mchehab+huawei@kernel.org>
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9e05bbac |
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27-May-2020 |
Sakari Ailus <sakari.ailus@linux.intel.com> |
media: smiapp-pll: Rename as ccs-pll MIPI CCS replaces SMIA and SMIA++ as the current standard. CCS brings new features while existing functionality will be supported. Rename the smiapp-pll as ccs-pll accordingly. Also add Intel copyright to the files. Signed-off-by: Sakari Ailus <sakari.ailus@linux.intel.com> Signed-off-by: Mauro Carvalho Chehab <mchehab+huawei@kernel.org>
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