/linux-master/drivers/gpu/drm/bridge/ |
H A D | parade-ps8640.c | 599 dsi->lanes = NUM_MIPI_LANES;
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/linux-master/drivers/gpu/drm/panel/ |
H A D | panel-samsung-s6d7aa0.c | 510 dsi->lanes = 4;
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H A D | panel-himax-hx83112a.c | 317 dsi->lanes = 4;
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H A D | panel-leadtek-ltk500hd1829.c | 652 dsi->lanes = 4;
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H A D | panel-truly-nt35597.c | 577 dsi_dev->lanes = 4;
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H A D | panel-novatek-nt35950.c | 587 nt->dsi[i]->lanes = nt->desc->num_lanes;
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/linux-master/drivers/gpu/drm/gma500/ |
H A D | psb_drv.h | 525 int lanes; member in struct:drm_psb_private::__anon16
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/linux-master/drivers/gpu/drm/i915/display/ |
H A D | intel_vbt_defs.h | 708 u8 lanes:4; member in struct:edp_fast_link_params
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H A D | intel_bios.c | 1440 switch (edp_link_params->lanes) { 1442 panel->vbt.edp.lanes = 1; 1445 panel->vbt.edp.lanes = 2; 1448 panel->vbt.edp.lanes = 4; 1453 edp_link_params->lanes);
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/linux-master/drivers/gpu/drm/display/ |
H A D | drm_dp_helper.c | 2707 u8 rate, lanes; local 2714 err = drm_dp_dpcd_readb(aux, DP_TEST_LANE_COUNT, &lanes); 2717 data->num_lanes = lanes & DP_MAX_LANE_COUNT_MASK; 2719 if (lanes & DP_ENHANCED_FRAME_CAP) 4171 * After each 250 data symbols on 2-4 lanes: 4175 * After 256 (2-4 lanes) or 128 (1 lane) FEC blocks: 4242 * Given a link rate and lanes, get the data bandwidth.
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/linux-master/drivers/gpu/drm/nouveau/nvkm/engine/disp/ |
H A D | gf119.c | 133 const u32 shift = sor->func->dp->lanes[ln] * 8; 193 .lanes = { 2, 1, 0, 3 },
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/linux-master/drivers/gpu/drm/radeon/ |
H A D | r300.c | 500 void rv370_set_pcie_lanes(struct radeon_device *rdev, int lanes) argument 512 switch (lanes) {
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H A D | rv770.c | 2022 u32 link_width_cntl, lanes, speed_cntl, tmp; local 2050 lanes = (link_width_cntl & LC_LINK_WIDTH_RD_MASK) >> LC_LINK_WIDTH_RD_SHIFT; 2053 link_width_cntl |= lanes | LC_RECONFIG_NOW |
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H A D | r600.c | 4395 void r600_set_pcie_lanes(struct radeon_device *rdev, int lanes) argument 4411 switch (lanes) { 4435 DRM_ERROR("invalid pcie lane request: %d\n", lanes); 4487 u32 link_width_cntl, lanes, speed_cntl, training_cntl, tmp; local 4529 lanes = (link_width_cntl & LC_LINK_WIDTH_RD_MASK) >> LC_LINK_WIDTH_RD_SHIFT; 4532 link_width_cntl |= lanes | LC_RECONFIG_NOW | LC_RENEGOTIATE_EN;
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H A D | radeon_asic.h | 179 extern void rv370_set_pcie_lanes(struct radeon_device *rdev, int lanes); 367 extern void r600_set_pcie_lanes(struct radeon_device *rdev, int lanes);
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/linux-master/drivers/media/platform/nxp/ |
H A D | imx-mipi-csis.c | 647 int lanes = csis->bus.num_data_lanes; local 652 val |= (lanes - 1) << MIPI_CSIS_CMN_CTRL_LANE_NR_OFFSET; 1301 "data lanes reordering is not supported"); 1309 dev_dbg(csis->dev, "data lanes: %d\n", csis->bus.num_data_lanes); 1506 dev_info(dev, "lanes: %d, freq: %u\n",
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/linux-master/drivers/media/platform/qcom/camss/ |
H A D | camss.c | 1323 * @lanes: Number of lanes in the link to the sensor 1328 unsigned int lanes) 1339 return v4l2_get_link_freq(subdev->ctrl_handler, bpp, 2 * lanes); 1327 camss_get_link_freq(struct media_entity *entity, unsigned int bpp, unsigned int lanes) argument
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/linux-master/drivers/phy/qualcomm/ |
H A D | phy-qcom-qmp-combo.c | 2090 for (i = 0; i < dp_opts->lanes; i++) { 2127 if (dp_opts->lanes == 1) { 2150 if (dp_opts->lanes == 4 || reverse) 2152 if (dp_opts->lanes == 4 || !reverse) 2397 if (dp_opts->lanes == 1) { 2402 } else if (dp_opts->lanes == 2) {
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/linux-master/drivers/net/ethernet/mellanox/mlxsw/ |
H A D | core.c | 3063 bool splittable, u32 lanes, 3075 attrs.lanes = lanes; 3113 bool splittable, u32 lanes, 3122 splittable, lanes, 3059 __mlxsw_core_port_init(struct mlxsw_core *mlxsw_core, u16 local_port, enum devlink_port_flavour flavour, u8 slot_index, u32 port_number, bool split, u32 split_port_subnumber, bool splittable, u32 lanes, const unsigned char *switch_id, unsigned char switch_id_len) argument 3110 mlxsw_core_port_init(struct mlxsw_core *mlxsw_core, u16 local_port, u8 slot_index, u32 port_number, bool split, u32 split_port_subnumber, bool splittable, u32 lanes, const unsigned char *switch_id, unsigned char switch_id_len) argument
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/linux-master/drivers/media/i2c/ |
H A D | ov08x40.c | 132 u32 lanes; member in struct:ov08x40_mode 1223 * data rate => double data rate; number of lanes => 4; bits per pixel => 10 1256 .lanes = 4, 1271 .lanes = 4, 2089 dev_err(dev, "number of CSI2 data lanes %d is not supported",
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/linux-master/drivers/gpu/drm/msm/dp/ |
H A D | dp_ctrl.c | 48 int nlanes; /* no.of.lanes */ 60 u8 lanes; member in struct:dp_vc_tu_mapping_table 1027 /* TODO: Update for all lanes instead of just first one */ 1448 ctrl->phy_opts.dp.lanes = ctrl->link->link_params.num_lanes; 1575 ctrl->phy_opts.dp.lanes = ctrl->link->link_params.num_lanes; 1793 * lane_count = 4, then only interested in 2 lanes 1871 * some lanes are ready,
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/linux-master/drivers/gpu/drm/amd/amdgpu/ |
H A D | si.c | 1540 static void si_set_pcie_lanes(struct amdgpu_device *adev, int lanes) argument 1547 switch (lanes) { 1567 DRM_ERROR("invalid pcie lane request: %d\n", lanes);
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/linux-master/drivers/gpu/drm/amd/amdkfd/ |
H A D | cwsr_trap_handler_gfx10.asm | 562 // Write HWREGs with 16 VGPR lanes. TTMPs occupy space after this. 567 // Write SGPRs with 32 VGPR lanes. This works in wave32 and wave64 mode. 605 s_cmp_eq_u32 ttmp13, 0x20 //have 32 VGPR lanes filled?
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/linux-master/drivers/gpu/drm/amd/pm/powerplay/hwmgr/ |
H A D | processpptables.c | 701 ps->pcie.lanes = ((le32_to_cpu(pnon_clock_info->ulCapsAndSettings) & 705 ps->pcie.lanes = 0;
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/linux-master/arch/x86/crypto/ |
H A D | sha256-avx-asm.S | 47 # This code schedules 1 block at a time, with 4 lanes per block
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