1// SPDX-License-Identifier: GPL-2.0 2/* 3 * Copyright (c) 2017, The Linux Foundation. All rights reserved. 4 */ 5 6#include <linux/clk.h> 7#include <linux/clk-provider.h> 8#include <linux/delay.h> 9#include <linux/err.h> 10#include <linux/io.h> 11#include <linux/iopoll.h> 12#include <linux/kernel.h> 13#include <linux/module.h> 14#include <linux/of.h> 15#include <linux/of_address.h> 16#include <linux/phy/phy.h> 17#include <linux/platform_device.h> 18#include <linux/regulator/consumer.h> 19#include <linux/reset.h> 20#include <linux/slab.h> 21#include <linux/usb/typec.h> 22#include <linux/usb/typec_mux.h> 23 24#include <drm/bridge/aux-bridge.h> 25 26#include <dt-bindings/phy/phy-qcom-qmp.h> 27 28#include "phy-qcom-qmp-common.h" 29 30#include "phy-qcom-qmp.h" 31#include "phy-qcom-qmp-pcs-misc-v3.h" 32#include "phy-qcom-qmp-pcs-usb-v4.h" 33#include "phy-qcom-qmp-pcs-usb-v5.h" 34#include "phy-qcom-qmp-pcs-usb-v6.h" 35 36#include "phy-qcom-qmp-dp-com-v3.h" 37 38#include "phy-qcom-qmp-dp-phy.h" 39#include "phy-qcom-qmp-dp-phy-v3.h" 40#include "phy-qcom-qmp-dp-phy-v4.h" 41#include "phy-qcom-qmp-dp-phy-v5.h" 42#include "phy-qcom-qmp-dp-phy-v6.h" 43 44/* QPHY_V3_DP_COM_RESET_OVRD_CTRL register bits */ 45/* DP PHY soft reset */ 46#define SW_DPPHY_RESET BIT(0) 47/* mux to select DP PHY reset control, 0:HW control, 1: software reset */ 48#define SW_DPPHY_RESET_MUX BIT(1) 49/* USB3 PHY soft reset */ 50#define SW_USB3PHY_RESET BIT(2) 51/* mux to select USB3 PHY reset control, 0:HW control, 1: software reset */ 52#define SW_USB3PHY_RESET_MUX BIT(3) 53 54/* QPHY_V3_DP_COM_PHY_MODE_CTRL register bits */ 55#define USB3_MODE BIT(0) /* enables USB3 mode */ 56#define DP_MODE BIT(1) /* enables DP mode */ 57 58/* QPHY_V3_DP_COM_TYPEC_CTRL register bits */ 59#define SW_PORTSELECT_VAL BIT(0) 60#define SW_PORTSELECT_MUX BIT(1) 61 62#define PHY_INIT_COMPLETE_TIMEOUT 10000 63 64/* set of registers with offsets different per-PHY */ 65enum qphy_reg_layout { 66 /* PCS registers */ 67 QPHY_SW_RESET, 68 QPHY_START_CTRL, 69 QPHY_PCS_STATUS, 70 QPHY_PCS_AUTONOMOUS_MODE_CTRL, 71 QPHY_PCS_LFPS_RXTERM_IRQ_CLEAR, 72 QPHY_PCS_POWER_DOWN_CONTROL, 73 74 QPHY_COM_RESETSM_CNTRL, 75 QPHY_COM_C_READY_STATUS, 76 QPHY_COM_CMN_STATUS, 77 QPHY_COM_BIAS_EN_CLKBUFLR_EN, 78 79 QPHY_DP_PHY_STATUS, 80 QPHY_DP_PHY_VCO_DIV, 81 82 QPHY_TX_TX_POL_INV, 83 QPHY_TX_TX_DRV_LVL, 84 QPHY_TX_TX_EMP_POST1_LVL, 85 QPHY_TX_HIGHZ_DRVR_EN, 86 QPHY_TX_TRANSCEIVER_BIAS_EN, 87 88 /* Keep last to ensure regs_layout arrays are properly initialized */ 89 QPHY_LAYOUT_SIZE 90}; 91 92static const unsigned int qmp_v3_usb3phy_regs_layout[QPHY_LAYOUT_SIZE] = { 93 [QPHY_SW_RESET] = QPHY_V3_PCS_SW_RESET, 94 [QPHY_START_CTRL] = QPHY_V3_PCS_START_CONTROL, 95 [QPHY_PCS_STATUS] = QPHY_V3_PCS_PCS_STATUS, 96 [QPHY_PCS_POWER_DOWN_CONTROL] = QPHY_V3_PCS_POWER_DOWN_CONTROL, 97 [QPHY_PCS_AUTONOMOUS_MODE_CTRL] = QPHY_V3_PCS_AUTONOMOUS_MODE_CTRL, 98 [QPHY_PCS_LFPS_RXTERM_IRQ_CLEAR] = QPHY_V3_PCS_LFPS_RXTERM_IRQ_CLEAR, 99 100 [QPHY_COM_RESETSM_CNTRL] = QSERDES_V3_COM_RESETSM_CNTRL, 101 [QPHY_COM_C_READY_STATUS] = QSERDES_V3_COM_C_READY_STATUS, 102 [QPHY_COM_CMN_STATUS] = QSERDES_V3_COM_CMN_STATUS, 103 [QPHY_COM_BIAS_EN_CLKBUFLR_EN] = QSERDES_V3_COM_BIAS_EN_CLKBUFLR_EN, 104 105 [QPHY_DP_PHY_STATUS] = QSERDES_V3_DP_PHY_STATUS, 106 [QPHY_DP_PHY_VCO_DIV] = QSERDES_V3_DP_PHY_VCO_DIV, 107 108 [QPHY_TX_TX_POL_INV] = QSERDES_V3_TX_TX_POL_INV, 109 [QPHY_TX_TX_DRV_LVL] = QSERDES_V3_TX_TX_DRV_LVL, 110 [QPHY_TX_TX_EMP_POST1_LVL] = QSERDES_V3_TX_TX_EMP_POST1_LVL, 111 [QPHY_TX_HIGHZ_DRVR_EN] = QSERDES_V3_TX_HIGHZ_DRVR_EN, 112 [QPHY_TX_TRANSCEIVER_BIAS_EN] = QSERDES_V3_TX_TRANSCEIVER_BIAS_EN, 113}; 114 115static const unsigned int qmp_v45_usb3phy_regs_layout[QPHY_LAYOUT_SIZE] = { 116 [QPHY_SW_RESET] = QPHY_V4_PCS_SW_RESET, 117 [QPHY_START_CTRL] = QPHY_V4_PCS_START_CONTROL, 118 [QPHY_PCS_STATUS] = QPHY_V4_PCS_PCS_STATUS1, 119 [QPHY_PCS_POWER_DOWN_CONTROL] = QPHY_V4_PCS_POWER_DOWN_CONTROL, 120 121 /* In PCS_USB */ 122 [QPHY_PCS_AUTONOMOUS_MODE_CTRL] = QPHY_V4_PCS_USB3_AUTONOMOUS_MODE_CTRL, 123 [QPHY_PCS_LFPS_RXTERM_IRQ_CLEAR] = QPHY_V4_PCS_USB3_LFPS_RXTERM_IRQ_CLEAR, 124 125 [QPHY_COM_RESETSM_CNTRL] = QSERDES_V4_COM_RESETSM_CNTRL, 126 [QPHY_COM_C_READY_STATUS] = QSERDES_V4_COM_C_READY_STATUS, 127 [QPHY_COM_CMN_STATUS] = QSERDES_V4_COM_CMN_STATUS, 128 [QPHY_COM_BIAS_EN_CLKBUFLR_EN] = QSERDES_V4_COM_BIAS_EN_CLKBUFLR_EN, 129 130 [QPHY_DP_PHY_STATUS] = QSERDES_V4_DP_PHY_STATUS, 131 [QPHY_DP_PHY_VCO_DIV] = QSERDES_V4_DP_PHY_VCO_DIV, 132 133 [QPHY_TX_TX_POL_INV] = QSERDES_V4_TX_TX_POL_INV, 134 [QPHY_TX_TX_DRV_LVL] = QSERDES_V4_TX_TX_DRV_LVL, 135 [QPHY_TX_TX_EMP_POST1_LVL] = QSERDES_V4_TX_TX_EMP_POST1_LVL, 136 [QPHY_TX_HIGHZ_DRVR_EN] = QSERDES_V4_TX_HIGHZ_DRVR_EN, 137 [QPHY_TX_TRANSCEIVER_BIAS_EN] = QSERDES_V4_TX_TRANSCEIVER_BIAS_EN, 138}; 139 140static const unsigned int qmp_v5_5nm_usb3phy_regs_layout[QPHY_LAYOUT_SIZE] = { 141 [QPHY_SW_RESET] = QPHY_V5_PCS_SW_RESET, 142 [QPHY_START_CTRL] = QPHY_V5_PCS_START_CONTROL, 143 [QPHY_PCS_STATUS] = QPHY_V5_PCS_PCS_STATUS1, 144 [QPHY_PCS_POWER_DOWN_CONTROL] = QPHY_V5_PCS_POWER_DOWN_CONTROL, 145 146 /* In PCS_USB */ 147 [QPHY_PCS_AUTONOMOUS_MODE_CTRL] = QPHY_V5_PCS_USB3_AUTONOMOUS_MODE_CTRL, 148 [QPHY_PCS_LFPS_RXTERM_IRQ_CLEAR] = QPHY_V5_PCS_USB3_LFPS_RXTERM_IRQ_CLEAR, 149 150 [QPHY_COM_RESETSM_CNTRL] = QSERDES_V5_COM_RESETSM_CNTRL, 151 [QPHY_COM_C_READY_STATUS] = QSERDES_V5_COM_C_READY_STATUS, 152 [QPHY_COM_CMN_STATUS] = QSERDES_V5_COM_CMN_STATUS, 153 [QPHY_COM_BIAS_EN_CLKBUFLR_EN] = QSERDES_V5_COM_BIAS_EN_CLKBUFLR_EN, 154 155 [QPHY_DP_PHY_STATUS] = QSERDES_V5_DP_PHY_STATUS, 156 [QPHY_DP_PHY_VCO_DIV] = QSERDES_V5_DP_PHY_VCO_DIV, 157 158 [QPHY_TX_TX_POL_INV] = QSERDES_V5_5NM_TX_TX_POL_INV, 159 [QPHY_TX_TX_DRV_LVL] = QSERDES_V5_5NM_TX_TX_DRV_LVL, 160 [QPHY_TX_TX_EMP_POST1_LVL] = QSERDES_V5_5NM_TX_TX_EMP_POST1_LVL, 161 [QPHY_TX_HIGHZ_DRVR_EN] = QSERDES_V5_5NM_TX_HIGHZ_DRVR_EN, 162 [QPHY_TX_TRANSCEIVER_BIAS_EN] = QSERDES_V5_5NM_TX_TRANSCEIVER_BIAS_EN, 163}; 164 165static const unsigned int qmp_v6_usb3phy_regs_layout[QPHY_LAYOUT_SIZE] = { 166 [QPHY_SW_RESET] = QPHY_V6_PCS_SW_RESET, 167 [QPHY_START_CTRL] = QPHY_V6_PCS_START_CONTROL, 168 [QPHY_PCS_STATUS] = QPHY_V6_PCS_PCS_STATUS1, 169 [QPHY_PCS_POWER_DOWN_CONTROL] = QPHY_V6_PCS_POWER_DOWN_CONTROL, 170 171 /* In PCS_USB */ 172 [QPHY_PCS_AUTONOMOUS_MODE_CTRL] = QPHY_V6_PCS_USB3_AUTONOMOUS_MODE_CTRL, 173 [QPHY_PCS_LFPS_RXTERM_IRQ_CLEAR] = QPHY_V6_PCS_USB3_LFPS_RXTERM_IRQ_CLEAR, 174 175 [QPHY_COM_RESETSM_CNTRL] = QSERDES_V6_COM_RESETSM_CNTRL, 176 [QPHY_COM_C_READY_STATUS] = QSERDES_V6_COM_C_READY_STATUS, 177 [QPHY_COM_CMN_STATUS] = QSERDES_V6_COM_CMN_STATUS, 178 [QPHY_COM_BIAS_EN_CLKBUFLR_EN] = QSERDES_V6_COM_PLL_BIAS_EN_CLK_BUFLR_EN, 179 180 [QPHY_DP_PHY_STATUS] = QSERDES_V6_DP_PHY_STATUS, 181 [QPHY_DP_PHY_VCO_DIV] = QSERDES_V6_DP_PHY_VCO_DIV, 182 183 [QPHY_TX_TX_POL_INV] = QSERDES_V6_TX_TX_POL_INV, 184 [QPHY_TX_TX_DRV_LVL] = QSERDES_V6_TX_TX_DRV_LVL, 185 [QPHY_TX_TX_EMP_POST1_LVL] = QSERDES_V6_TX_TX_EMP_POST1_LVL, 186 [QPHY_TX_HIGHZ_DRVR_EN] = QSERDES_V6_TX_HIGHZ_DRVR_EN, 187 [QPHY_TX_TRANSCEIVER_BIAS_EN] = QSERDES_V6_TX_TRANSCEIVER_BIAS_EN, 188}; 189 190static const struct qmp_phy_init_tbl qmp_v3_usb3_serdes_tbl[] = { 191 QMP_PHY_INIT_CFG(QSERDES_V3_COM_PLL_IVCO, 0x07), 192 QMP_PHY_INIT_CFG(QSERDES_V3_COM_SYSCLK_EN_SEL, 0x14), 193 QMP_PHY_INIT_CFG(QSERDES_V3_COM_BIAS_EN_CLKBUFLR_EN, 0x08), 194 QMP_PHY_INIT_CFG(QSERDES_V3_COM_CLK_SELECT, 0x30), 195 QMP_PHY_INIT_CFG(QSERDES_V3_COM_SYS_CLK_CTRL, 0x02), 196 QMP_PHY_INIT_CFG(QSERDES_V3_COM_RESETSM_CNTRL2, 0x08), 197 QMP_PHY_INIT_CFG(QSERDES_V3_COM_CMN_CONFIG, 0x16), 198 QMP_PHY_INIT_CFG(QSERDES_V3_COM_SVS_MODE_CLK_SEL, 0x01), 199 QMP_PHY_INIT_CFG(QSERDES_V3_COM_HSCLK_SEL, 0x80), 200 QMP_PHY_INIT_CFG(QSERDES_V3_COM_DEC_START_MODE0, 0x82), 201 QMP_PHY_INIT_CFG(QSERDES_V3_COM_DIV_FRAC_START1_MODE0, 0xab), 202 QMP_PHY_INIT_CFG(QSERDES_V3_COM_DIV_FRAC_START2_MODE0, 0xea), 203 QMP_PHY_INIT_CFG(QSERDES_V3_COM_DIV_FRAC_START3_MODE0, 0x02), 204 QMP_PHY_INIT_CFG(QSERDES_V3_COM_CP_CTRL_MODE0, 0x06), 205 QMP_PHY_INIT_CFG(QSERDES_V3_COM_PLL_RCTRL_MODE0, 0x16), 206 QMP_PHY_INIT_CFG(QSERDES_V3_COM_PLL_CCTRL_MODE0, 0x36), 207 QMP_PHY_INIT_CFG(QSERDES_V3_COM_INTEGLOOP_GAIN1_MODE0, 0x00), 208 QMP_PHY_INIT_CFG(QSERDES_V3_COM_INTEGLOOP_GAIN0_MODE0, 0x3f), 209 QMP_PHY_INIT_CFG(QSERDES_V3_COM_VCO_TUNE2_MODE0, 0x01), 210 QMP_PHY_INIT_CFG(QSERDES_V3_COM_VCO_TUNE1_MODE0, 0xc9), 211 QMP_PHY_INIT_CFG(QSERDES_V3_COM_CORECLK_DIV_MODE0, 0x0a), 212 QMP_PHY_INIT_CFG(QSERDES_V3_COM_LOCK_CMP3_MODE0, 0x00), 213 QMP_PHY_INIT_CFG(QSERDES_V3_COM_LOCK_CMP2_MODE0, 0x34), 214 QMP_PHY_INIT_CFG(QSERDES_V3_COM_LOCK_CMP1_MODE0, 0x15), 215 QMP_PHY_INIT_CFG(QSERDES_V3_COM_LOCK_CMP_EN, 0x04), 216 QMP_PHY_INIT_CFG(QSERDES_V3_COM_CORE_CLK_EN, 0x00), 217 QMP_PHY_INIT_CFG(QSERDES_V3_COM_LOCK_CMP_CFG, 0x00), 218 QMP_PHY_INIT_CFG(QSERDES_V3_COM_VCO_TUNE_MAP, 0x00), 219 QMP_PHY_INIT_CFG(QSERDES_V3_COM_SYSCLK_BUF_ENABLE, 0x0a), 220 QMP_PHY_INIT_CFG(QSERDES_V3_COM_SSC_EN_CENTER, 0x01), 221 QMP_PHY_INIT_CFG(QSERDES_V3_COM_SSC_PER1, 0x31), 222 QMP_PHY_INIT_CFG(QSERDES_V3_COM_SSC_PER2, 0x01), 223 QMP_PHY_INIT_CFG(QSERDES_V3_COM_SSC_ADJ_PER1, 0x00), 224 QMP_PHY_INIT_CFG(QSERDES_V3_COM_SSC_ADJ_PER2, 0x00), 225 QMP_PHY_INIT_CFG(QSERDES_V3_COM_SSC_STEP_SIZE1, 0x85), 226 QMP_PHY_INIT_CFG(QSERDES_V3_COM_SSC_STEP_SIZE2, 0x07), 227}; 228 229static const struct qmp_phy_init_tbl qmp_v3_usb3_tx_tbl[] = { 230 QMP_PHY_INIT_CFG(QSERDES_V3_TX_HIGHZ_DRVR_EN, 0x10), 231 QMP_PHY_INIT_CFG(QSERDES_V3_TX_RCV_DETECT_LVL_2, 0x12), 232 QMP_PHY_INIT_CFG(QSERDES_V3_TX_LANE_MODE_1, 0x16), 233 QMP_PHY_INIT_CFG(QSERDES_V3_TX_RES_CODE_LANE_OFFSET_RX, 0x09), 234 QMP_PHY_INIT_CFG(QSERDES_V3_TX_RES_CODE_LANE_OFFSET_TX, 0x06), 235}; 236 237static const struct qmp_phy_init_tbl qmp_v3_dp_serdes_tbl[] = { 238 QMP_PHY_INIT_CFG(QSERDES_V3_COM_SVS_MODE_CLK_SEL, 0x01), 239 QMP_PHY_INIT_CFG(QSERDES_V3_COM_SYSCLK_EN_SEL, 0x37), 240 QMP_PHY_INIT_CFG(QSERDES_V3_COM_SYS_CLK_CTRL, 0x02), 241 QMP_PHY_INIT_CFG(QSERDES_V3_COM_CLK_ENABLE1, 0x0e), 242 QMP_PHY_INIT_CFG(QSERDES_V3_COM_SYSCLK_BUF_ENABLE, 0x06), 243 QMP_PHY_INIT_CFG(QSERDES_V3_COM_CLK_SELECT, 0x30), 244 QMP_PHY_INIT_CFG(QSERDES_V3_COM_CMN_CONFIG, 0x02), 245 QMP_PHY_INIT_CFG(QSERDES_V3_COM_DIV_FRAC_START1_MODE0, 0x00), 246 QMP_PHY_INIT_CFG(QSERDES_V3_COM_INTEGLOOP_GAIN0_MODE0, 0x3f), 247 QMP_PHY_INIT_CFG(QSERDES_V3_COM_INTEGLOOP_GAIN1_MODE0, 0x00), 248 QMP_PHY_INIT_CFG(QSERDES_V3_COM_VCO_TUNE_MAP, 0x00), 249 QMP_PHY_INIT_CFG(QSERDES_V3_COM_LOCK_CMP3_MODE0, 0x00), 250 QMP_PHY_INIT_CFG(QSERDES_V3_COM_BG_TIMER, 0x0a), 251 QMP_PHY_INIT_CFG(QSERDES_V3_COM_CORECLK_DIV_MODE0, 0x0a), 252 QMP_PHY_INIT_CFG(QSERDES_V3_COM_VCO_TUNE_CTRL, 0x00), 253 QMP_PHY_INIT_CFG(QSERDES_V3_COM_BIAS_EN_CLKBUFLR_EN, 0x3f), 254 QMP_PHY_INIT_CFG(QSERDES_V3_COM_CORE_CLK_EN, 0x1f), 255 QMP_PHY_INIT_CFG(QSERDES_V3_COM_PLL_IVCO, 0x07), 256 QMP_PHY_INIT_CFG(QSERDES_V3_COM_PLL_CCTRL_MODE0, 0x36), 257 QMP_PHY_INIT_CFG(QSERDES_V3_COM_PLL_RCTRL_MODE0, 0x16), 258 QMP_PHY_INIT_CFG(QSERDES_V3_COM_CP_CTRL_MODE0, 0x06), 259}; 260 261static const struct qmp_phy_init_tbl qmp_v3_dp_serdes_tbl_rbr[] = { 262 QMP_PHY_INIT_CFG(QSERDES_V3_COM_HSCLK_SEL, 0x0c), 263 QMP_PHY_INIT_CFG(QSERDES_V3_COM_DEC_START_MODE0, 0x69), 264 QMP_PHY_INIT_CFG(QSERDES_V3_COM_DIV_FRAC_START2_MODE0, 0x80), 265 QMP_PHY_INIT_CFG(QSERDES_V3_COM_DIV_FRAC_START3_MODE0, 0x07), 266 QMP_PHY_INIT_CFG(QSERDES_V3_COM_LOCK_CMP1_MODE0, 0x6f), 267 QMP_PHY_INIT_CFG(QSERDES_V3_COM_LOCK_CMP2_MODE0, 0x08), 268 QMP_PHY_INIT_CFG(QSERDES_V3_COM_LOCK_CMP_EN, 0x00), 269}; 270 271static const struct qmp_phy_init_tbl qmp_v3_dp_serdes_tbl_hbr[] = { 272 QMP_PHY_INIT_CFG(QSERDES_V3_COM_HSCLK_SEL, 0x04), 273 QMP_PHY_INIT_CFG(QSERDES_V3_COM_DEC_START_MODE0, 0x69), 274 QMP_PHY_INIT_CFG(QSERDES_V3_COM_DIV_FRAC_START2_MODE0, 0x80), 275 QMP_PHY_INIT_CFG(QSERDES_V3_COM_DIV_FRAC_START3_MODE0, 0x07), 276 QMP_PHY_INIT_CFG(QSERDES_V3_COM_LOCK_CMP1_MODE0, 0x0f), 277 QMP_PHY_INIT_CFG(QSERDES_V3_COM_LOCK_CMP2_MODE0, 0x0e), 278 QMP_PHY_INIT_CFG(QSERDES_V3_COM_LOCK_CMP_EN, 0x00), 279}; 280 281static const struct qmp_phy_init_tbl qmp_v3_dp_serdes_tbl_hbr2[] = { 282 QMP_PHY_INIT_CFG(QSERDES_V3_COM_HSCLK_SEL, 0x00), 283 QMP_PHY_INIT_CFG(QSERDES_V3_COM_DEC_START_MODE0, 0x8c), 284 QMP_PHY_INIT_CFG(QSERDES_V3_COM_DIV_FRAC_START2_MODE0, 0x00), 285 QMP_PHY_INIT_CFG(QSERDES_V3_COM_DIV_FRAC_START3_MODE0, 0x0a), 286 QMP_PHY_INIT_CFG(QSERDES_V3_COM_LOCK_CMP1_MODE0, 0x1f), 287 QMP_PHY_INIT_CFG(QSERDES_V3_COM_LOCK_CMP2_MODE0, 0x1c), 288 QMP_PHY_INIT_CFG(QSERDES_V3_COM_LOCK_CMP_EN, 0x00), 289}; 290 291static const struct qmp_phy_init_tbl qmp_v3_dp_serdes_tbl_hbr3[] = { 292 QMP_PHY_INIT_CFG(QSERDES_V3_COM_HSCLK_SEL, 0x03), 293 QMP_PHY_INIT_CFG(QSERDES_V3_COM_DEC_START_MODE0, 0x69), 294 QMP_PHY_INIT_CFG(QSERDES_V3_COM_DIV_FRAC_START2_MODE0, 0x80), 295 QMP_PHY_INIT_CFG(QSERDES_V3_COM_DIV_FRAC_START3_MODE0, 0x07), 296 QMP_PHY_INIT_CFG(QSERDES_V3_COM_LOCK_CMP1_MODE0, 0x2f), 297 QMP_PHY_INIT_CFG(QSERDES_V3_COM_LOCK_CMP2_MODE0, 0x2a), 298 QMP_PHY_INIT_CFG(QSERDES_V3_COM_LOCK_CMP_EN, 0x08), 299}; 300 301static const struct qmp_phy_init_tbl qmp_v3_dp_tx_tbl[] = { 302 QMP_PHY_INIT_CFG(QSERDES_V3_TX_TRANSCEIVER_BIAS_EN, 0x1a), 303 QMP_PHY_INIT_CFG(QSERDES_V3_TX_VMODE_CTRL1, 0x40), 304 QMP_PHY_INIT_CFG(QSERDES_V3_TX_PRE_STALL_LDO_BOOST_EN, 0x30), 305 QMP_PHY_INIT_CFG(QSERDES_V3_TX_INTERFACE_SELECT, 0x3d), 306 QMP_PHY_INIT_CFG(QSERDES_V3_TX_CLKBUF_ENABLE, 0x0f), 307 QMP_PHY_INIT_CFG(QSERDES_V3_TX_RESET_TSYNC_EN, 0x03), 308 QMP_PHY_INIT_CFG(QSERDES_V3_TX_TRAN_DRVR_EMP_EN, 0x03), 309 QMP_PHY_INIT_CFG(QSERDES_V3_TX_PARRATE_REC_DETECT_IDLE_EN, 0x00), 310 QMP_PHY_INIT_CFG(QSERDES_V3_TX_TX_INTERFACE_MODE, 0x00), 311 QMP_PHY_INIT_CFG(QSERDES_V3_TX_TX_BAND, 0x4), 312 QMP_PHY_INIT_CFG(QSERDES_V3_TX_TX_POL_INV, 0x0a), 313 QMP_PHY_INIT_CFG(QSERDES_V3_TX_TX_DRV_LVL, 0x38), 314 QMP_PHY_INIT_CFG(QSERDES_V3_TX_TX_EMP_POST1_LVL, 0x20), 315 QMP_PHY_INIT_CFG(QSERDES_V3_TX_RES_CODE_LANE_OFFSET_TX, 0x06), 316 QMP_PHY_INIT_CFG(QSERDES_V3_TX_RES_CODE_LANE_OFFSET_RX, 0x07), 317}; 318 319static const struct qmp_phy_init_tbl qmp_v3_usb3_rx_tbl[] = { 320 QMP_PHY_INIT_CFG(QSERDES_V3_RX_UCDR_FASTLOCK_FO_GAIN, 0x0b), 321 QMP_PHY_INIT_CFG(QSERDES_V3_RX_RX_EQU_ADAPTOR_CNTRL2, 0x0f), 322 QMP_PHY_INIT_CFG(QSERDES_V3_RX_RX_EQU_ADAPTOR_CNTRL3, 0x4e), 323 QMP_PHY_INIT_CFG(QSERDES_V3_RX_RX_EQU_ADAPTOR_CNTRL4, 0x18), 324 QMP_PHY_INIT_CFG(QSERDES_V3_RX_RX_EQ_OFFSET_ADAPTOR_CNTRL1, 0x77), 325 QMP_PHY_INIT_CFG(QSERDES_V3_RX_RX_OFFSET_ADAPTOR_CNTRL2, 0x80), 326 QMP_PHY_INIT_CFG(QSERDES_V3_RX_SIGDET_CNTRL, 0x03), 327 QMP_PHY_INIT_CFG(QSERDES_V3_RX_SIGDET_DEGLITCH_CNTRL, 0x16), 328 QMP_PHY_INIT_CFG(QSERDES_V3_RX_UCDR_SO_SATURATION_AND_ENABLE, 0x75), 329}; 330 331static const struct qmp_phy_init_tbl qmp_v3_usb3_pcs_tbl[] = { 332 /* FLL settings */ 333 QMP_PHY_INIT_CFG(QPHY_V3_PCS_FLL_CNTRL2, 0x83), 334 QMP_PHY_INIT_CFG(QPHY_V3_PCS_FLL_CNT_VAL_L, 0x09), 335 QMP_PHY_INIT_CFG(QPHY_V3_PCS_FLL_CNT_VAL_H_TOL, 0xa2), 336 QMP_PHY_INIT_CFG(QPHY_V3_PCS_FLL_MAN_CODE, 0x40), 337 QMP_PHY_INIT_CFG(QPHY_V3_PCS_FLL_CNTRL1, 0x02), 338 339 /* Lock Det settings */ 340 QMP_PHY_INIT_CFG(QPHY_V3_PCS_LOCK_DETECT_CONFIG1, 0xd1), 341 QMP_PHY_INIT_CFG(QPHY_V3_PCS_LOCK_DETECT_CONFIG2, 0x1f), 342 QMP_PHY_INIT_CFG(QPHY_V3_PCS_LOCK_DETECT_CONFIG3, 0x47), 343 QMP_PHY_INIT_CFG(QPHY_V3_PCS_POWER_STATE_CONFIG2, 0x1b), 344 345 QMP_PHY_INIT_CFG(QPHY_V3_PCS_RX_SIGDET_LVL, 0xba), 346 QMP_PHY_INIT_CFG(QPHY_V3_PCS_TXMGN_V0, 0x9f), 347 QMP_PHY_INIT_CFG(QPHY_V3_PCS_TXMGN_V1, 0x9f), 348 QMP_PHY_INIT_CFG(QPHY_V3_PCS_TXMGN_V2, 0xb7), 349 QMP_PHY_INIT_CFG(QPHY_V3_PCS_TXMGN_V3, 0x4e), 350 QMP_PHY_INIT_CFG(QPHY_V3_PCS_TXMGN_V4, 0x65), 351 QMP_PHY_INIT_CFG(QPHY_V3_PCS_TXMGN_LS, 0x6b), 352 QMP_PHY_INIT_CFG(QPHY_V3_PCS_TXDEEMPH_M6DB_V0, 0x15), 353 QMP_PHY_INIT_CFG(QPHY_V3_PCS_TXDEEMPH_M3P5DB_V0, 0x0d), 354 QMP_PHY_INIT_CFG(QPHY_V3_PCS_TXDEEMPH_M6DB_V1, 0x15), 355 QMP_PHY_INIT_CFG(QPHY_V3_PCS_TXDEEMPH_M3P5DB_V1, 0x0d), 356 QMP_PHY_INIT_CFG(QPHY_V3_PCS_TXDEEMPH_M6DB_V2, 0x15), 357 QMP_PHY_INIT_CFG(QPHY_V3_PCS_TXDEEMPH_M3P5DB_V2, 0x0d), 358 QMP_PHY_INIT_CFG(QPHY_V3_PCS_TXDEEMPH_M6DB_V3, 0x15), 359 QMP_PHY_INIT_CFG(QPHY_V3_PCS_TXDEEMPH_M3P5DB_V3, 0x1d), 360 QMP_PHY_INIT_CFG(QPHY_V3_PCS_TXDEEMPH_M6DB_V4, 0x15), 361 QMP_PHY_INIT_CFG(QPHY_V3_PCS_TXDEEMPH_M3P5DB_V4, 0x0d), 362 QMP_PHY_INIT_CFG(QPHY_V3_PCS_TXDEEMPH_M6DB_LS, 0x15), 363 QMP_PHY_INIT_CFG(QPHY_V3_PCS_TXDEEMPH_M3P5DB_LS, 0x0d), 364 365 QMP_PHY_INIT_CFG(QPHY_V3_PCS_RATE_SLEW_CNTRL, 0x02), 366 QMP_PHY_INIT_CFG(QPHY_V3_PCS_PWRUP_RESET_DLY_TIME_AUXCLK, 0x04), 367 QMP_PHY_INIT_CFG(QPHY_V3_PCS_TSYNC_RSYNC_TIME, 0x44), 368 QMP_PHY_INIT_CFG(QPHY_V3_PCS_PWRUP_RESET_DLY_TIME_AUXCLK, 0x04), 369 QMP_PHY_INIT_CFG(QPHY_V3_PCS_RCVR_DTCT_DLY_P1U2_L, 0xe7), 370 QMP_PHY_INIT_CFG(QPHY_V3_PCS_RCVR_DTCT_DLY_P1U2_H, 0x03), 371 QMP_PHY_INIT_CFG(QPHY_V3_PCS_RCVR_DTCT_DLY_U3_L, 0x40), 372 QMP_PHY_INIT_CFG(QPHY_V3_PCS_RCVR_DTCT_DLY_U3_H, 0x00), 373 QMP_PHY_INIT_CFG(QPHY_V3_PCS_RXEQTRAINING_WAIT_TIME, 0x75), 374 QMP_PHY_INIT_CFG(QPHY_V3_PCS_LFPS_TX_ECSTART_EQTLOCK, 0x86), 375 QMP_PHY_INIT_CFG(QPHY_V3_PCS_RXEQTRAINING_RUN_TIME, 0x13), 376}; 377 378static const struct qmp_phy_init_tbl sm6350_usb3_rx_tbl[] = { 379 QMP_PHY_INIT_CFG(QSERDES_V3_RX_UCDR_FASTLOCK_FO_GAIN, 0x0b), 380 QMP_PHY_INIT_CFG(QSERDES_V3_RX_RX_EQU_ADAPTOR_CNTRL2, 0x0f), 381 QMP_PHY_INIT_CFG(QSERDES_V3_RX_RX_EQU_ADAPTOR_CNTRL3, 0x4e), 382 QMP_PHY_INIT_CFG(QSERDES_V3_RX_RX_EQU_ADAPTOR_CNTRL4, 0x18), 383 QMP_PHY_INIT_CFG(QSERDES_V3_RX_RX_EQ_OFFSET_ADAPTOR_CNTRL1, 0x77), 384 QMP_PHY_INIT_CFG(QSERDES_V3_RX_RX_OFFSET_ADAPTOR_CNTRL2, 0x80), 385 QMP_PHY_INIT_CFG(QSERDES_V3_RX_SIGDET_CNTRL, 0x03), 386 QMP_PHY_INIT_CFG(QSERDES_V3_RX_SIGDET_DEGLITCH_CNTRL, 0x16), 387 QMP_PHY_INIT_CFG(QSERDES_V3_RX_RX_MODE_00, 0x05), 388 QMP_PHY_INIT_CFG(QSERDES_V3_RX_UCDR_SO_SATURATION_AND_ENABLE, 0x75), 389}; 390 391static const struct qmp_phy_init_tbl sm6350_usb3_pcs_tbl[] = { 392 /* FLL settings */ 393 QMP_PHY_INIT_CFG(QPHY_V3_PCS_FLL_CNTRL2, 0x83), 394 QMP_PHY_INIT_CFG(QPHY_V3_PCS_FLL_CNT_VAL_L, 0x09), 395 QMP_PHY_INIT_CFG(QPHY_V3_PCS_FLL_CNT_VAL_H_TOL, 0xa2), 396 QMP_PHY_INIT_CFG(QPHY_V3_PCS_FLL_MAN_CODE, 0x40), 397 QMP_PHY_INIT_CFG(QPHY_V3_PCS_FLL_CNTRL1, 0x02), 398 399 /* Lock Det settings */ 400 QMP_PHY_INIT_CFG(QPHY_V3_PCS_LOCK_DETECT_CONFIG1, 0xd1), 401 QMP_PHY_INIT_CFG(QPHY_V3_PCS_LOCK_DETECT_CONFIG2, 0x1f), 402 QMP_PHY_INIT_CFG(QPHY_V3_PCS_LOCK_DETECT_CONFIG3, 0x47), 403 QMP_PHY_INIT_CFG(QPHY_V3_PCS_POWER_STATE_CONFIG2, 0x1b), 404 405 QMP_PHY_INIT_CFG(QPHY_V3_PCS_RX_SIGDET_LVL, 0xcc), 406 QMP_PHY_INIT_CFG(QPHY_V3_PCS_TXMGN_V0, 0x9f), 407 QMP_PHY_INIT_CFG(QPHY_V3_PCS_TXMGN_V1, 0x9f), 408 QMP_PHY_INIT_CFG(QPHY_V3_PCS_TXMGN_V2, 0xb7), 409 QMP_PHY_INIT_CFG(QPHY_V3_PCS_TXMGN_V3, 0x4e), 410 QMP_PHY_INIT_CFG(QPHY_V3_PCS_TXMGN_V4, 0x65), 411 QMP_PHY_INIT_CFG(QPHY_V3_PCS_TXMGN_LS, 0x6b), 412 QMP_PHY_INIT_CFG(QPHY_V3_PCS_TXDEEMPH_M6DB_V0, 0x15), 413 QMP_PHY_INIT_CFG(QPHY_V3_PCS_TXDEEMPH_M3P5DB_V0, 0x0d), 414 QMP_PHY_INIT_CFG(QPHY_V3_PCS_TXDEEMPH_M6DB_V1, 0x15), 415 QMP_PHY_INIT_CFG(QPHY_V3_PCS_TXDEEMPH_M3P5DB_V1, 0x0d), 416 QMP_PHY_INIT_CFG(QPHY_V3_PCS_TXDEEMPH_M6DB_V2, 0x15), 417 QMP_PHY_INIT_CFG(QPHY_V3_PCS_TXDEEMPH_M3P5DB_V2, 0x0d), 418 QMP_PHY_INIT_CFG(QPHY_V3_PCS_TXDEEMPH_M6DB_V3, 0x15), 419 QMP_PHY_INIT_CFG(QPHY_V3_PCS_TXDEEMPH_M3P5DB_V3, 0x1d), 420 QMP_PHY_INIT_CFG(QPHY_V3_PCS_TXDEEMPH_M6DB_V4, 0x15), 421 QMP_PHY_INIT_CFG(QPHY_V3_PCS_TXDEEMPH_M3P5DB_V4, 0x0d), 422 QMP_PHY_INIT_CFG(QPHY_V3_PCS_TXDEEMPH_M6DB_LS, 0x15), 423 QMP_PHY_INIT_CFG(QPHY_V3_PCS_TXDEEMPH_M3P5DB_LS, 0x0d), 424 425 QMP_PHY_INIT_CFG(QPHY_V3_PCS_RATE_SLEW_CNTRL, 0x02), 426 QMP_PHY_INIT_CFG(QPHY_V3_PCS_PWRUP_RESET_DLY_TIME_AUXCLK, 0x04), 427 QMP_PHY_INIT_CFG(QPHY_V3_PCS_TSYNC_RSYNC_TIME, 0x44), 428 QMP_PHY_INIT_CFG(QPHY_V3_PCS_PWRUP_RESET_DLY_TIME_AUXCLK, 0x04), 429 QMP_PHY_INIT_CFG(QPHY_V3_PCS_RCVR_DTCT_DLY_P1U2_L, 0xe7), 430 QMP_PHY_INIT_CFG(QPHY_V3_PCS_RCVR_DTCT_DLY_P1U2_H, 0x03), 431 QMP_PHY_INIT_CFG(QPHY_V3_PCS_RCVR_DTCT_DLY_U3_L, 0x40), 432 QMP_PHY_INIT_CFG(QPHY_V3_PCS_RCVR_DTCT_DLY_U3_H, 0x00), 433 QMP_PHY_INIT_CFG(QPHY_V3_PCS_RXEQTRAINING_WAIT_TIME, 0x75), 434 QMP_PHY_INIT_CFG(QPHY_V3_PCS_LFPS_TX_ECSTART_EQTLOCK, 0x86), 435 QMP_PHY_INIT_CFG(QPHY_V3_PCS_RXEQTRAINING_RUN_TIME, 0x13), 436 QMP_PHY_INIT_CFG(QPHY_V3_PCS_LFPS_DET_HIGH_COUNT_VAL, 0x04), 437 438 QMP_PHY_INIT_CFG(QPHY_V3_PCS_REFGEN_REQ_CONFIG1, 0x21), 439 QMP_PHY_INIT_CFG(QPHY_V3_PCS_REFGEN_REQ_CONFIG2, 0x60), 440}; 441 442static const struct qmp_phy_init_tbl sm8150_usb3_serdes_tbl[] = { 443 QMP_PHY_INIT_CFG(QSERDES_V4_COM_SSC_EN_CENTER, 0x01), 444 QMP_PHY_INIT_CFG(QSERDES_V4_COM_SSC_PER1, 0x31), 445 QMP_PHY_INIT_CFG(QSERDES_V4_COM_SSC_PER2, 0x01), 446 QMP_PHY_INIT_CFG(QSERDES_V4_COM_SSC_STEP_SIZE1_MODE0, 0xde), 447 QMP_PHY_INIT_CFG(QSERDES_V4_COM_SSC_STEP_SIZE2_MODE0, 0x07), 448 QMP_PHY_INIT_CFG(QSERDES_V4_COM_SSC_STEP_SIZE1_MODE1, 0xde), 449 QMP_PHY_INIT_CFG(QSERDES_V4_COM_SSC_STEP_SIZE2_MODE1, 0x07), 450 QMP_PHY_INIT_CFG(QSERDES_V4_COM_SYSCLK_BUF_ENABLE, 0x0a), 451 QMP_PHY_INIT_CFG(QSERDES_V4_COM_CMN_IPTRIM, 0x20), 452 QMP_PHY_INIT_CFG(QSERDES_V4_COM_CP_CTRL_MODE0, 0x06), 453 QMP_PHY_INIT_CFG(QSERDES_V4_COM_CP_CTRL_MODE1, 0x06), 454 QMP_PHY_INIT_CFG(QSERDES_V4_COM_PLL_RCTRL_MODE0, 0x16), 455 QMP_PHY_INIT_CFG(QSERDES_V4_COM_PLL_RCTRL_MODE1, 0x16), 456 QMP_PHY_INIT_CFG(QSERDES_V4_COM_PLL_CCTRL_MODE0, 0x36), 457 QMP_PHY_INIT_CFG(QSERDES_V4_COM_PLL_CCTRL_MODE1, 0x36), 458 QMP_PHY_INIT_CFG(QSERDES_V4_COM_SYSCLK_EN_SEL, 0x1a), 459 QMP_PHY_INIT_CFG(QSERDES_V4_COM_LOCK_CMP_EN, 0x04), 460 QMP_PHY_INIT_CFG(QSERDES_V4_COM_LOCK_CMP1_MODE0, 0x14), 461 QMP_PHY_INIT_CFG(QSERDES_V4_COM_LOCK_CMP2_MODE0, 0x34), 462 QMP_PHY_INIT_CFG(QSERDES_V4_COM_LOCK_CMP1_MODE1, 0x34), 463 QMP_PHY_INIT_CFG(QSERDES_V4_COM_LOCK_CMP2_MODE1, 0x82), 464 QMP_PHY_INIT_CFG(QSERDES_V4_COM_DEC_START_MODE0, 0x82), 465 QMP_PHY_INIT_CFG(QSERDES_V4_COM_DEC_START_MODE1, 0x82), 466 QMP_PHY_INIT_CFG(QSERDES_V4_COM_DIV_FRAC_START1_MODE0, 0xab), 467 QMP_PHY_INIT_CFG(QSERDES_V4_COM_DIV_FRAC_START2_MODE0, 0xea), 468 QMP_PHY_INIT_CFG(QSERDES_V4_COM_DIV_FRAC_START3_MODE0, 0x02), 469 QMP_PHY_INIT_CFG(QSERDES_V4_COM_VCO_TUNE_MAP, 0x02), 470 QMP_PHY_INIT_CFG(QSERDES_V4_COM_DIV_FRAC_START1_MODE1, 0xab), 471 QMP_PHY_INIT_CFG(QSERDES_V4_COM_DIV_FRAC_START2_MODE1, 0xea), 472 QMP_PHY_INIT_CFG(QSERDES_V4_COM_DIV_FRAC_START3_MODE1, 0x02), 473 QMP_PHY_INIT_CFG(QSERDES_V4_COM_VCO_TUNE1_MODE0, 0x24), 474 QMP_PHY_INIT_CFG(QSERDES_V4_COM_VCO_TUNE1_MODE1, 0x24), 475 QMP_PHY_INIT_CFG(QSERDES_V4_COM_VCO_TUNE2_MODE1, 0x02), 476 QMP_PHY_INIT_CFG(QSERDES_V4_COM_HSCLK_SEL, 0x01), 477 QMP_PHY_INIT_CFG(QSERDES_V4_COM_CORECLK_DIV_MODE1, 0x08), 478 QMP_PHY_INIT_CFG(QSERDES_V4_COM_BIN_VCOCAL_CMP_CODE1_MODE0, 0xca), 479 QMP_PHY_INIT_CFG(QSERDES_V4_COM_BIN_VCOCAL_CMP_CODE2_MODE0, 0x1e), 480 QMP_PHY_INIT_CFG(QSERDES_V4_COM_BIN_VCOCAL_CMP_CODE1_MODE1, 0xca), 481 QMP_PHY_INIT_CFG(QSERDES_V4_COM_BIN_VCOCAL_CMP_CODE2_MODE1, 0x1e), 482 QMP_PHY_INIT_CFG(QSERDES_V4_COM_BIN_VCOCAL_HSCLK_SEL, 0x11), 483}; 484 485static const struct qmp_phy_init_tbl sm8150_usb3_tx_tbl[] = { 486 QMP_PHY_INIT_CFG(QSERDES_V4_TX_RES_CODE_LANE_TX, 0x00), 487 QMP_PHY_INIT_CFG(QSERDES_V4_TX_RES_CODE_LANE_RX, 0x00), 488 QMP_PHY_INIT_CFG(QSERDES_V4_TX_LANE_MODE_1, 0xd5), 489 QMP_PHY_INIT_CFG(QSERDES_V4_TX_RCV_DETECT_LVL_2, 0x12), 490 QMP_PHY_INIT_CFG(QSERDES_V4_TX_PI_QEC_CTRL, 0x20), 491}; 492 493static const struct qmp_phy_init_tbl sm8150_usb3_rx_tbl[] = { 494 QMP_PHY_INIT_CFG(QSERDES_V4_RX_UCDR_SO_GAIN, 0x05), 495 QMP_PHY_INIT_CFG(QSERDES_V4_RX_UCDR_FASTLOCK_FO_GAIN, 0x2f), 496 QMP_PHY_INIT_CFG(QSERDES_V4_RX_UCDR_SO_SATURATION_AND_ENABLE, 0x7f), 497 QMP_PHY_INIT_CFG(QSERDES_V4_RX_UCDR_FASTLOCK_COUNT_LOW, 0xff), 498 QMP_PHY_INIT_CFG(QSERDES_V4_RX_UCDR_FASTLOCK_COUNT_HIGH, 0x0f), 499 QMP_PHY_INIT_CFG(QSERDES_V4_RX_UCDR_PI_CONTROLS, 0x99), 500 QMP_PHY_INIT_CFG(QSERDES_V4_RX_UCDR_SB2_THRESH1, 0x04), 501 QMP_PHY_INIT_CFG(QSERDES_V4_RX_UCDR_SB2_THRESH2, 0x08), 502 QMP_PHY_INIT_CFG(QSERDES_V4_RX_UCDR_SB2_GAIN1, 0x05), 503 QMP_PHY_INIT_CFG(QSERDES_V4_RX_UCDR_SB2_GAIN2, 0x05), 504 QMP_PHY_INIT_CFG(QSERDES_V4_RX_VGA_CAL_CNTRL1, 0x54), 505 QMP_PHY_INIT_CFG(QSERDES_V4_RX_VGA_CAL_CNTRL2, 0x0e), 506 QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_EQU_ADAPTOR_CNTRL2, 0x0f), 507 QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_EQU_ADAPTOR_CNTRL3, 0x4a), 508 QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_EQU_ADAPTOR_CNTRL4, 0x0a), 509 QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_IDAC_TSETTLE_LOW, 0xc0), 510 QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_IDAC_TSETTLE_HIGH, 0x00), 511 QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_EQ_OFFSET_ADAPTOR_CNTRL1, 0x77), 512 QMP_PHY_INIT_CFG(QSERDES_V4_RX_SIGDET_CNTRL, 0x04), 513 QMP_PHY_INIT_CFG(QSERDES_V4_RX_SIGDET_DEGLITCH_CNTRL, 0x0e), 514 QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_00_LOW, 0xbf), 515 QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_00_HIGH, 0xbf), 516 QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_00_HIGH2, 0x3f), 517 QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_00_HIGH3, 0x7f), 518 QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_00_HIGH4, 0x94), 519 QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_01_LOW, 0xdc), 520 QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_01_HIGH, 0xdc), 521 QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_01_HIGH2, 0x5c), 522 QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_01_HIGH3, 0x0b), 523 QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_01_HIGH4, 0xb3), 524 QMP_PHY_INIT_CFG(QSERDES_V4_RX_DFE_EN_TIMER, 0x04), 525 QMP_PHY_INIT_CFG(QSERDES_V4_RX_DFE_CTLE_POST_CAL_OFFSET, 0x38), 526 QMP_PHY_INIT_CFG(QSERDES_V4_RX_AUX_DATA_TCOARSE_TFINE, 0xa0), 527 QMP_PHY_INIT_CFG(QSERDES_V4_RX_DCC_CTRL1, 0x0c), 528 QMP_PHY_INIT_CFG(QSERDES_V4_RX_GM_CAL, 0x1f), 529 QMP_PHY_INIT_CFG(QSERDES_V4_RX_VTH_CODE, 0x10), 530}; 531 532static const struct qmp_phy_init_tbl sm8150_usb3_pcs_tbl[] = { 533 /* Lock Det settings */ 534 QMP_PHY_INIT_CFG(QPHY_V4_PCS_LOCK_DETECT_CONFIG1, 0xd0), 535 QMP_PHY_INIT_CFG(QPHY_V4_PCS_LOCK_DETECT_CONFIG2, 0x07), 536 QMP_PHY_INIT_CFG(QPHY_V4_PCS_LOCK_DETECT_CONFIG6, 0x13), 537 538 QMP_PHY_INIT_CFG(QPHY_V4_PCS_REFGEN_REQ_CONFIG1, 0x21), 539 QMP_PHY_INIT_CFG(QPHY_V4_PCS_RX_SIGDET_LVL, 0xaa), 540 QMP_PHY_INIT_CFG(QPHY_V4_PCS_CDR_RESET_TIME, 0x0a), 541 QMP_PHY_INIT_CFG(QPHY_V4_PCS_ALIGN_DETECT_CONFIG1, 0x88), 542 QMP_PHY_INIT_CFG(QPHY_V4_PCS_ALIGN_DETECT_CONFIG2, 0x13), 543 QMP_PHY_INIT_CFG(QPHY_V4_PCS_PCS_TX_RX_CONFIG, 0x0c), 544 QMP_PHY_INIT_CFG(QPHY_V4_PCS_EQ_CONFIG1, 0x4b), 545 QMP_PHY_INIT_CFG(QPHY_V4_PCS_EQ_CONFIG5, 0x10), 546}; 547 548static const struct qmp_phy_init_tbl sm8150_usb3_pcs_usb_tbl[] = { 549 QMP_PHY_INIT_CFG(QPHY_V4_PCS_USB3_LFPS_DET_HIGH_COUNT_VAL, 0xf8), 550 QMP_PHY_INIT_CFG(QPHY_V4_PCS_USB3_RXEQTRAINING_DFE_TIME_S2, 0x07), 551}; 552 553static const struct qmp_phy_init_tbl sm8250_usb3_tx_tbl[] = { 554 QMP_PHY_INIT_CFG(QSERDES_V4_TX_RES_CODE_LANE_TX, 0x60), 555 QMP_PHY_INIT_CFG(QSERDES_V4_TX_RES_CODE_LANE_RX, 0x60), 556 QMP_PHY_INIT_CFG(QSERDES_V4_TX_RES_CODE_LANE_OFFSET_TX, 0x11), 557 QMP_PHY_INIT_CFG(QSERDES_V4_TX_RES_CODE_LANE_OFFSET_RX, 0x02), 558 QMP_PHY_INIT_CFG(QSERDES_V4_TX_LANE_MODE_1, 0xd5), 559 QMP_PHY_INIT_CFG(QSERDES_V4_TX_RCV_DETECT_LVL_2, 0x12), 560 QMP_PHY_INIT_CFG_LANE(QSERDES_V4_TX_PI_QEC_CTRL, 0x40, 1), 561 QMP_PHY_INIT_CFG_LANE(QSERDES_V4_TX_PI_QEC_CTRL, 0x54, 2), 562}; 563 564static const struct qmp_phy_init_tbl sm8250_usb3_rx_tbl[] = { 565 QMP_PHY_INIT_CFG(QSERDES_V4_RX_UCDR_SO_GAIN, 0x06), 566 QMP_PHY_INIT_CFG(QSERDES_V4_RX_UCDR_FASTLOCK_FO_GAIN, 0x2f), 567 QMP_PHY_INIT_CFG(QSERDES_V4_RX_UCDR_SO_SATURATION_AND_ENABLE, 0x7f), 568 QMP_PHY_INIT_CFG(QSERDES_V4_RX_UCDR_FASTLOCK_COUNT_LOW, 0xff), 569 QMP_PHY_INIT_CFG(QSERDES_V4_RX_UCDR_FASTLOCK_COUNT_HIGH, 0x0f), 570 QMP_PHY_INIT_CFG(QSERDES_V4_RX_UCDR_PI_CONTROLS, 0x99), 571 QMP_PHY_INIT_CFG(QSERDES_V4_RX_UCDR_SB2_THRESH1, 0x04), 572 QMP_PHY_INIT_CFG(QSERDES_V4_RX_UCDR_SB2_THRESH2, 0x08), 573 QMP_PHY_INIT_CFG(QSERDES_V4_RX_UCDR_SB2_GAIN1, 0x05), 574 QMP_PHY_INIT_CFG(QSERDES_V4_RX_UCDR_SB2_GAIN2, 0x05), 575 QMP_PHY_INIT_CFG(QSERDES_V4_RX_VGA_CAL_CNTRL1, 0x54), 576 QMP_PHY_INIT_CFG(QSERDES_V4_RX_VGA_CAL_CNTRL2, 0x0c), 577 QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_EQU_ADAPTOR_CNTRL2, 0x0f), 578 QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_EQU_ADAPTOR_CNTRL3, 0x4a), 579 QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_EQU_ADAPTOR_CNTRL4, 0x0a), 580 QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_IDAC_TSETTLE_LOW, 0xc0), 581 QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_IDAC_TSETTLE_HIGH, 0x00), 582 QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_EQ_OFFSET_ADAPTOR_CNTRL1, 0x77), 583 QMP_PHY_INIT_CFG(QSERDES_V4_RX_SIGDET_CNTRL, 0x04), 584 QMP_PHY_INIT_CFG(QSERDES_V4_RX_SIGDET_DEGLITCH_CNTRL, 0x0e), 585 QMP_PHY_INIT_CFG_LANE(QSERDES_V4_RX_RX_MODE_00_LOW, 0xff, 1), 586 QMP_PHY_INIT_CFG_LANE(QSERDES_V4_RX_RX_MODE_00_LOW, 0x7f, 2), 587 QMP_PHY_INIT_CFG_LANE(QSERDES_V4_RX_RX_MODE_00_HIGH, 0x7f, 1), 588 QMP_PHY_INIT_CFG_LANE(QSERDES_V4_RX_RX_MODE_00_HIGH, 0xff, 2), 589 QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_00_HIGH2, 0x7f), 590 QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_00_HIGH3, 0x7f), 591 QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_00_HIGH4, 0x97), 592 QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_01_LOW, 0xdc), 593 QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_01_HIGH, 0xdc), 594 QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_01_HIGH2, 0x5c), 595 QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_01_HIGH3, 0x7b), 596 QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_01_HIGH4, 0xb4), 597 QMP_PHY_INIT_CFG(QSERDES_V4_RX_DFE_EN_TIMER, 0x04), 598 QMP_PHY_INIT_CFG(QSERDES_V4_RX_DFE_CTLE_POST_CAL_OFFSET, 0x38), 599 QMP_PHY_INIT_CFG(QSERDES_V4_RX_AUX_DATA_TCOARSE_TFINE, 0xa0), 600 QMP_PHY_INIT_CFG(QSERDES_V4_RX_DCC_CTRL1, 0x0c), 601 QMP_PHY_INIT_CFG(QSERDES_V4_RX_GM_CAL, 0x1f), 602 QMP_PHY_INIT_CFG(QSERDES_V4_RX_VTH_CODE, 0x10), 603}; 604 605static const struct qmp_phy_init_tbl sm8250_usb3_pcs_tbl[] = { 606 QMP_PHY_INIT_CFG(QPHY_V4_PCS_LOCK_DETECT_CONFIG1, 0xd0), 607 QMP_PHY_INIT_CFG(QPHY_V4_PCS_LOCK_DETECT_CONFIG2, 0x07), 608 QMP_PHY_INIT_CFG(QPHY_V4_PCS_LOCK_DETECT_CONFIG3, 0x20), 609 QMP_PHY_INIT_CFG(QPHY_V4_PCS_LOCK_DETECT_CONFIG6, 0x13), 610 QMP_PHY_INIT_CFG(QPHY_V4_PCS_REFGEN_REQ_CONFIG1, 0x21), 611 QMP_PHY_INIT_CFG(QPHY_V4_PCS_RX_SIGDET_LVL, 0xa9), 612 QMP_PHY_INIT_CFG(QPHY_V4_PCS_CDR_RESET_TIME, 0x0a), 613 QMP_PHY_INIT_CFG(QPHY_V4_PCS_ALIGN_DETECT_CONFIG1, 0x88), 614 QMP_PHY_INIT_CFG(QPHY_V4_PCS_ALIGN_DETECT_CONFIG2, 0x13), 615 QMP_PHY_INIT_CFG(QPHY_V4_PCS_PCS_TX_RX_CONFIG, 0x0c), 616 QMP_PHY_INIT_CFG(QPHY_V4_PCS_EQ_CONFIG1, 0x4b), 617 QMP_PHY_INIT_CFG(QPHY_V4_PCS_EQ_CONFIG5, 0x10), 618}; 619 620static const struct qmp_phy_init_tbl sm8250_usb3_pcs_usb_tbl[] = { 621 QMP_PHY_INIT_CFG(QPHY_V4_PCS_USB3_LFPS_DET_HIGH_COUNT_VAL, 0xf8), 622 QMP_PHY_INIT_CFG(QPHY_V4_PCS_USB3_RXEQTRAINING_DFE_TIME_S2, 0x07), 623}; 624 625static const struct qmp_phy_init_tbl sm8350_usb3_tx_tbl[] = { 626 QMP_PHY_INIT_CFG(QSERDES_V5_TX_RES_CODE_LANE_TX, 0x00), 627 QMP_PHY_INIT_CFG(QSERDES_V5_TX_RES_CODE_LANE_RX, 0x00), 628 QMP_PHY_INIT_CFG(QSERDES_V5_TX_RES_CODE_LANE_OFFSET_TX, 0x16), 629 QMP_PHY_INIT_CFG(QSERDES_V5_TX_RES_CODE_LANE_OFFSET_RX, 0x0e), 630 QMP_PHY_INIT_CFG(QSERDES_V5_TX_LANE_MODE_1, 0x35), 631 QMP_PHY_INIT_CFG(QSERDES_V5_TX_LANE_MODE_3, 0x3f), 632 QMP_PHY_INIT_CFG(QSERDES_V5_TX_LANE_MODE_4, 0x7f), 633 QMP_PHY_INIT_CFG(QSERDES_V5_TX_LANE_MODE_5, 0x3f), 634 QMP_PHY_INIT_CFG(QSERDES_V5_TX_RCV_DETECT_LVL_2, 0x12), 635 QMP_PHY_INIT_CFG(QSERDES_V5_TX_PI_QEC_CTRL, 0x21), 636}; 637 638static const struct qmp_phy_init_tbl sm8350_usb3_rx_tbl[] = { 639 QMP_PHY_INIT_CFG(QSERDES_V5_RX_UCDR_FO_GAIN, 0x0a), 640 QMP_PHY_INIT_CFG(QSERDES_V5_RX_UCDR_SO_GAIN, 0x05), 641 QMP_PHY_INIT_CFG(QSERDES_V5_RX_UCDR_FASTLOCK_FO_GAIN, 0x2f), 642 QMP_PHY_INIT_CFG(QSERDES_V5_RX_UCDR_SO_SATURATION_AND_ENABLE, 0x7f), 643 QMP_PHY_INIT_CFG(QSERDES_V5_RX_UCDR_FASTLOCK_COUNT_LOW, 0xff), 644 QMP_PHY_INIT_CFG(QSERDES_V5_RX_UCDR_FASTLOCK_COUNT_HIGH, 0x0f), 645 QMP_PHY_INIT_CFG(QSERDES_V5_RX_UCDR_PI_CONTROLS, 0x99), 646 QMP_PHY_INIT_CFG(QSERDES_V5_RX_UCDR_SB2_THRESH1, 0x08), 647 QMP_PHY_INIT_CFG(QSERDES_V5_RX_UCDR_SB2_THRESH2, 0x08), 648 QMP_PHY_INIT_CFG(QSERDES_V5_RX_UCDR_SB2_GAIN1, 0x00), 649 QMP_PHY_INIT_CFG(QSERDES_V5_RX_UCDR_SB2_GAIN2, 0x04), 650 QMP_PHY_INIT_CFG(QSERDES_V5_RX_VGA_CAL_CNTRL1, 0x54), 651 QMP_PHY_INIT_CFG(QSERDES_V5_RX_VGA_CAL_CNTRL2, 0x0f), 652 QMP_PHY_INIT_CFG(QSERDES_V5_RX_RX_EQU_ADAPTOR_CNTRL2, 0x0f), 653 QMP_PHY_INIT_CFG(QSERDES_V5_RX_RX_EQU_ADAPTOR_CNTRL3, 0x4a), 654 QMP_PHY_INIT_CFG(QSERDES_V5_RX_RX_EQU_ADAPTOR_CNTRL4, 0x0a), 655 QMP_PHY_INIT_CFG(QSERDES_V5_RX_RX_IDAC_TSETTLE_LOW, 0xc0), 656 QMP_PHY_INIT_CFG(QSERDES_V5_RX_RX_IDAC_TSETTLE_HIGH, 0x00), 657 QMP_PHY_INIT_CFG(QSERDES_V5_RX_RX_EQ_OFFSET_ADAPTOR_CNTRL1, 0x47), 658 QMP_PHY_INIT_CFG(QSERDES_V5_RX_SIGDET_CNTRL, 0x04), 659 QMP_PHY_INIT_CFG(QSERDES_V5_RX_SIGDET_DEGLITCH_CNTRL, 0x0e), 660 QMP_PHY_INIT_CFG(QSERDES_V5_RX_RX_MODE_00_LOW, 0xbb), 661 QMP_PHY_INIT_CFG(QSERDES_V5_RX_RX_MODE_00_HIGH, 0x7b), 662 QMP_PHY_INIT_CFG(QSERDES_V5_RX_RX_MODE_00_HIGH2, 0xbb), 663 QMP_PHY_INIT_CFG_LANE(QSERDES_V5_RX_RX_MODE_00_HIGH3, 0x3d, 1), 664 QMP_PHY_INIT_CFG_LANE(QSERDES_V5_RX_RX_MODE_00_HIGH3, 0x3c, 2), 665 QMP_PHY_INIT_CFG(QSERDES_V5_RX_RX_MODE_00_HIGH4, 0xdb), 666 QMP_PHY_INIT_CFG(QSERDES_V5_RX_RX_MODE_01_LOW, 0x64), 667 QMP_PHY_INIT_CFG(QSERDES_V5_RX_RX_MODE_01_HIGH, 0x24), 668 QMP_PHY_INIT_CFG(QSERDES_V5_RX_RX_MODE_01_HIGH2, 0xd2), 669 QMP_PHY_INIT_CFG(QSERDES_V5_RX_RX_MODE_01_HIGH3, 0x13), 670 QMP_PHY_INIT_CFG(QSERDES_V5_RX_RX_MODE_01_HIGH4, 0xa9), 671 QMP_PHY_INIT_CFG(QSERDES_V5_RX_DFE_EN_TIMER, 0x04), 672 QMP_PHY_INIT_CFG(QSERDES_V5_RX_DFE_CTLE_POST_CAL_OFFSET, 0x38), 673 QMP_PHY_INIT_CFG(QSERDES_V5_RX_AUX_DATA_TCOARSE_TFINE, 0xa0), 674 QMP_PHY_INIT_CFG(QSERDES_V5_RX_DCC_CTRL1, 0x0c), 675 QMP_PHY_INIT_CFG(QSERDES_V5_RX_GM_CAL, 0x00), 676 QMP_PHY_INIT_CFG(QSERDES_V5_RX_VTH_CODE, 0x10), 677}; 678 679static const struct qmp_phy_init_tbl sm8350_usb3_pcs_tbl[] = { 680 QMP_PHY_INIT_CFG(QPHY_V4_PCS_RCVR_DTCT_DLY_P1U2_L, 0xe7), 681 QMP_PHY_INIT_CFG(QPHY_V4_PCS_RCVR_DTCT_DLY_P1U2_H, 0x03), 682 QMP_PHY_INIT_CFG(QPHY_V4_PCS_LOCK_DETECT_CONFIG1, 0xd0), 683 QMP_PHY_INIT_CFG(QPHY_V4_PCS_LOCK_DETECT_CONFIG2, 0x07), 684 QMP_PHY_INIT_CFG(QPHY_V4_PCS_LOCK_DETECT_CONFIG3, 0x20), 685 QMP_PHY_INIT_CFG(QPHY_V4_PCS_LOCK_DETECT_CONFIG6, 0x13), 686 QMP_PHY_INIT_CFG(QPHY_V4_PCS_REFGEN_REQ_CONFIG1, 0x21), 687 QMP_PHY_INIT_CFG(QPHY_V4_PCS_RX_SIGDET_LVL, 0xaa), 688 QMP_PHY_INIT_CFG(QPHY_V4_PCS_CDR_RESET_TIME, 0x0a), 689 QMP_PHY_INIT_CFG(QPHY_V4_PCS_ALIGN_DETECT_CONFIG1, 0x88), 690 QMP_PHY_INIT_CFG(QPHY_V4_PCS_ALIGN_DETECT_CONFIG2, 0x13), 691 QMP_PHY_INIT_CFG(QPHY_V4_PCS_PCS_TX_RX_CONFIG, 0x0c), 692 QMP_PHY_INIT_CFG(QPHY_V4_PCS_EQ_CONFIG1, 0x4b), 693 QMP_PHY_INIT_CFG(QPHY_V4_PCS_EQ_CONFIG5, 0x10), 694}; 695 696static const struct qmp_phy_init_tbl sm8350_usb3_pcs_usb_tbl[] = { 697 QMP_PHY_INIT_CFG(QPHY_V5_PCS_USB3_RCVR_DTCT_DLY_U3_L, 0x40), 698 QMP_PHY_INIT_CFG(QPHY_V5_PCS_USB3_RCVR_DTCT_DLY_U3_H, 0x00), 699 QMP_PHY_INIT_CFG(QPHY_V5_PCS_USB3_LFPS_DET_HIGH_COUNT_VAL, 0xf8), 700 QMP_PHY_INIT_CFG(QPHY_V5_PCS_USB3_RXEQTRAINING_DFE_TIME_S2, 0x07), 701}; 702 703static const struct qmp_phy_init_tbl sm8550_usb3_serdes_tbl[] = { 704 QMP_PHY_INIT_CFG(QSERDES_V6_COM_SSC_STEP_SIZE1_MODE1, 0xc0), 705 QMP_PHY_INIT_CFG(QSERDES_V6_COM_SSC_STEP_SIZE2_MODE1, 0x01), 706 QMP_PHY_INIT_CFG(QSERDES_V6_COM_CP_CTRL_MODE1, 0x02), 707 QMP_PHY_INIT_CFG(QSERDES_V6_COM_PLL_RCTRL_MODE1, 0x16), 708 QMP_PHY_INIT_CFG(QSERDES_V6_COM_PLL_CCTRL_MODE1, 0x36), 709 QMP_PHY_INIT_CFG(QSERDES_V6_COM_CORECLK_DIV_MODE1, 0x04), 710 QMP_PHY_INIT_CFG(QSERDES_V6_COM_LOCK_CMP1_MODE1, 0x16), 711 QMP_PHY_INIT_CFG(QSERDES_V6_COM_LOCK_CMP2_MODE1, 0x41), 712 QMP_PHY_INIT_CFG(QSERDES_V6_COM_DEC_START_MODE1, 0x41), 713 QMP_PHY_INIT_CFG(QSERDES_V6_COM_DEC_START_MSB_MODE1, 0x00), 714 QMP_PHY_INIT_CFG(QSERDES_V6_COM_DIV_FRAC_START1_MODE1, 0x55), 715 QMP_PHY_INIT_CFG(QSERDES_V6_COM_DIV_FRAC_START2_MODE1, 0x75), 716 QMP_PHY_INIT_CFG(QSERDES_V6_COM_DIV_FRAC_START3_MODE1, 0x01), 717 QMP_PHY_INIT_CFG(QSERDES_V6_COM_HSCLK_SEL_1, 0x01), 718 QMP_PHY_INIT_CFG(QSERDES_V6_COM_VCO_TUNE1_MODE1, 0x25), 719 QMP_PHY_INIT_CFG(QSERDES_V6_COM_VCO_TUNE2_MODE1, 0x02), 720 QMP_PHY_INIT_CFG(QSERDES_V6_COM_BIN_VCOCAL_CMP_CODE1_MODE1, 0x5c), 721 QMP_PHY_INIT_CFG(QSERDES_V6_COM_BIN_VCOCAL_CMP_CODE2_MODE1, 0x0f), 722 QMP_PHY_INIT_CFG(QSERDES_V6_COM_BIN_VCOCAL_CMP_CODE1_MODE0, 0x5c), 723 QMP_PHY_INIT_CFG(QSERDES_V6_COM_BIN_VCOCAL_CMP_CODE2_MODE0, 0x0f), 724 QMP_PHY_INIT_CFG(QSERDES_V6_COM_SSC_STEP_SIZE1_MODE0, 0xc0), 725 QMP_PHY_INIT_CFG(QSERDES_V6_COM_SSC_STEP_SIZE2_MODE0, 0x01), 726 QMP_PHY_INIT_CFG(QSERDES_V6_COM_CP_CTRL_MODE0, 0x02), 727 QMP_PHY_INIT_CFG(QSERDES_V6_COM_PLL_RCTRL_MODE0, 0x16), 728 QMP_PHY_INIT_CFG(QSERDES_V6_COM_PLL_CCTRL_MODE0, 0x36), 729 QMP_PHY_INIT_CFG(QSERDES_V6_COM_LOCK_CMP1_MODE0, 0x08), 730 QMP_PHY_INIT_CFG(QSERDES_V6_COM_LOCK_CMP2_MODE0, 0x1a), 731 QMP_PHY_INIT_CFG(QSERDES_V6_COM_DEC_START_MODE0, 0x41), 732 QMP_PHY_INIT_CFG(QSERDES_V6_COM_DEC_START_MSB_MODE0, 0x00), 733 QMP_PHY_INIT_CFG(QSERDES_V6_COM_DIV_FRAC_START1_MODE0, 0x55), 734 QMP_PHY_INIT_CFG(QSERDES_V6_COM_DIV_FRAC_START2_MODE0, 0x75), 735 QMP_PHY_INIT_CFG(QSERDES_V6_COM_DIV_FRAC_START3_MODE0, 0x01), 736 QMP_PHY_INIT_CFG(QSERDES_V6_COM_VCO_TUNE1_MODE0, 0x25), 737 QMP_PHY_INIT_CFG(QSERDES_V6_COM_VCO_TUNE2_MODE0, 0x02), 738 QMP_PHY_INIT_CFG(QSERDES_V6_COM_BG_TIMER, 0x0a), 739 QMP_PHY_INIT_CFG(QSERDES_V6_COM_SSC_EN_CENTER, 0x01), 740 QMP_PHY_INIT_CFG(QSERDES_V6_COM_SSC_PER1, 0x62), 741 QMP_PHY_INIT_CFG(QSERDES_V6_COM_SSC_PER2, 0x02), 742 QMP_PHY_INIT_CFG(QSERDES_V6_COM_SYSCLK_BUF_ENABLE, 0x0c), 743 QMP_PHY_INIT_CFG(QSERDES_V6_COM_SYSCLK_EN_SEL, 0x1a), 744 QMP_PHY_INIT_CFG(QSERDES_V6_COM_LOCK_CMP_CFG, 0x14), 745 QMP_PHY_INIT_CFG(QSERDES_V6_COM_VCO_TUNE_MAP, 0x04), 746 QMP_PHY_INIT_CFG(QSERDES_V6_COM_CORE_CLK_EN, 0x20), 747 QMP_PHY_INIT_CFG(QSERDES_V6_COM_CMN_CONFIG_1, 0x16), 748 QMP_PHY_INIT_CFG(QSERDES_V6_COM_AUTO_GAIN_ADJ_CTRL_1, 0xb6), 749 QMP_PHY_INIT_CFG(QSERDES_V6_COM_AUTO_GAIN_ADJ_CTRL_2, 0x4b), 750 QMP_PHY_INIT_CFG(QSERDES_V6_COM_AUTO_GAIN_ADJ_CTRL_3, 0x37), 751 QMP_PHY_INIT_CFG(QSERDES_V6_COM_ADDITIONAL_MISC, 0x0c), 752}; 753 754static const struct qmp_phy_init_tbl sm8550_usb3_tx_tbl[] = { 755 QMP_PHY_INIT_CFG(QSERDES_V6_TX_RES_CODE_LANE_TX, 0x00), 756 QMP_PHY_INIT_CFG(QSERDES_V6_TX_RES_CODE_LANE_RX, 0x00), 757 QMP_PHY_INIT_CFG(QSERDES_V6_TX_RES_CODE_LANE_OFFSET_TX, 0x1f), 758 QMP_PHY_INIT_CFG(QSERDES_V6_TX_RES_CODE_LANE_OFFSET_RX, 0x09), 759 QMP_PHY_INIT_CFG(QSERDES_V6_TX_LANE_MODE_1, 0xf5), 760 QMP_PHY_INIT_CFG(QSERDES_V6_TX_LANE_MODE_3, 0x3f), 761 QMP_PHY_INIT_CFG(QSERDES_V6_TX_LANE_MODE_4, 0x3f), 762 QMP_PHY_INIT_CFG(QSERDES_V6_TX_LANE_MODE_5, 0x5f), 763 QMP_PHY_INIT_CFG(QSERDES_V6_TX_RCV_DETECT_LVL_2, 0x12), 764 QMP_PHY_INIT_CFG_LANE(QSERDES_V6_TX_PI_QEC_CTRL, 0x21, 1), 765 QMP_PHY_INIT_CFG_LANE(QSERDES_V6_TX_PI_QEC_CTRL, 0x05, 2), 766}; 767 768static const struct qmp_phy_init_tbl sm8550_usb3_rx_tbl[] = { 769 QMP_PHY_INIT_CFG(QSERDES_V6_RX_UCDR_FO_GAIN, 0x0a), 770 QMP_PHY_INIT_CFG(QSERDES_V6_RX_UCDR_SO_GAIN, 0x06), 771 QMP_PHY_INIT_CFG(QSERDES_V6_RX_UCDR_FASTLOCK_FO_GAIN, 0x2f), 772 QMP_PHY_INIT_CFG(QSERDES_V6_RX_UCDR_SO_SATURATION_AND_ENABLE, 0x7f), 773 QMP_PHY_INIT_CFG(QSERDES_V6_RX_UCDR_FASTLOCK_COUNT_LOW, 0xff), 774 QMP_PHY_INIT_CFG(QSERDES_V6_RX_UCDR_FASTLOCK_COUNT_HIGH, 0x0f), 775 QMP_PHY_INIT_CFG(QSERDES_V6_RX_UCDR_PI_CONTROLS, 0x99), 776 QMP_PHY_INIT_CFG(QSERDES_V6_RX_UCDR_SB2_THRESH1, 0x08), 777 QMP_PHY_INIT_CFG(QSERDES_V6_RX_UCDR_SB2_THRESH2, 0x08), 778 QMP_PHY_INIT_CFG(QSERDES_V6_RX_UCDR_SB2_GAIN1, 0x00), 779 QMP_PHY_INIT_CFG(QSERDES_V6_RX_UCDR_SB2_GAIN2, 0x0a), 780 QMP_PHY_INIT_CFG(QSERDES_V6_RX_AUX_DATA_TCOARSE_TFINE, 0xa0), 781 QMP_PHY_INIT_CFG(QSERDES_V6_RX_VGA_CAL_CNTRL1, 0x54), 782 QMP_PHY_INIT_CFG(QSERDES_V6_RX_VGA_CAL_CNTRL2, 0x0f), 783 QMP_PHY_INIT_CFG(QSERDES_V6_RX_GM_CAL, 0x13), 784 QMP_PHY_INIT_CFG(QSERDES_V6_RX_RX_EQU_ADAPTOR_CNTRL2, 0x0f), 785 QMP_PHY_INIT_CFG(QSERDES_V6_RX_RX_EQU_ADAPTOR_CNTRL3, 0x4a), 786 QMP_PHY_INIT_CFG(QSERDES_V6_RX_RX_EQU_ADAPTOR_CNTRL4, 0x0a), 787 QMP_PHY_INIT_CFG(QSERDES_V6_RX_RX_IDAC_TSETTLE_LOW, 0x07), 788 QMP_PHY_INIT_CFG(QSERDES_V6_RX_RX_IDAC_TSETTLE_HIGH, 0x00), 789 QMP_PHY_INIT_CFG(QSERDES_V6_RX_RX_EQ_OFFSET_ADAPTOR_CNTRL1, 0x47), 790 QMP_PHY_INIT_CFG(QSERDES_V6_RX_SIGDET_CNTRL, 0x04), 791 QMP_PHY_INIT_CFG(QSERDES_V6_RX_SIGDET_DEGLITCH_CNTRL, 0x0e), 792 QMP_PHY_INIT_CFG(QSERDES_V6_RX_RX_MODE_01_LOW, 0xdc), 793 QMP_PHY_INIT_CFG(QSERDES_V6_RX_RX_MODE_01_HIGH, 0x5c), 794 QMP_PHY_INIT_CFG(QSERDES_V6_RX_RX_MODE_01_HIGH2, 0x9c), 795 QMP_PHY_INIT_CFG(QSERDES_V6_RX_RX_MODE_01_HIGH3, 0x1d), 796 QMP_PHY_INIT_CFG(QSERDES_V6_RX_RX_MODE_01_HIGH4, 0x09), 797 QMP_PHY_INIT_CFG(QSERDES_V6_RX_DFE_EN_TIMER, 0x04), 798 QMP_PHY_INIT_CFG(QSERDES_V6_RX_DFE_CTLE_POST_CAL_OFFSET, 0x38), 799 QMP_PHY_INIT_CFG(QSERDES_V6_RX_DCC_CTRL1, 0x0c), 800 QMP_PHY_INIT_CFG(QSERDES_V6_RX_VTH_CODE, 0x10), 801 QMP_PHY_INIT_CFG(QSERDES_V6_RX_SIGDET_CAL_CTRL1, 0x14), 802 QMP_PHY_INIT_CFG(QSERDES_V6_RX_SIGDET_CAL_TRIM, 0x08), 803 804 QMP_PHY_INIT_CFG_LANE(QSERDES_V6_RX_RX_MODE_00_LOW, 0x3f, 1), 805 QMP_PHY_INIT_CFG_LANE(QSERDES_V6_RX_RX_MODE_00_HIGH, 0xbf, 1), 806 QMP_PHY_INIT_CFG_LANE(QSERDES_V6_RX_RX_MODE_00_HIGH2, 0xff, 1), 807 QMP_PHY_INIT_CFG_LANE(QSERDES_V6_RX_RX_MODE_00_HIGH3, 0xdf, 1), 808 QMP_PHY_INIT_CFG_LANE(QSERDES_V6_RX_RX_MODE_00_HIGH4, 0xed, 1), 809 810 QMP_PHY_INIT_CFG_LANE(QSERDES_V6_RX_RX_MODE_00_LOW, 0xbf, 2), 811 QMP_PHY_INIT_CFG_LANE(QSERDES_V6_RX_RX_MODE_00_HIGH, 0xbf, 2), 812 QMP_PHY_INIT_CFG_LANE(QSERDES_V6_RX_RX_MODE_00_HIGH2, 0xbf, 2), 813 QMP_PHY_INIT_CFG_LANE(QSERDES_V6_RX_RX_MODE_00_HIGH3, 0xdf, 2), 814 QMP_PHY_INIT_CFG_LANE(QSERDES_V6_RX_RX_MODE_00_HIGH4, 0xfd, 2), 815}; 816 817static const struct qmp_phy_init_tbl sm8550_usb3_pcs_tbl[] = { 818 QMP_PHY_INIT_CFG(QPHY_V6_PCS_LOCK_DETECT_CONFIG1, 0xc4), 819 QMP_PHY_INIT_CFG(QPHY_V6_PCS_LOCK_DETECT_CONFIG2, 0x89), 820 QMP_PHY_INIT_CFG(QPHY_V6_PCS_LOCK_DETECT_CONFIG3, 0x20), 821 QMP_PHY_INIT_CFG(QPHY_V6_PCS_LOCK_DETECT_CONFIG6, 0x13), 822 QMP_PHY_INIT_CFG(QPHY_V6_PCS_REFGEN_REQ_CONFIG1, 0x21), 823 QMP_PHY_INIT_CFG(QPHY_V6_PCS_RX_SIGDET_LVL, 0x99), 824 QMP_PHY_INIT_CFG(QPHY_V6_PCS_RCVR_DTCT_DLY_P1U2_L, 0xe7), 825 QMP_PHY_INIT_CFG(QPHY_V6_PCS_RCVR_DTCT_DLY_P1U2_H, 0x03), 826 QMP_PHY_INIT_CFG(QPHY_V6_PCS_CDR_RESET_TIME, 0x0a), 827 QMP_PHY_INIT_CFG(QPHY_V6_PCS_ALIGN_DETECT_CONFIG1, 0x88), 828 QMP_PHY_INIT_CFG(QPHY_V6_PCS_ALIGN_DETECT_CONFIG2, 0x13), 829 QMP_PHY_INIT_CFG(QPHY_V6_PCS_PCS_TX_RX_CONFIG, 0x0c), 830 QMP_PHY_INIT_CFG(QPHY_V6_PCS_EQ_CONFIG1, 0x4b), 831 QMP_PHY_INIT_CFG(QPHY_V6_PCS_EQ_CONFIG5, 0x10), 832}; 833 834static const struct qmp_phy_init_tbl sm8550_usb3_pcs_usb_tbl[] = { 835 QMP_PHY_INIT_CFG(QPHY_V6_PCS_USB3_LFPS_DET_HIGH_COUNT_VAL, 0xf8), 836 QMP_PHY_INIT_CFG(QPHY_V6_PCS_USB3_RXEQTRAINING_DFE_TIME_S2, 0x07), 837 QMP_PHY_INIT_CFG(QPHY_V6_PCS_USB3_RCVR_DTCT_DLY_U3_L, 0x40), 838 QMP_PHY_INIT_CFG(QPHY_V6_PCS_USB3_RCVR_DTCT_DLY_U3_H, 0x00), 839 QMP_PHY_INIT_CFG(QPHY_V6_PCS_USB3_POWER_STATE_CONFIG1, 0x68), 840}; 841 842static const struct qmp_phy_init_tbl qmp_v4_dp_serdes_tbl[] = { 843 QMP_PHY_INIT_CFG(QSERDES_V4_COM_SVS_MODE_CLK_SEL, 0x05), 844 QMP_PHY_INIT_CFG(QSERDES_V4_COM_SYSCLK_EN_SEL, 0x3b), 845 QMP_PHY_INIT_CFG(QSERDES_V4_COM_SYS_CLK_CTRL, 0x02), 846 QMP_PHY_INIT_CFG(QSERDES_V4_COM_CLK_ENABLE1, 0x0c), 847 QMP_PHY_INIT_CFG(QSERDES_V4_COM_SYSCLK_BUF_ENABLE, 0x06), 848 QMP_PHY_INIT_CFG(QSERDES_V4_COM_CLK_SELECT, 0x30), 849 QMP_PHY_INIT_CFG(QSERDES_V4_COM_PLL_IVCO, 0x0f), 850 QMP_PHY_INIT_CFG(QSERDES_V4_COM_PLL_CCTRL_MODE0, 0x36), 851 QMP_PHY_INIT_CFG(QSERDES_V4_COM_PLL_RCTRL_MODE0, 0x16), 852 QMP_PHY_INIT_CFG(QSERDES_V4_COM_CP_CTRL_MODE0, 0x06), 853 QMP_PHY_INIT_CFG(QSERDES_V4_COM_CMN_CONFIG, 0x02), 854 QMP_PHY_INIT_CFG(QSERDES_V4_COM_INTEGLOOP_GAIN0_MODE0, 0x3f), 855 QMP_PHY_INIT_CFG(QSERDES_V4_COM_INTEGLOOP_GAIN1_MODE0, 0x00), 856 QMP_PHY_INIT_CFG(QSERDES_V4_COM_VCO_TUNE_MAP, 0x00), 857 QMP_PHY_INIT_CFG(QSERDES_V4_COM_DIV_FRAC_START1_MODE0, 0x00), 858 QMP_PHY_INIT_CFG(QSERDES_V4_COM_BG_TIMER, 0x0a), 859 QMP_PHY_INIT_CFG(QSERDES_V4_COM_CORECLK_DIV_MODE0, 0x0a), 860 QMP_PHY_INIT_CFG(QSERDES_V4_COM_VCO_TUNE_CTRL, 0x00), 861 QMP_PHY_INIT_CFG(QSERDES_V4_COM_BIAS_EN_CLKBUFLR_EN, 0x17), 862 QMP_PHY_INIT_CFG(QSERDES_V4_COM_CORE_CLK_EN, 0x1f), 863}; 864 865static const struct qmp_phy_init_tbl qmp_v4_dp_serdes_tbl_rbr[] = { 866 QMP_PHY_INIT_CFG(QSERDES_V4_COM_HSCLK_SEL, 0x05), 867 QMP_PHY_INIT_CFG(QSERDES_V4_COM_DEC_START_MODE0, 0x69), 868 QMP_PHY_INIT_CFG(QSERDES_V4_COM_DIV_FRAC_START2_MODE0, 0x80), 869 QMP_PHY_INIT_CFG(QSERDES_V4_COM_DIV_FRAC_START3_MODE0, 0x07), 870 QMP_PHY_INIT_CFG(QSERDES_V4_COM_LOCK_CMP1_MODE0, 0x6f), 871 QMP_PHY_INIT_CFG(QSERDES_V4_COM_LOCK_CMP2_MODE0, 0x08), 872 QMP_PHY_INIT_CFG(QSERDES_V4_COM_LOCK_CMP_EN, 0x04), 873}; 874 875static const struct qmp_phy_init_tbl qmp_v4_dp_serdes_tbl_hbr[] = { 876 QMP_PHY_INIT_CFG(QSERDES_V4_COM_HSCLK_SEL, 0x03), 877 QMP_PHY_INIT_CFG(QSERDES_V4_COM_DEC_START_MODE0, 0x69), 878 QMP_PHY_INIT_CFG(QSERDES_V4_COM_DIV_FRAC_START2_MODE0, 0x80), 879 QMP_PHY_INIT_CFG(QSERDES_V4_COM_DIV_FRAC_START3_MODE0, 0x07), 880 QMP_PHY_INIT_CFG(QSERDES_V4_COM_LOCK_CMP1_MODE0, 0x0f), 881 QMP_PHY_INIT_CFG(QSERDES_V4_COM_LOCK_CMP2_MODE0, 0x0e), 882 QMP_PHY_INIT_CFG(QSERDES_V4_COM_LOCK_CMP_EN, 0x08), 883}; 884 885static const struct qmp_phy_init_tbl qmp_v4_dp_serdes_tbl_hbr2[] = { 886 QMP_PHY_INIT_CFG(QSERDES_V4_COM_HSCLK_SEL, 0x01), 887 QMP_PHY_INIT_CFG(QSERDES_V4_COM_DEC_START_MODE0, 0x8c), 888 QMP_PHY_INIT_CFG(QSERDES_V4_COM_DIV_FRAC_START2_MODE0, 0x00), 889 QMP_PHY_INIT_CFG(QSERDES_V4_COM_DIV_FRAC_START3_MODE0, 0x0a), 890 QMP_PHY_INIT_CFG(QSERDES_V4_COM_LOCK_CMP1_MODE0, 0x1f), 891 QMP_PHY_INIT_CFG(QSERDES_V4_COM_LOCK_CMP2_MODE0, 0x1c), 892 QMP_PHY_INIT_CFG(QSERDES_V4_COM_LOCK_CMP_EN, 0x08), 893}; 894 895static const struct qmp_phy_init_tbl qmp_v4_dp_serdes_tbl_hbr3[] = { 896 QMP_PHY_INIT_CFG(QSERDES_V4_COM_HSCLK_SEL, 0x00), 897 QMP_PHY_INIT_CFG(QSERDES_V4_COM_DEC_START_MODE0, 0x69), 898 QMP_PHY_INIT_CFG(QSERDES_V4_COM_DIV_FRAC_START2_MODE0, 0x80), 899 QMP_PHY_INIT_CFG(QSERDES_V4_COM_DIV_FRAC_START3_MODE0, 0x07), 900 QMP_PHY_INIT_CFG(QSERDES_V4_COM_LOCK_CMP1_MODE0, 0x2f), 901 QMP_PHY_INIT_CFG(QSERDES_V4_COM_LOCK_CMP2_MODE0, 0x2a), 902 QMP_PHY_INIT_CFG(QSERDES_V4_COM_LOCK_CMP_EN, 0x08), 903}; 904 905static const struct qmp_phy_init_tbl qmp_v4_dp_tx_tbl[] = { 906 QMP_PHY_INIT_CFG(QSERDES_V4_TX_VMODE_CTRL1, 0x40), 907 QMP_PHY_INIT_CFG(QSERDES_V4_TX_PRE_STALL_LDO_BOOST_EN, 0x30), 908 QMP_PHY_INIT_CFG(QSERDES_V4_TX_INTERFACE_SELECT, 0x3b), 909 QMP_PHY_INIT_CFG(QSERDES_V4_TX_CLKBUF_ENABLE, 0x0f), 910 QMP_PHY_INIT_CFG(QSERDES_V4_TX_RESET_TSYNC_EN, 0x03), 911 QMP_PHY_INIT_CFG(QSERDES_V4_TX_TRAN_DRVR_EMP_EN, 0x0f), 912 QMP_PHY_INIT_CFG(QSERDES_V4_TX_PARRATE_REC_DETECT_IDLE_EN, 0x00), 913 QMP_PHY_INIT_CFG(QSERDES_V4_TX_TX_INTERFACE_MODE, 0x00), 914 QMP_PHY_INIT_CFG(QSERDES_V4_TX_RES_CODE_LANE_OFFSET_TX, 0x11), 915 QMP_PHY_INIT_CFG(QSERDES_V4_TX_RES_CODE_LANE_OFFSET_RX, 0x11), 916 QMP_PHY_INIT_CFG(QSERDES_V4_TX_TX_BAND, 0x4), 917 QMP_PHY_INIT_CFG(QSERDES_V4_TX_TX_POL_INV, 0x0a), 918 QMP_PHY_INIT_CFG(QSERDES_V4_TX_TX_DRV_LVL, 0x2a), 919 QMP_PHY_INIT_CFG(QSERDES_V4_TX_TX_EMP_POST1_LVL, 0x20), 920}; 921 922static const struct qmp_phy_init_tbl qmp_v5_dp_serdes_tbl[] = { 923 QMP_PHY_INIT_CFG(QSERDES_V4_COM_SVS_MODE_CLK_SEL, 0x05), 924 QMP_PHY_INIT_CFG(QSERDES_V4_COM_SYSCLK_EN_SEL, 0x3b), 925 QMP_PHY_INIT_CFG(QSERDES_V4_COM_SYS_CLK_CTRL, 0x02), 926 QMP_PHY_INIT_CFG(QSERDES_V4_COM_CLK_ENABLE1, 0x0c), 927 QMP_PHY_INIT_CFG(QSERDES_V4_COM_SYSCLK_BUF_ENABLE, 0x06), 928 QMP_PHY_INIT_CFG(QSERDES_V4_COM_CLK_SELECT, 0x30), 929 QMP_PHY_INIT_CFG(QSERDES_V4_COM_PLL_IVCO, 0x0f), 930 QMP_PHY_INIT_CFG(QSERDES_V4_COM_PLL_CCTRL_MODE0, 0x36), 931 QMP_PHY_INIT_CFG(QSERDES_V4_COM_PLL_CCTRL_MODE1, 0x36), 932 QMP_PHY_INIT_CFG(QSERDES_V4_COM_PLL_RCTRL_MODE0, 0x16), 933 QMP_PHY_INIT_CFG(QSERDES_V4_COM_PLL_RCTRL_MODE1, 0x16), 934 QMP_PHY_INIT_CFG(QSERDES_V4_COM_CP_CTRL_MODE0, 0x06), 935 QMP_PHY_INIT_CFG(QSERDES_V4_COM_CP_CTRL_MODE1, 0x06), 936 QMP_PHY_INIT_CFG(QSERDES_V4_COM_CMN_CONFIG, 0x02), 937 QMP_PHY_INIT_CFG(QSERDES_V4_COM_INTEGLOOP_GAIN0_MODE0, 0x3f), 938 QMP_PHY_INIT_CFG(QSERDES_V4_COM_INTEGLOOP_GAIN1_MODE0, 0x00), 939 QMP_PHY_INIT_CFG(QSERDES_V4_COM_VCO_TUNE_MAP, 0x02), 940 QMP_PHY_INIT_CFG(QSERDES_V4_COM_DIV_FRAC_START1_MODE0, 0x00), 941 QMP_PHY_INIT_CFG(QSERDES_V4_COM_BG_TIMER, 0x0a), 942 QMP_PHY_INIT_CFG(QSERDES_V4_COM_CORECLK_DIV_MODE0, 0x0a), 943 QMP_PHY_INIT_CFG(QSERDES_V4_COM_VCO_TUNE_CTRL, 0x00), 944 QMP_PHY_INIT_CFG(QSERDES_V4_COM_BIAS_EN_CLKBUFLR_EN, 0x17), 945 QMP_PHY_INIT_CFG(QSERDES_V4_COM_CORE_CLK_EN, 0x1f), 946}; 947 948static const struct qmp_phy_init_tbl qmp_v5_dp_tx_tbl[] = { 949 QMP_PHY_INIT_CFG(QSERDES_V5_TX_VMODE_CTRL1, 0x40), 950 QMP_PHY_INIT_CFG(QSERDES_V5_TX_PRE_STALL_LDO_BOOST_EN, 0x30), 951 QMP_PHY_INIT_CFG(QSERDES_V5_TX_INTERFACE_SELECT, 0x3b), 952 QMP_PHY_INIT_CFG(QSERDES_V5_TX_CLKBUF_ENABLE, 0x0f), 953 QMP_PHY_INIT_CFG(QSERDES_V5_TX_RESET_TSYNC_EN, 0x03), 954 QMP_PHY_INIT_CFG(QSERDES_V5_TX_TRAN_DRVR_EMP_EN, 0x0f), 955 QMP_PHY_INIT_CFG(QSERDES_V5_TX_PARRATE_REC_DETECT_IDLE_EN, 0x00), 956 QMP_PHY_INIT_CFG(QSERDES_V5_TX_TX_INTERFACE_MODE, 0x00), 957 QMP_PHY_INIT_CFG(QSERDES_V5_TX_RES_CODE_LANE_OFFSET_TX, 0x11), 958 QMP_PHY_INIT_CFG(QSERDES_V5_TX_RES_CODE_LANE_OFFSET_RX, 0x11), 959 QMP_PHY_INIT_CFG(QSERDES_V5_TX_TX_BAND, 0x04), 960}; 961 962static const struct qmp_phy_init_tbl qmp_v5_5nm_dp_tx_tbl[] = { 963 QMP_PHY_INIT_CFG(QSERDES_V5_5NM_TX_LANE_MODE_3, 0x51), 964 QMP_PHY_INIT_CFG(QSERDES_V5_5NM_TX_TRANSCEIVER_BIAS_EN, 0x1a), 965 QMP_PHY_INIT_CFG(QSERDES_V5_5NM_TX_VMODE_CTRL1, 0x40), 966 QMP_PHY_INIT_CFG(QSERDES_V5_5NM_TX_PRE_STALL_LDO_BOOST_EN, 0x0), 967 QMP_PHY_INIT_CFG(QSERDES_V5_5NM_TX_INTERFACE_SELECT, 0xff), 968 QMP_PHY_INIT_CFG(QSERDES_V5_5NM_TX_CLKBUF_ENABLE, 0x0f), 969 QMP_PHY_INIT_CFG(QSERDES_V5_5NM_TX_RESET_TSYNC_EN, 0x03), 970 QMP_PHY_INIT_CFG(QSERDES_V5_5NM_TX_TRAN_DRVR_EMP_EN, 0xf), 971 QMP_PHY_INIT_CFG(QSERDES_V5_5NM_TX_PARRATE_REC_DETECT_IDLE_EN, 0x00), 972 QMP_PHY_INIT_CFG(QSERDES_V5_5NM_TX_RES_CODE_LANE_OFFSET_TX, 0x11), 973 QMP_PHY_INIT_CFG(QSERDES_V5_5NM_TX_RES_CODE_LANE_OFFSET_RX, 0x11), 974 QMP_PHY_INIT_CFG(QSERDES_V5_5NM_TX_TX_BAND, 0x01), 975}; 976 977static const struct qmp_phy_init_tbl qmp_v6_dp_serdes_tbl[] = { 978 QMP_PHY_INIT_CFG(QSERDES_V6_COM_SVS_MODE_CLK_SEL, 0x15), 979 QMP_PHY_INIT_CFG(QSERDES_V6_COM_SYSCLK_EN_SEL, 0x3b), 980 QMP_PHY_INIT_CFG(QSERDES_V6_COM_SYS_CLK_CTRL, 0x02), 981 QMP_PHY_INIT_CFG(QSERDES_V6_COM_CLK_ENABLE1, 0x0c), 982 QMP_PHY_INIT_CFG(QSERDES_V6_COM_SYSCLK_BUF_ENABLE, 0x06), 983 QMP_PHY_INIT_CFG(QSERDES_V6_COM_CLK_SELECT, 0x30), 984 QMP_PHY_INIT_CFG(QSERDES_V6_COM_PLL_IVCO, 0x0f), 985 QMP_PHY_INIT_CFG(QSERDES_V6_COM_PLL_CCTRL_MODE0, 0x36), 986 QMP_PHY_INIT_CFG(QSERDES_V6_COM_PLL_RCTRL_MODE0, 0x16), 987 QMP_PHY_INIT_CFG(QSERDES_V6_COM_CP_CTRL_MODE0, 0x06), 988 QMP_PHY_INIT_CFG(QSERDES_V6_COM_DIV_FRAC_START1_MODE0, 0x00), 989 QMP_PHY_INIT_CFG(QSERDES_V6_COM_CMN_CONFIG_1, 0x12), 990 QMP_PHY_INIT_CFG(QSERDES_V6_COM_INTEGLOOP_GAIN0_MODE0, 0x3f), 991 QMP_PHY_INIT_CFG(QSERDES_V6_COM_INTEGLOOP_GAIN1_MODE0, 0x00), 992 QMP_PHY_INIT_CFG(QSERDES_V6_COM_VCO_TUNE_MAP, 0x00), 993 QMP_PHY_INIT_CFG(QSERDES_V6_COM_BG_TIMER, 0x0a), 994 QMP_PHY_INIT_CFG(QSERDES_V6_COM_PLL_CORE_CLK_DIV_MODE0, 0x14), 995 QMP_PHY_INIT_CFG(QSERDES_V6_COM_VCO_TUNE_CTRL, 0x00), 996 QMP_PHY_INIT_CFG(QSERDES_V6_COM_PLL_BIAS_EN_CLK_BUFLR_EN, 0x17), 997 QMP_PHY_INIT_CFG(QSERDES_V6_COM_CORE_CLK_EN, 0x0f), 998}; 999 1000static const struct qmp_phy_init_tbl qmp_v6_dp_tx_tbl[] = { 1001 QMP_PHY_INIT_CFG(QSERDES_V6_TX_VMODE_CTRL1, 0x40), 1002 QMP_PHY_INIT_CFG(QSERDES_V6_TX_PRE_STALL_LDO_BOOST_EN, 0x30), 1003 QMP_PHY_INIT_CFG(QSERDES_V6_TX_INTERFACE_SELECT, 0x3b), 1004 QMP_PHY_INIT_CFG(QSERDES_V6_TX_CLKBUF_ENABLE, 0x0f), 1005 QMP_PHY_INIT_CFG(QSERDES_V6_TX_RESET_TSYNC_EN, 0x03), 1006 QMP_PHY_INIT_CFG(QSERDES_V6_TX_TRAN_DRVR_EMP_EN, 0x0f), 1007 QMP_PHY_INIT_CFG(QSERDES_V6_TX_PARRATE_REC_DETECT_IDLE_EN, 0x00), 1008 QMP_PHY_INIT_CFG(QSERDES_V6_TX_TX_INTERFACE_MODE, 0x00), 1009 QMP_PHY_INIT_CFG(QSERDES_V6_TX_RES_CODE_LANE_OFFSET_TX, 0x0c), 1010 QMP_PHY_INIT_CFG(QSERDES_V6_TX_RES_CODE_LANE_OFFSET_RX, 0x0c), 1011 QMP_PHY_INIT_CFG(QSERDES_V6_TX_TX_BAND, 0x4), 1012}; 1013 1014static const struct qmp_phy_init_tbl qmp_v6_dp_serdes_tbl_rbr[] = { 1015 QMP_PHY_INIT_CFG(QSERDES_V6_COM_HSCLK_SEL_1, 0x05), 1016 QMP_PHY_INIT_CFG(QSERDES_V6_COM_DEC_START_MODE0, 0x34), 1017 QMP_PHY_INIT_CFG(QSERDES_V6_COM_DIV_FRAC_START2_MODE0, 0xc0), 1018 QMP_PHY_INIT_CFG(QSERDES_V6_COM_DIV_FRAC_START3_MODE0, 0x0b), 1019 QMP_PHY_INIT_CFG(QSERDES_V6_COM_LOCK_CMP1_MODE0, 0x37), 1020 QMP_PHY_INIT_CFG(QSERDES_V6_COM_LOCK_CMP2_MODE0, 0x04), 1021 QMP_PHY_INIT_CFG(QSERDES_V6_COM_LOCK_CMP_EN, 0x04), 1022 QMP_PHY_INIT_CFG(QSERDES_V6_COM_BIN_VCOCAL_CMP_CODE1_MODE0, 0x71), 1023 QMP_PHY_INIT_CFG(QSERDES_V6_COM_BIN_VCOCAL_CMP_CODE2_MODE0, 0x0c), 1024}; 1025 1026static const struct qmp_phy_init_tbl qmp_v6_dp_serdes_tbl_hbr[] = { 1027 QMP_PHY_INIT_CFG(QSERDES_V6_COM_HSCLK_SEL_1, 0x03), 1028 QMP_PHY_INIT_CFG(QSERDES_V6_COM_DEC_START_MODE0, 0x34), 1029 QMP_PHY_INIT_CFG(QSERDES_V6_COM_DIV_FRAC_START2_MODE0, 0xc0), 1030 QMP_PHY_INIT_CFG(QSERDES_V6_COM_DIV_FRAC_START3_MODE0, 0x0b), 1031 QMP_PHY_INIT_CFG(QSERDES_V6_COM_LOCK_CMP1_MODE0, 0x07), 1032 QMP_PHY_INIT_CFG(QSERDES_V6_COM_LOCK_CMP2_MODE0, 0x07), 1033 QMP_PHY_INIT_CFG(QSERDES_V6_COM_LOCK_CMP_EN, 0x08), 1034 QMP_PHY_INIT_CFG(QSERDES_V6_COM_BIN_VCOCAL_CMP_CODE1_MODE0, 0x71), 1035 QMP_PHY_INIT_CFG(QSERDES_V6_COM_BIN_VCOCAL_CMP_CODE2_MODE0, 0x0c), 1036}; 1037 1038static const struct qmp_phy_init_tbl qmp_v6_dp_serdes_tbl_hbr2[] = { 1039 QMP_PHY_INIT_CFG(QSERDES_V6_COM_HSCLK_SEL_1, 0x01), 1040 QMP_PHY_INIT_CFG(QSERDES_V6_COM_DEC_START_MODE0, 0x46), 1041 QMP_PHY_INIT_CFG(QSERDES_V6_COM_DIV_FRAC_START2_MODE0, 0x00), 1042 QMP_PHY_INIT_CFG(QSERDES_V6_COM_DIV_FRAC_START3_MODE0, 0x05), 1043 QMP_PHY_INIT_CFG(QSERDES_V6_COM_LOCK_CMP1_MODE0, 0x0f), 1044 QMP_PHY_INIT_CFG(QSERDES_V6_COM_LOCK_CMP2_MODE0, 0x0e), 1045 QMP_PHY_INIT_CFG(QSERDES_V6_COM_LOCK_CMP_EN, 0x08), 1046 QMP_PHY_INIT_CFG(QSERDES_V6_COM_BIN_VCOCAL_CMP_CODE1_MODE0, 0x97), 1047 QMP_PHY_INIT_CFG(QSERDES_V6_COM_BIN_VCOCAL_CMP_CODE2_MODE0, 0x10), 1048}; 1049 1050static const struct qmp_phy_init_tbl qmp_v6_dp_serdes_tbl_hbr3[] = { 1051 QMP_PHY_INIT_CFG(QSERDES_V6_COM_HSCLK_SEL_1, 0x00), 1052 QMP_PHY_INIT_CFG(QSERDES_V6_COM_DEC_START_MODE0, 0x34), 1053 QMP_PHY_INIT_CFG(QSERDES_V6_COM_DIV_FRAC_START2_MODE0, 0xc0), 1054 QMP_PHY_INIT_CFG(QSERDES_V6_COM_DIV_FRAC_START3_MODE0, 0x0b), 1055 QMP_PHY_INIT_CFG(QSERDES_V6_COM_LOCK_CMP1_MODE0, 0x17), 1056 QMP_PHY_INIT_CFG(QSERDES_V6_COM_LOCK_CMP2_MODE0, 0x15), 1057 QMP_PHY_INIT_CFG(QSERDES_V6_COM_LOCK_CMP_EN, 0x08), 1058 QMP_PHY_INIT_CFG(QSERDES_V6_COM_BIN_VCOCAL_CMP_CODE1_MODE0, 0x71), 1059 QMP_PHY_INIT_CFG(QSERDES_V6_COM_BIN_VCOCAL_CMP_CODE2_MODE0, 0x0c), 1060}; 1061 1062static const struct qmp_phy_init_tbl sc8280xp_usb43dp_serdes_tbl[] = { 1063 QMP_PHY_INIT_CFG(QSERDES_V5_COM_SSC_EN_CENTER, 0x01), 1064 QMP_PHY_INIT_CFG(QSERDES_V5_COM_SSC_PER1, 0x31), 1065 QMP_PHY_INIT_CFG(QSERDES_V5_COM_SSC_PER2, 0x01), 1066 QMP_PHY_INIT_CFG(QSERDES_V5_COM_SSC_STEP_SIZE1_MODE0, 0xfd), 1067 QMP_PHY_INIT_CFG(QSERDES_V5_COM_SSC_STEP_SIZE2_MODE0, 0x0d), 1068 QMP_PHY_INIT_CFG(QSERDES_V5_COM_SSC_STEP_SIZE1_MODE1, 0xfd), 1069 QMP_PHY_INIT_CFG(QSERDES_V5_COM_SSC_STEP_SIZE2_MODE1, 0x0d), 1070 QMP_PHY_INIT_CFG(QSERDES_V5_COM_SYSCLK_BUF_ENABLE, 0x0a), 1071 QMP_PHY_INIT_CFG(QSERDES_V5_COM_CP_CTRL_MODE0, 0x02), 1072 QMP_PHY_INIT_CFG(QSERDES_V5_COM_CP_CTRL_MODE1, 0x02), 1073 QMP_PHY_INIT_CFG(QSERDES_V5_COM_PLL_RCTRL_MODE0, 0x16), 1074 QMP_PHY_INIT_CFG(QSERDES_V5_COM_PLL_RCTRL_MODE1, 0x16), 1075 QMP_PHY_INIT_CFG(QSERDES_V5_COM_PLL_CCTRL_MODE0, 0x36), 1076 QMP_PHY_INIT_CFG(QSERDES_V5_COM_PLL_CCTRL_MODE1, 0x36), 1077 QMP_PHY_INIT_CFG(QSERDES_V5_COM_SYSCLK_EN_SEL, 0x1a), 1078 QMP_PHY_INIT_CFG(QSERDES_V5_COM_LOCK_CMP_EN, 0x04), 1079 QMP_PHY_INIT_CFG(QSERDES_V5_COM_LOCK_CMP1_MODE0, 0x14), 1080 QMP_PHY_INIT_CFG(QSERDES_V5_COM_LOCK_CMP2_MODE0, 0x34), 1081 QMP_PHY_INIT_CFG(QSERDES_V5_COM_LOCK_CMP1_MODE1, 0x34), 1082 QMP_PHY_INIT_CFG(QSERDES_V5_COM_LOCK_CMP2_MODE1, 0x82), 1083 QMP_PHY_INIT_CFG(QSERDES_V5_COM_DEC_START_MODE0, 0x04), 1084 QMP_PHY_INIT_CFG(QSERDES_V5_COM_DEC_START_MSB_MODE0, 0x01), 1085 QMP_PHY_INIT_CFG(QSERDES_V5_COM_DEC_START_MODE1, 0x04), 1086 QMP_PHY_INIT_CFG(QSERDES_V5_COM_DEC_START_MSB_MODE1, 0x01), 1087 QMP_PHY_INIT_CFG(QSERDES_V5_COM_DIV_FRAC_START1_MODE0, 0x55), 1088 QMP_PHY_INIT_CFG(QSERDES_V5_COM_DIV_FRAC_START2_MODE0, 0xd5), 1089 QMP_PHY_INIT_CFG(QSERDES_V5_COM_DIV_FRAC_START3_MODE0, 0x05), 1090 QMP_PHY_INIT_CFG(QSERDES_V5_COM_DIV_FRAC_START1_MODE1, 0x55), 1091 QMP_PHY_INIT_CFG(QSERDES_V5_COM_DIV_FRAC_START2_MODE1, 0xd5), 1092 QMP_PHY_INIT_CFG(QSERDES_V5_COM_DIV_FRAC_START3_MODE1, 0x05), 1093 QMP_PHY_INIT_CFG(QSERDES_V5_COM_VCO_TUNE_MAP, 0x02), 1094 QMP_PHY_INIT_CFG(QSERDES_V5_COM_VCO_TUNE1_MODE0, 0xd4), 1095 QMP_PHY_INIT_CFG(QSERDES_V5_COM_VCO_TUNE2_MODE0, 0x00), 1096 QMP_PHY_INIT_CFG(QSERDES_V5_COM_VCO_TUNE1_MODE1, 0xd4), 1097 QMP_PHY_INIT_CFG(QSERDES_V5_COM_VCO_TUNE2_MODE1, 0x00), 1098 QMP_PHY_INIT_CFG(QSERDES_V5_COM_HSCLK_SEL, 0x13), 1099 QMP_PHY_INIT_CFG(QSERDES_V5_COM_HSCLK_HS_SWITCH_SEL, 0x00), 1100 QMP_PHY_INIT_CFG(QSERDES_V5_COM_CORECLK_DIV_MODE0, 0x0a), 1101 QMP_PHY_INIT_CFG(QSERDES_V5_COM_CORECLK_DIV_MODE1, 0x04), 1102 QMP_PHY_INIT_CFG(QSERDES_V5_COM_CORE_CLK_EN, 0x60), 1103 QMP_PHY_INIT_CFG(QSERDES_V5_COM_CMN_CONFIG, 0x76), 1104 QMP_PHY_INIT_CFG(QSERDES_V5_COM_PLL_IVCO, 0xff), 1105 QMP_PHY_INIT_CFG(QSERDES_V5_COM_INTEGLOOP_GAIN0_MODE0, 0x20), 1106 QMP_PHY_INIT_CFG(QSERDES_V5_COM_INTEGLOOP_GAIN0_MODE1, 0x20), 1107 QMP_PHY_INIT_CFG(QSERDES_V5_COM_VCO_TUNE_INITVAL2, 0x00), 1108 QMP_PHY_INIT_CFG(QSERDES_V5_COM_VCO_TUNE_MAXVAL2, 0x01), 1109 QMP_PHY_INIT_CFG(QSERDES_V5_COM_SVS_MODE_CLK_SEL, 0x0a), 1110}; 1111 1112static const struct qmp_phy_init_tbl sc8280xp_usb43dp_tx_tbl[] = { 1113 QMP_PHY_INIT_CFG(QSERDES_V5_5NM_TX_LANE_MODE_1, 0x05), 1114 QMP_PHY_INIT_CFG(QSERDES_V5_5NM_TX_LANE_MODE_2, 0xc2), 1115 QMP_PHY_INIT_CFG(QSERDES_V5_5NM_TX_LANE_MODE_3, 0x10), 1116 QMP_PHY_INIT_CFG(QSERDES_V5_5NM_TX_RES_CODE_LANE_OFFSET_TX, 0x1f), 1117 QMP_PHY_INIT_CFG(QSERDES_V5_5NM_TX_RES_CODE_LANE_OFFSET_RX, 0x0a), 1118}; 1119 1120static const struct qmp_phy_init_tbl sc8280xp_usb43dp_rx_tbl[] = { 1121 QMP_PHY_INIT_CFG(QSERDES_V5_5NM_RX_SIGDET_CNTRL, 0x04), 1122 QMP_PHY_INIT_CFG(QSERDES_V5_5NM_RX_SIGDET_DEGLITCH_CNTRL, 0x0e), 1123 QMP_PHY_INIT_CFG(QSERDES_V5_5NM_RX_SIGDET_ENABLES, 0x00), 1124 QMP_PHY_INIT_CFG(QSERDES_V5_5NM_RX_RX_MODE_RATE_0_1_B0, 0xd2), 1125 QMP_PHY_INIT_CFG(QSERDES_V5_5NM_RX_RX_MODE_RATE_0_1_B1, 0xd2), 1126 QMP_PHY_INIT_CFG(QSERDES_V5_5NM_RX_RX_MODE_RATE_0_1_B2, 0xdb), 1127 QMP_PHY_INIT_CFG(QSERDES_V5_5NM_RX_RX_MODE_RATE_0_1_B3, 0x21), 1128 QMP_PHY_INIT_CFG(QSERDES_V5_5NM_RX_RX_MODE_RATE_0_1_B4, 0x3f), 1129 QMP_PHY_INIT_CFG(QSERDES_V5_5NM_RX_RX_MODE_RATE_0_1_B5, 0x80), 1130 QMP_PHY_INIT_CFG(QSERDES_V5_5NM_RX_RX_MODE_RATE_0_1_B6, 0x45), 1131 QMP_PHY_INIT_CFG(QSERDES_V5_5NM_RX_RX_MODE_RATE_0_1_B7, 0x00), 1132 QMP_PHY_INIT_CFG(QSERDES_V5_5NM_RX_RX_MODE_RATE2_B0, 0x6b), 1133 QMP_PHY_INIT_CFG(QSERDES_V5_5NM_RX_RX_MODE_RATE2_B1, 0x63), 1134 QMP_PHY_INIT_CFG(QSERDES_V5_5NM_RX_RX_MODE_RATE2_B2, 0xb6), 1135 QMP_PHY_INIT_CFG(QSERDES_V5_5NM_RX_RX_MODE_RATE2_B3, 0x23), 1136 QMP_PHY_INIT_CFG(QSERDES_V5_5NM_RX_RX_MODE_RATE2_B4, 0x35), 1137 QMP_PHY_INIT_CFG(QSERDES_V5_5NM_RX_RX_MODE_RATE2_B5, 0x30), 1138 QMP_PHY_INIT_CFG(QSERDES_V5_5NM_RX_RX_MODE_RATE2_B6, 0x8e), 1139 QMP_PHY_INIT_CFG(QSERDES_V5_5NM_RX_RX_MODE_RATE2_B7, 0x00), 1140 QMP_PHY_INIT_CFG(QSERDES_V5_5NM_RX_RX_IVCM_CAL_CODE_OVERRIDE, 0x00), 1141 QMP_PHY_INIT_CFG(QSERDES_V5_5NM_RX_RX_IVCM_CAL_CTRL2, 0x80), 1142 QMP_PHY_INIT_CFG(QSERDES_V5_5NM_RX_RX_SUMMER_CAL_SPD_MODE, 0x1b), 1143 QMP_PHY_INIT_CFG(QSERDES_V5_5NM_RX_DFE_CTLE_POST_CAL_OFFSET, 0x38), 1144 QMP_PHY_INIT_CFG(QSERDES_V5_5NM_RX_UCDR_PI_CONTROLS, 0x15), 1145 QMP_PHY_INIT_CFG(QSERDES_V5_5NM_RX_UCDR_SB2_GAIN2_RATE2, 0x0a), 1146 QMP_PHY_INIT_CFG(QSERDES_V5_5NM_RX_RX_IVCM_POSTCAL_OFFSET, 0x7c), 1147 QMP_PHY_INIT_CFG(QSERDES_V5_5NM_RX_VGA_CAL_CNTRL1, 0x00), 1148 QMP_PHY_INIT_CFG(QSERDES_V5_5NM_RX_VGA_CAL_MAN_VAL, 0x0d), 1149 QMP_PHY_INIT_CFG(QSERDES_V5_5NM_RX_DFE_DAC_ENABLE1, 0x00), 1150 QMP_PHY_INIT_CFG(QSERDES_V5_5NM_RX_DFE_3, 0x45), 1151 QMP_PHY_INIT_CFG(QSERDES_V5_5NM_RX_GM_CAL, 0x09), 1152 QMP_PHY_INIT_CFG(QSERDES_V5_5NM_RX_UCDR_FO_GAIN_RATE2, 0x09), 1153 QMP_PHY_INIT_CFG(QSERDES_V5_5NM_RX_UCDR_SO_GAIN_RATE2, 0x05), 1154 QMP_PHY_INIT_CFG(QSERDES_V5_5NM_RX_Q_PI_INTRINSIC_BIAS_RATE32, 0x3f), 1155}; 1156 1157static const struct qmp_phy_init_tbl sc8280xp_usb43dp_pcs_tbl[] = { 1158 QMP_PHY_INIT_CFG(QPHY_V5_PCS_RCVR_DTCT_DLY_P1U2_L, 0xe7), 1159 QMP_PHY_INIT_CFG(QPHY_V5_PCS_RCVR_DTCT_DLY_P1U2_H, 0x03), 1160 QMP_PHY_INIT_CFG(QPHY_V5_PCS_LOCK_DETECT_CONFIG1, 0xd0), 1161 QMP_PHY_INIT_CFG(QPHY_V5_PCS_LOCK_DETECT_CONFIG2, 0x07), 1162 QMP_PHY_INIT_CFG(QPHY_V5_PCS_LOCK_DETECT_CONFIG3, 0x20), 1163 QMP_PHY_INIT_CFG(QPHY_V5_PCS_LOCK_DETECT_CONFIG6, 0x13), 1164 QMP_PHY_INIT_CFG(QPHY_V5_PCS_REFGEN_REQ_CONFIG1, 0x21), 1165 QMP_PHY_INIT_CFG(QPHY_V5_PCS_RX_SIGDET_LVL, 0xaa), 1166 QMP_PHY_INIT_CFG(QPHY_V5_PCS_RX_CONFIG, 0x0a), 1167 QMP_PHY_INIT_CFG(QPHY_V5_PCS_ALIGN_DETECT_CONFIG1, 0x88), 1168 QMP_PHY_INIT_CFG(QPHY_V5_PCS_ALIGN_DETECT_CONFIG2, 0x13), 1169 QMP_PHY_INIT_CFG(QPHY_V5_PCS_PCS_TX_RX_CONFIG, 0x0c), 1170 QMP_PHY_INIT_CFG(QPHY_V5_PCS_EQ_CONFIG1, 0x4b), 1171 QMP_PHY_INIT_CFG(QPHY_V5_PCS_EQ_CONFIG5, 0x10), 1172 QMP_PHY_INIT_CFG(QPHY_V5_PCS_USB3_LFPS_DET_HIGH_COUNT_VAL, 0xf8), 1173 QMP_PHY_INIT_CFG(QPHY_V5_PCS_USB3_RXEQTRAINING_DFE_TIME_S2, 0x07), 1174}; 1175 1176static const struct qmp_phy_init_tbl x1e80100_usb43dp_serdes_tbl[] = { 1177 QMP_PHY_INIT_CFG(QSERDES_V6_COM_SSC_EN_CENTER, 0x01), 1178 QMP_PHY_INIT_CFG(QSERDES_V6_COM_SSC_PER1, 0x62), 1179 QMP_PHY_INIT_CFG(QSERDES_V6_COM_SSC_PER2, 0x02), 1180 QMP_PHY_INIT_CFG(QSERDES_V6_COM_SSC_STEP_SIZE1_MODE0, 0xc2), 1181 QMP_PHY_INIT_CFG(QSERDES_V6_COM_SSC_STEP_SIZE2_MODE0, 0x03), 1182 QMP_PHY_INIT_CFG(QSERDES_V6_COM_SSC_STEP_SIZE1_MODE1, 0xc2), 1183 QMP_PHY_INIT_CFG(QSERDES_V6_COM_SSC_STEP_SIZE2_MODE1, 0x03), 1184 QMP_PHY_INIT_CFG(QSERDES_V6_COM_SYSCLK_BUF_ENABLE, 0x0a), 1185 QMP_PHY_INIT_CFG(QSERDES_V6_COM_CP_CTRL_MODE0, 0x02), 1186 QMP_PHY_INIT_CFG(QSERDES_V6_COM_CP_CTRL_MODE1, 0x02), 1187 QMP_PHY_INIT_CFG(QSERDES_V6_COM_PLL_RCTRL_MODE0, 0x16), 1188 QMP_PHY_INIT_CFG(QSERDES_V6_COM_PLL_RCTRL_MODE1, 0x16), 1189 QMP_PHY_INIT_CFG(QSERDES_V6_COM_PLL_CCTRL_MODE0, 0x36), 1190 QMP_PHY_INIT_CFG(QSERDES_V6_COM_PLL_CCTRL_MODE1, 0x36), 1191 QMP_PHY_INIT_CFG(QSERDES_V6_COM_SYSCLK_EN_SEL, 0x1a), 1192 QMP_PHY_INIT_CFG(QSERDES_V6_COM_LOCK_CMP_EN, 0x04), 1193 QMP_PHY_INIT_CFG(QSERDES_V6_COM_LOCK_CMP_CFG, 0x04), 1194 QMP_PHY_INIT_CFG(QSERDES_V6_COM_LOCK_CMP1_MODE0, 0x08), 1195 QMP_PHY_INIT_CFG(QSERDES_V6_COM_LOCK_CMP2_MODE0, 0x1a), 1196 QMP_PHY_INIT_CFG(QSERDES_V6_COM_LOCK_CMP1_MODE1, 0x16), 1197 QMP_PHY_INIT_CFG(QSERDES_V6_COM_LOCK_CMP2_MODE1, 0x41), 1198 QMP_PHY_INIT_CFG(QSERDES_V6_COM_DEC_START_MODE0, 0x82), 1199 QMP_PHY_INIT_CFG(QSERDES_V6_COM_DEC_START_MSB_MODE0, 0x00), 1200 QMP_PHY_INIT_CFG(QSERDES_V6_COM_DEC_START_MODE1, 0x82), 1201 QMP_PHY_INIT_CFG(QSERDES_V6_COM_DEC_START_MSB_MODE1, 0x00), 1202 QMP_PHY_INIT_CFG(QSERDES_V6_COM_DIV_FRAC_START1_MODE0, 0x55), 1203 QMP_PHY_INIT_CFG(QSERDES_V6_COM_DIV_FRAC_START2_MODE0, 0x55), 1204 QMP_PHY_INIT_CFG(QSERDES_V6_COM_DIV_FRAC_START3_MODE0, 0x03), 1205 QMP_PHY_INIT_CFG(QSERDES_V6_COM_DIV_FRAC_START1_MODE1, 0x55), 1206 QMP_PHY_INIT_CFG(QSERDES_V6_COM_DIV_FRAC_START2_MODE1, 0x55), 1207 QMP_PHY_INIT_CFG(QSERDES_V6_COM_DIV_FRAC_START3_MODE1, 0x03), 1208 QMP_PHY_INIT_CFG(QSERDES_V6_COM_VCO_TUNE_MAP, 0x14), 1209 QMP_PHY_INIT_CFG(QSERDES_V6_COM_VCO_TUNE1_MODE0, 0xba), 1210 QMP_PHY_INIT_CFG(QSERDES_V6_COM_VCO_TUNE2_MODE0, 0x00), 1211 QMP_PHY_INIT_CFG(QSERDES_V6_COM_VCO_TUNE1_MODE1, 0xba), 1212 QMP_PHY_INIT_CFG(QSERDES_V6_COM_VCO_TUNE2_MODE1, 0x00), 1213 QMP_PHY_INIT_CFG(QSERDES_V6_COM_HSCLK_SEL_1, 0x13), 1214 QMP_PHY_INIT_CFG(QSERDES_V6_COM_HSCLK_HS_SWITCH_SEL_1, 0x00), 1215 QMP_PHY_INIT_CFG(QSERDES_V6_COM_PLL_CORE_CLK_DIV_MODE0, 0x0a), 1216 QMP_PHY_INIT_CFG(QSERDES_V6_COM_CORECLK_DIV_MODE1, 0x04), 1217 QMP_PHY_INIT_CFG(QSERDES_V6_COM_CORE_CLK_EN, 0xa0), 1218 QMP_PHY_INIT_CFG(QSERDES_V6_COM_CMN_CONFIG_1, 0x76), 1219 QMP_PHY_INIT_CFG(QSERDES_V6_COM_PLL_IVCO, 0x0f), 1220 QMP_PHY_INIT_CFG(QSERDES_V6_COM_PLL_IVCO_MODE1, 0x0f), 1221 QMP_PHY_INIT_CFG(QSERDES_V6_COM_INTEGLOOP_GAIN0_MODE0, 0x20), 1222 QMP_PHY_INIT_CFG(QSERDES_V6_COM_INTEGLOOP_GAIN0_MODE1, 0x20), 1223 QMP_PHY_INIT_CFG(QSERDES_V6_COM_VCO_TUNE_INITVAL2, 0x00), 1224 QMP_PHY_INIT_CFG(QSERDES_V6_COM_VCO_TUNE_MAXVAL2, 0x01), 1225 QMP_PHY_INIT_CFG(QSERDES_V6_COM_SVS_MODE_CLK_SEL, 0x0a), 1226 QMP_PHY_INIT_CFG(QSERDES_V6_COM_BG_TIMER, 0x0a), 1227}; 1228 1229static const struct qmp_phy_init_tbl x1e80100_usb43dp_tx_tbl[] = { 1230 QMP_PHY_INIT_CFG(QSERDES_V6_N4_TX_LANE_MODE_1, 0x05), 1231 QMP_PHY_INIT_CFG(QSERDES_V6_N4_TX_LANE_MODE_2, 0x50), 1232 QMP_PHY_INIT_CFG(QSERDES_V6_N4_TX_LANE_MODE_3, 0x50), 1233 QMP_PHY_INIT_CFG(QSERDES_V6_N4_TX_RES_CODE_LANE_OFFSET_TX, 0x1f), 1234 QMP_PHY_INIT_CFG(QSERDES_V6_N4_TX_RES_CODE_LANE_OFFSET_RX, 0x0a), 1235}; 1236 1237static const struct qmp_phy_init_tbl x1e80100_usb43dp_rx_tbl[] = { 1238 QMP_PHY_INIT_CFG(QSERDES_V6_N4_RX_SIGDET_CNTRL, 0x04), 1239 QMP_PHY_INIT_CFG(QSERDES_V6_N4_RX_SIGDET_DEGLITCH_CNTRL, 0x0e), 1240 QMP_PHY_INIT_CFG(QSERDES_V6_N4_RX_SIGDET_ENABLES, 0x00), 1241 QMP_PHY_INIT_CFG(QSERDES_V6_N4_RX_MODE_RATE_0_1_B0, 0xc3), 1242 QMP_PHY_INIT_CFG(QSERDES_V6_N4_RX_MODE_RATE_0_1_B1, 0xc3), 1243 QMP_PHY_INIT_CFG(QSERDES_V6_N4_RX_MODE_RATE_0_1_B2, 0xd8), 1244 QMP_PHY_INIT_CFG(QSERDES_V6_N4_RX_MODE_RATE_0_1_B3, 0x9e), 1245 QMP_PHY_INIT_CFG(QSERDES_V6_N4_RX_MODE_RATE_0_1_B4, 0x36), 1246 QMP_PHY_INIT_CFG(QSERDES_V6_N4_RX_MODE_RATE_0_1_B5, 0xb6), 1247 QMP_PHY_INIT_CFG(QSERDES_V6_N4_RX_MODE_RATE_0_1_B6, 0x64), 1248 QMP_PHY_INIT_CFG(QSERDES_V6_N4_RX_MODE_RATE2_B0, 0xd6), 1249 QMP_PHY_INIT_CFG(QSERDES_V6_N4_RX_MODE_RATE2_B1, 0xee), 1250 QMP_PHY_INIT_CFG(QSERDES_V6_N4_RX_MODE_RATE2_B2, 0x18), 1251 QMP_PHY_INIT_CFG(QSERDES_V6_N4_RX_MODE_RATE2_B3, 0x9a), 1252 QMP_PHY_INIT_CFG(QSERDES_V6_N4_RX_MODE_RATE2_B4, 0x04), 1253 QMP_PHY_INIT_CFG(QSERDES_V6_N4_RX_MODE_RATE2_B5, 0x36), 1254 QMP_PHY_INIT_CFG(QSERDES_V6_N4_RX_MODE_RATE2_B6, 0xe3), 1255 QMP_PHY_INIT_CFG(QSERDES_V6_N4_RX_IVCM_CAL_CODE_OVERRIDE, 0x00), 1256 QMP_PHY_INIT_CFG(QSERDES_V6_N4_RX_RX_IVCM_CAL_CTRL2, 0x80), 1257 QMP_PHY_INIT_CFG(QSERDES_V6_N4_RX_RX_SUMMER_CAL_SPD_MODE, 0x2f), 1258 QMP_PHY_INIT_CFG(QSERDES_V6_N4_RX_DFE_CTLE_POST_CAL_OFFSET, 0x08), 1259 QMP_PHY_INIT_CFG(QSERDES_V6_N4_RX_UCDR_PI_CONTROLS, 0x15), 1260 QMP_PHY_INIT_CFG(QSERDES_V6_N4_RX_UCDR_PI_CTRL1, 0xd0), 1261 QMP_PHY_INIT_CFG(QSERDES_V6_N4_RX_UCDR_PI_CTRL2, 0x48), 1262 QMP_PHY_INIT_CFG(QSERDES_V6_N4_RX_UCDR_SB2_GAIN2_RATE2, 0x0a), 1263 QMP_PHY_INIT_CFG(QSERDES_V6_N4_RX_RX_IVCM_POSTCAL_OFFSET, 0x7c), 1264 QMP_PHY_INIT_CFG(QSERDES_V6_N4_RX_VGA_CAL_CNTRL1, 0x00), 1265 QMP_PHY_INIT_CFG(QSERDES_V6_N4_RX_VGA_CAL_MAN_VAL, 0x04), 1266 QMP_PHY_INIT_CFG(QSERDES_V6_N4_RX_DFE_DAC_ENABLE1, 0x88), 1267 QMP_PHY_INIT_CFG(QSERDES_V6_N4_RX_DFE_3, 0x45), 1268 QMP_PHY_INIT_CFG(QSERDES_V6_N4_RX_GM_CAL, 0x0d), 1269 QMP_PHY_INIT_CFG(QSERDES_V6_N4_RX_UCDR_FO_GAIN_RATE2, 0x09), 1270 QMP_PHY_INIT_CFG(QSERDES_V6_N4_RX_UCDR_SO_GAIN_RATE2, 0x05), 1271 QMP_PHY_INIT_CFG(QSERDES_V6_N4_RX_Q_PI_INTRINSIC_BIAS_RATE32, 0x2f), 1272 QMP_PHY_INIT_CFG(QSERDES_V6_N4_RX_RX_BKUP_CTRL1, 0x14), 1273}; 1274 1275static const struct qmp_phy_init_tbl x1e80100_usb43dp_pcs_tbl[] = { 1276 QMP_PHY_INIT_CFG(QPHY_V6_PCS_RCVR_DTCT_DLY_P1U2_L, 0xe7), 1277 QMP_PHY_INIT_CFG(QPHY_V6_PCS_RCVR_DTCT_DLY_P1U2_H, 0x03), 1278 QMP_PHY_INIT_CFG(QPHY_V6_PCS_LOCK_DETECT_CONFIG1, 0xc4), 1279 QMP_PHY_INIT_CFG(QPHY_V6_PCS_LOCK_DETECT_CONFIG2, 0x89), 1280 QMP_PHY_INIT_CFG(QPHY_V6_PCS_LOCK_DETECT_CONFIG3, 0x20), 1281 QMP_PHY_INIT_CFG(QPHY_V6_PCS_LOCK_DETECT_CONFIG6, 0x13), 1282 QMP_PHY_INIT_CFG(QPHY_V6_PCS_REFGEN_REQ_CONFIG1, 0x21), 1283 QMP_PHY_INIT_CFG(QPHY_V6_PCS_RX_SIGDET_LVL, 0x55), 1284 QMP_PHY_INIT_CFG(QPHY_V6_PCS_CDR_RESET_TIME, 0x0a), 1285 QMP_PHY_INIT_CFG(QPHY_V6_PCS_ALIGN_DETECT_CONFIG1, 0xd4), 1286 QMP_PHY_INIT_CFG(QPHY_V6_PCS_ALIGN_DETECT_CONFIG2, 0x30), 1287 QMP_PHY_INIT_CFG(QPHY_V6_PCS_PCS_TX_RX_CONFIG, 0x0c), 1288 QMP_PHY_INIT_CFG(QPHY_V6_PCS_EQ_CONFIG1, 0x4b), 1289 QMP_PHY_INIT_CFG(QPHY_V6_PCS_EQ_CONFIG5, 0x10), 1290}; 1291 1292static const struct qmp_phy_init_tbl x1e80100_usb43dp_pcs_usb_tbl[] = { 1293 QMP_PHY_INIT_CFG(QPHY_V6_PCS_USB3_LFPS_DET_HIGH_COUNT_VAL, 0xf8), 1294 QMP_PHY_INIT_CFG(QPHY_V6_PCS_USB3_RXEQTRAINING_DFE_TIME_S2, 0x07), 1295}; 1296 1297/* list of regulators */ 1298struct qmp_regulator_data { 1299 const char *name; 1300 unsigned int enable_load; 1301}; 1302 1303static struct qmp_regulator_data qmp_phy_vreg_l[] = { 1304 { .name = "vdda-phy", .enable_load = 21800 }, 1305 { .name = "vdda-pll", .enable_load = 36000 }, 1306}; 1307 1308static const u8 qmp_dp_v3_pre_emphasis_hbr3_hbr2[4][4] = { 1309 { 0x00, 0x0c, 0x15, 0x1a }, 1310 { 0x02, 0x0e, 0x16, 0xff }, 1311 { 0x02, 0x11, 0xff, 0xff }, 1312 { 0x04, 0xff, 0xff, 0xff } 1313}; 1314 1315static const u8 qmp_dp_v3_voltage_swing_hbr3_hbr2[4][4] = { 1316 { 0x02, 0x12, 0x16, 0x1a }, 1317 { 0x09, 0x19, 0x1f, 0xff }, 1318 { 0x10, 0x1f, 0xff, 0xff }, 1319 { 0x1f, 0xff, 0xff, 0xff } 1320}; 1321 1322static const u8 qmp_dp_v3_pre_emphasis_hbr_rbr[4][4] = { 1323 { 0x00, 0x0c, 0x14, 0x19 }, 1324 { 0x00, 0x0b, 0x12, 0xff }, 1325 { 0x00, 0x0b, 0xff, 0xff }, 1326 { 0x04, 0xff, 0xff, 0xff } 1327}; 1328 1329static const u8 qmp_dp_v3_voltage_swing_hbr_rbr[4][4] = { 1330 { 0x08, 0x0f, 0x16, 0x1f }, 1331 { 0x11, 0x1e, 0x1f, 0xff }, 1332 { 0x19, 0x1f, 0xff, 0xff }, 1333 { 0x1f, 0xff, 0xff, 0xff } 1334}; 1335 1336static const u8 qmp_dp_v4_pre_emphasis_hbr3_hbr2[4][4] = { 1337 { 0x00, 0x0c, 0x15, 0x1b }, 1338 { 0x02, 0x0e, 0x16, 0xff }, 1339 { 0x02, 0x11, 0xff, 0xff }, 1340 { 0x04, 0xff, 0xff, 0xff } 1341}; 1342 1343static const u8 qmp_dp_v4_pre_emphasis_hbr_rbr[4][4] = { 1344 { 0x00, 0x0d, 0x14, 0x1a }, 1345 { 0x00, 0x0e, 0x15, 0xff }, 1346 { 0x00, 0x0d, 0xff, 0xff }, 1347 { 0x03, 0xff, 0xff, 0xff } 1348}; 1349 1350static const u8 qmp_dp_v4_voltage_swing_hbr_rbr[4][4] = { 1351 { 0x08, 0x0f, 0x16, 0x1f }, 1352 { 0x11, 0x1e, 0x1f, 0xff }, 1353 { 0x16, 0x1f, 0xff, 0xff }, 1354 { 0x1f, 0xff, 0xff, 0xff } 1355}; 1356 1357static const u8 qmp_dp_v5_pre_emphasis_hbr3_hbr2[4][4] = { 1358 { 0x20, 0x2c, 0x35, 0x3b }, 1359 { 0x22, 0x2e, 0x36, 0xff }, 1360 { 0x22, 0x31, 0xff, 0xff }, 1361 { 0x24, 0xff, 0xff, 0xff } 1362}; 1363 1364static const u8 qmp_dp_v5_voltage_swing_hbr3_hbr2[4][4] = { 1365 { 0x22, 0x32, 0x36, 0x3a }, 1366 { 0x29, 0x39, 0x3f, 0xff }, 1367 { 0x30, 0x3f, 0xff, 0xff }, 1368 { 0x3f, 0xff, 0xff, 0xff } 1369}; 1370 1371static const u8 qmp_dp_v5_pre_emphasis_hbr_rbr[4][4] = { 1372 { 0x20, 0x2d, 0x34, 0x3a }, 1373 { 0x20, 0x2e, 0x35, 0xff }, 1374 { 0x20, 0x2e, 0xff, 0xff }, 1375 { 0x24, 0xff, 0xff, 0xff } 1376}; 1377 1378static const u8 qmp_dp_v5_voltage_swing_hbr_rbr[4][4] = { 1379 { 0x28, 0x2f, 0x36, 0x3f }, 1380 { 0x31, 0x3e, 0x3f, 0xff }, 1381 { 0x36, 0x3f, 0xff, 0xff }, 1382 { 0x3f, 0xff, 0xff, 0xff } 1383}; 1384 1385static const u8 qmp_dp_v6_pre_emphasis_hbr_rbr[4][4] = { 1386 { 0x20, 0x2d, 0x34, 0x3a }, 1387 { 0x20, 0x2e, 0x35, 0xff }, 1388 { 0x20, 0x2e, 0xff, 0xff }, 1389 { 0x22, 0xff, 0xff, 0xff } 1390}; 1391 1392struct qmp_combo; 1393 1394struct qmp_combo_offsets { 1395 u16 com; 1396 u16 txa; 1397 u16 rxa; 1398 u16 txb; 1399 u16 rxb; 1400 u16 usb3_serdes; 1401 u16 usb3_pcs_misc; 1402 u16 usb3_pcs; 1403 u16 usb3_pcs_usb; 1404 u16 dp_serdes; 1405 u16 dp_txa; 1406 u16 dp_txb; 1407 u16 dp_dp_phy; 1408}; 1409 1410struct qmp_phy_cfg { 1411 const struct qmp_combo_offsets *offsets; 1412 1413 /* Init sequence for PHY blocks - serdes, tx, rx, pcs */ 1414 const struct qmp_phy_init_tbl *serdes_tbl; 1415 int serdes_tbl_num; 1416 const struct qmp_phy_init_tbl *tx_tbl; 1417 int tx_tbl_num; 1418 const struct qmp_phy_init_tbl *rx_tbl; 1419 int rx_tbl_num; 1420 const struct qmp_phy_init_tbl *pcs_tbl; 1421 int pcs_tbl_num; 1422 const struct qmp_phy_init_tbl *pcs_usb_tbl; 1423 int pcs_usb_tbl_num; 1424 1425 const struct qmp_phy_init_tbl *dp_serdes_tbl; 1426 int dp_serdes_tbl_num; 1427 const struct qmp_phy_init_tbl *dp_tx_tbl; 1428 int dp_tx_tbl_num; 1429 1430 /* Init sequence for DP PHY block link rates */ 1431 const struct qmp_phy_init_tbl *serdes_tbl_rbr; 1432 int serdes_tbl_rbr_num; 1433 const struct qmp_phy_init_tbl *serdes_tbl_hbr; 1434 int serdes_tbl_hbr_num; 1435 const struct qmp_phy_init_tbl *serdes_tbl_hbr2; 1436 int serdes_tbl_hbr2_num; 1437 const struct qmp_phy_init_tbl *serdes_tbl_hbr3; 1438 int serdes_tbl_hbr3_num; 1439 1440 /* DP PHY swing and pre_emphasis tables */ 1441 const u8 (*swing_hbr_rbr)[4][4]; 1442 const u8 (*swing_hbr3_hbr2)[4][4]; 1443 const u8 (*pre_emphasis_hbr_rbr)[4][4]; 1444 const u8 (*pre_emphasis_hbr3_hbr2)[4][4]; 1445 1446 /* DP PHY callbacks */ 1447 int (*configure_dp_phy)(struct qmp_combo *qmp); 1448 void (*configure_dp_tx)(struct qmp_combo *qmp); 1449 int (*calibrate_dp_phy)(struct qmp_combo *qmp); 1450 void (*dp_aux_init)(struct qmp_combo *qmp); 1451 1452 /* resets to be requested */ 1453 const char * const *reset_list; 1454 int num_resets; 1455 /* regulators to be requested */ 1456 const struct qmp_regulator_data *vreg_list; 1457 int num_vregs; 1458 1459 /* array of registers with different offsets */ 1460 const unsigned int *regs; 1461 1462 /* true, if PHY needs delay after POWER_DOWN */ 1463 bool has_pwrdn_delay; 1464 1465 /* Offset from PCS to PCS_USB region */ 1466 unsigned int pcs_usb_offset; 1467 1468}; 1469 1470struct qmp_combo { 1471 struct device *dev; 1472 1473 const struct qmp_phy_cfg *cfg; 1474 1475 void __iomem *com; 1476 1477 void __iomem *serdes; 1478 void __iomem *tx; 1479 void __iomem *rx; 1480 void __iomem *pcs; 1481 void __iomem *tx2; 1482 void __iomem *rx2; 1483 void __iomem *pcs_misc; 1484 void __iomem *pcs_usb; 1485 1486 void __iomem *dp_serdes; 1487 void __iomem *dp_tx; 1488 void __iomem *dp_tx2; 1489 void __iomem *dp_dp_phy; 1490 1491 struct clk *pipe_clk; 1492 struct clk_bulk_data *clks; 1493 int num_clks; 1494 struct reset_control_bulk_data *resets; 1495 struct regulator_bulk_data *vregs; 1496 1497 struct mutex phy_mutex; 1498 int init_count; 1499 1500 struct phy *usb_phy; 1501 enum phy_mode mode; 1502 unsigned int usb_init_count; 1503 1504 struct phy *dp_phy; 1505 unsigned int dp_aux_cfg; 1506 struct phy_configure_opts_dp dp_opts; 1507 unsigned int dp_init_count; 1508 1509 struct clk_fixed_rate pipe_clk_fixed; 1510 struct clk_hw dp_link_hw; 1511 struct clk_hw dp_pixel_hw; 1512 1513 struct typec_switch_dev *sw; 1514 enum typec_orientation orientation; 1515}; 1516 1517static void qmp_v3_dp_aux_init(struct qmp_combo *qmp); 1518static void qmp_v3_configure_dp_tx(struct qmp_combo *qmp); 1519static int qmp_v3_configure_dp_phy(struct qmp_combo *qmp); 1520static int qmp_v3_calibrate_dp_phy(struct qmp_combo *qmp); 1521 1522static void qmp_v4_dp_aux_init(struct qmp_combo *qmp); 1523static void qmp_v4_configure_dp_tx(struct qmp_combo *qmp); 1524static int qmp_v4_configure_dp_phy(struct qmp_combo *qmp); 1525static int qmp_v4_calibrate_dp_phy(struct qmp_combo *qmp); 1526 1527static inline void qphy_setbits(void __iomem *base, u32 offset, u32 val) 1528{ 1529 u32 reg; 1530 1531 reg = readl(base + offset); 1532 reg |= val; 1533 writel(reg, base + offset); 1534 1535 /* ensure that above write is through */ 1536 readl(base + offset); 1537} 1538 1539static inline void qphy_clrbits(void __iomem *base, u32 offset, u32 val) 1540{ 1541 u32 reg; 1542 1543 reg = readl(base + offset); 1544 reg &= ~val; 1545 writel(reg, base + offset); 1546 1547 /* ensure that above write is through */ 1548 readl(base + offset); 1549} 1550 1551/* list of clocks required by phy */ 1552static const char * const qmp_combo_phy_clk_l[] = { 1553 "aux", "cfg_ahb", "ref", "com_aux", 1554}; 1555 1556/* list of resets */ 1557static const char * const msm8996_usb3phy_reset_l[] = { 1558 "phy", "common", 1559}; 1560 1561static const char * const sc7180_usb3phy_reset_l[] = { 1562 "phy", 1563}; 1564 1565static const struct qmp_combo_offsets qmp_combo_offsets_v3 = { 1566 .com = 0x0000, 1567 .txa = 0x1200, 1568 .rxa = 0x1400, 1569 .txb = 0x1600, 1570 .rxb = 0x1800, 1571 .usb3_serdes = 0x1000, 1572 .usb3_pcs_misc = 0x1a00, 1573 .usb3_pcs = 0x1c00, 1574 .usb3_pcs_usb = 0x1f00, 1575 .dp_serdes = 0x2000, 1576 .dp_txa = 0x2200, 1577 .dp_txb = 0x2600, 1578 .dp_dp_phy = 0x2a00, 1579}; 1580 1581static const struct qmp_combo_offsets qmp_combo_offsets_v5 = { 1582 .com = 0x0000, 1583 .txa = 0x0400, 1584 .rxa = 0x0600, 1585 .txb = 0x0a00, 1586 .rxb = 0x0c00, 1587 .usb3_serdes = 0x1000, 1588 .usb3_pcs_misc = 0x1200, 1589 .usb3_pcs = 0x1400, 1590 .usb3_pcs_usb = 0x1700, 1591 .dp_serdes = 0x2000, 1592 .dp_dp_phy = 0x2200, 1593}; 1594 1595static const struct qmp_phy_cfg sc7180_usb3dpphy_cfg = { 1596 .offsets = &qmp_combo_offsets_v3, 1597 1598 .serdes_tbl = qmp_v3_usb3_serdes_tbl, 1599 .serdes_tbl_num = ARRAY_SIZE(qmp_v3_usb3_serdes_tbl), 1600 .tx_tbl = qmp_v3_usb3_tx_tbl, 1601 .tx_tbl_num = ARRAY_SIZE(qmp_v3_usb3_tx_tbl), 1602 .rx_tbl = qmp_v3_usb3_rx_tbl, 1603 .rx_tbl_num = ARRAY_SIZE(qmp_v3_usb3_rx_tbl), 1604 .pcs_tbl = qmp_v3_usb3_pcs_tbl, 1605 .pcs_tbl_num = ARRAY_SIZE(qmp_v3_usb3_pcs_tbl), 1606 1607 .dp_serdes_tbl = qmp_v3_dp_serdes_tbl, 1608 .dp_serdes_tbl_num = ARRAY_SIZE(qmp_v3_dp_serdes_tbl), 1609 .dp_tx_tbl = qmp_v3_dp_tx_tbl, 1610 .dp_tx_tbl_num = ARRAY_SIZE(qmp_v3_dp_tx_tbl), 1611 1612 .serdes_tbl_rbr = qmp_v3_dp_serdes_tbl_rbr, 1613 .serdes_tbl_rbr_num = ARRAY_SIZE(qmp_v3_dp_serdes_tbl_rbr), 1614 .serdes_tbl_hbr = qmp_v3_dp_serdes_tbl_hbr, 1615 .serdes_tbl_hbr_num = ARRAY_SIZE(qmp_v3_dp_serdes_tbl_hbr), 1616 .serdes_tbl_hbr2 = qmp_v3_dp_serdes_tbl_hbr2, 1617 .serdes_tbl_hbr2_num = ARRAY_SIZE(qmp_v3_dp_serdes_tbl_hbr2), 1618 .serdes_tbl_hbr3 = qmp_v3_dp_serdes_tbl_hbr3, 1619 .serdes_tbl_hbr3_num = ARRAY_SIZE(qmp_v3_dp_serdes_tbl_hbr3), 1620 1621 .swing_hbr_rbr = &qmp_dp_v3_voltage_swing_hbr_rbr, 1622 .pre_emphasis_hbr_rbr = &qmp_dp_v3_pre_emphasis_hbr_rbr, 1623 .swing_hbr3_hbr2 = &qmp_dp_v3_voltage_swing_hbr3_hbr2, 1624 .pre_emphasis_hbr3_hbr2 = &qmp_dp_v3_pre_emphasis_hbr3_hbr2, 1625 1626 .dp_aux_init = qmp_v3_dp_aux_init, 1627 .configure_dp_tx = qmp_v3_configure_dp_tx, 1628 .configure_dp_phy = qmp_v3_configure_dp_phy, 1629 .calibrate_dp_phy = qmp_v3_calibrate_dp_phy, 1630 1631 .reset_list = sc7180_usb3phy_reset_l, 1632 .num_resets = ARRAY_SIZE(sc7180_usb3phy_reset_l), 1633 .vreg_list = qmp_phy_vreg_l, 1634 .num_vregs = ARRAY_SIZE(qmp_phy_vreg_l), 1635 .regs = qmp_v3_usb3phy_regs_layout, 1636 1637 .has_pwrdn_delay = true, 1638}; 1639 1640static const struct qmp_phy_cfg sdm845_usb3dpphy_cfg = { 1641 .offsets = &qmp_combo_offsets_v3, 1642 1643 .serdes_tbl = qmp_v3_usb3_serdes_tbl, 1644 .serdes_tbl_num = ARRAY_SIZE(qmp_v3_usb3_serdes_tbl), 1645 .tx_tbl = qmp_v3_usb3_tx_tbl, 1646 .tx_tbl_num = ARRAY_SIZE(qmp_v3_usb3_tx_tbl), 1647 .rx_tbl = qmp_v3_usb3_rx_tbl, 1648 .rx_tbl_num = ARRAY_SIZE(qmp_v3_usb3_rx_tbl), 1649 .pcs_tbl = qmp_v3_usb3_pcs_tbl, 1650 .pcs_tbl_num = ARRAY_SIZE(qmp_v3_usb3_pcs_tbl), 1651 1652 .dp_serdes_tbl = qmp_v3_dp_serdes_tbl, 1653 .dp_serdes_tbl_num = ARRAY_SIZE(qmp_v3_dp_serdes_tbl), 1654 .dp_tx_tbl = qmp_v3_dp_tx_tbl, 1655 .dp_tx_tbl_num = ARRAY_SIZE(qmp_v3_dp_tx_tbl), 1656 1657 .serdes_tbl_rbr = qmp_v3_dp_serdes_tbl_rbr, 1658 .serdes_tbl_rbr_num = ARRAY_SIZE(qmp_v3_dp_serdes_tbl_rbr), 1659 .serdes_tbl_hbr = qmp_v3_dp_serdes_tbl_hbr, 1660 .serdes_tbl_hbr_num = ARRAY_SIZE(qmp_v3_dp_serdes_tbl_hbr), 1661 .serdes_tbl_hbr2 = qmp_v3_dp_serdes_tbl_hbr2, 1662 .serdes_tbl_hbr2_num = ARRAY_SIZE(qmp_v3_dp_serdes_tbl_hbr2), 1663 .serdes_tbl_hbr3 = qmp_v3_dp_serdes_tbl_hbr3, 1664 .serdes_tbl_hbr3_num = ARRAY_SIZE(qmp_v3_dp_serdes_tbl_hbr3), 1665 1666 .swing_hbr_rbr = &qmp_dp_v3_voltage_swing_hbr_rbr, 1667 .pre_emphasis_hbr_rbr = &qmp_dp_v3_pre_emphasis_hbr_rbr, 1668 .swing_hbr3_hbr2 = &qmp_dp_v3_voltage_swing_hbr3_hbr2, 1669 .pre_emphasis_hbr3_hbr2 = &qmp_dp_v3_pre_emphasis_hbr3_hbr2, 1670 1671 .dp_aux_init = qmp_v3_dp_aux_init, 1672 .configure_dp_tx = qmp_v3_configure_dp_tx, 1673 .configure_dp_phy = qmp_v3_configure_dp_phy, 1674 .calibrate_dp_phy = qmp_v3_calibrate_dp_phy, 1675 1676 .reset_list = msm8996_usb3phy_reset_l, 1677 .num_resets = ARRAY_SIZE(msm8996_usb3phy_reset_l), 1678 .vreg_list = qmp_phy_vreg_l, 1679 .num_vregs = ARRAY_SIZE(qmp_phy_vreg_l), 1680 .regs = qmp_v3_usb3phy_regs_layout, 1681 1682 .has_pwrdn_delay = true, 1683}; 1684 1685static const struct qmp_phy_cfg sc8180x_usb3dpphy_cfg = { 1686 .offsets = &qmp_combo_offsets_v3, 1687 1688 .serdes_tbl = sm8150_usb3_serdes_tbl, 1689 .serdes_tbl_num = ARRAY_SIZE(sm8150_usb3_serdes_tbl), 1690 .tx_tbl = sm8150_usb3_tx_tbl, 1691 .tx_tbl_num = ARRAY_SIZE(sm8150_usb3_tx_tbl), 1692 .rx_tbl = sm8150_usb3_rx_tbl, 1693 .rx_tbl_num = ARRAY_SIZE(sm8150_usb3_rx_tbl), 1694 .pcs_tbl = sm8150_usb3_pcs_tbl, 1695 .pcs_tbl_num = ARRAY_SIZE(sm8150_usb3_pcs_tbl), 1696 .pcs_usb_tbl = sm8150_usb3_pcs_usb_tbl, 1697 .pcs_usb_tbl_num = ARRAY_SIZE(sm8150_usb3_pcs_usb_tbl), 1698 1699 .dp_serdes_tbl = qmp_v4_dp_serdes_tbl, 1700 .dp_serdes_tbl_num = ARRAY_SIZE(qmp_v4_dp_serdes_tbl), 1701 .dp_tx_tbl = qmp_v4_dp_tx_tbl, 1702 .dp_tx_tbl_num = ARRAY_SIZE(qmp_v4_dp_tx_tbl), 1703 1704 .serdes_tbl_rbr = qmp_v4_dp_serdes_tbl_rbr, 1705 .serdes_tbl_rbr_num = ARRAY_SIZE(qmp_v4_dp_serdes_tbl_rbr), 1706 .serdes_tbl_hbr = qmp_v4_dp_serdes_tbl_hbr, 1707 .serdes_tbl_hbr_num = ARRAY_SIZE(qmp_v4_dp_serdes_tbl_hbr), 1708 .serdes_tbl_hbr2 = qmp_v4_dp_serdes_tbl_hbr2, 1709 .serdes_tbl_hbr2_num = ARRAY_SIZE(qmp_v4_dp_serdes_tbl_hbr2), 1710 .serdes_tbl_hbr3 = qmp_v4_dp_serdes_tbl_hbr3, 1711 .serdes_tbl_hbr3_num = ARRAY_SIZE(qmp_v4_dp_serdes_tbl_hbr3), 1712 1713 .swing_hbr_rbr = &qmp_dp_v3_voltage_swing_hbr_rbr, 1714 .pre_emphasis_hbr_rbr = &qmp_dp_v3_pre_emphasis_hbr_rbr, 1715 .swing_hbr3_hbr2 = &qmp_dp_v3_voltage_swing_hbr3_hbr2, 1716 .pre_emphasis_hbr3_hbr2 = &qmp_dp_v3_pre_emphasis_hbr3_hbr2, 1717 1718 .dp_aux_init = qmp_v4_dp_aux_init, 1719 .configure_dp_tx = qmp_v4_configure_dp_tx, 1720 .configure_dp_phy = qmp_v4_configure_dp_phy, 1721 .calibrate_dp_phy = qmp_v4_calibrate_dp_phy, 1722 1723 .reset_list = msm8996_usb3phy_reset_l, 1724 .num_resets = ARRAY_SIZE(msm8996_usb3phy_reset_l), 1725 .vreg_list = qmp_phy_vreg_l, 1726 .num_vregs = ARRAY_SIZE(qmp_phy_vreg_l), 1727 .regs = qmp_v45_usb3phy_regs_layout, 1728 .pcs_usb_offset = 0x300, 1729 1730 .has_pwrdn_delay = true, 1731}; 1732 1733static const struct qmp_phy_cfg sc8280xp_usb43dpphy_cfg = { 1734 .offsets = &qmp_combo_offsets_v5, 1735 1736 .serdes_tbl = sc8280xp_usb43dp_serdes_tbl, 1737 .serdes_tbl_num = ARRAY_SIZE(sc8280xp_usb43dp_serdes_tbl), 1738 .tx_tbl = sc8280xp_usb43dp_tx_tbl, 1739 .tx_tbl_num = ARRAY_SIZE(sc8280xp_usb43dp_tx_tbl), 1740 .rx_tbl = sc8280xp_usb43dp_rx_tbl, 1741 .rx_tbl_num = ARRAY_SIZE(sc8280xp_usb43dp_rx_tbl), 1742 .pcs_tbl = sc8280xp_usb43dp_pcs_tbl, 1743 .pcs_tbl_num = ARRAY_SIZE(sc8280xp_usb43dp_pcs_tbl), 1744 1745 .dp_serdes_tbl = qmp_v5_dp_serdes_tbl, 1746 .dp_serdes_tbl_num = ARRAY_SIZE(qmp_v5_dp_serdes_tbl), 1747 .dp_tx_tbl = qmp_v5_5nm_dp_tx_tbl, 1748 .dp_tx_tbl_num = ARRAY_SIZE(qmp_v5_5nm_dp_tx_tbl), 1749 1750 .serdes_tbl_rbr = qmp_v4_dp_serdes_tbl_rbr, 1751 .serdes_tbl_rbr_num = ARRAY_SIZE(qmp_v4_dp_serdes_tbl_rbr), 1752 .serdes_tbl_hbr = qmp_v4_dp_serdes_tbl_hbr, 1753 .serdes_tbl_hbr_num = ARRAY_SIZE(qmp_v4_dp_serdes_tbl_hbr), 1754 .serdes_tbl_hbr2 = qmp_v4_dp_serdes_tbl_hbr2, 1755 .serdes_tbl_hbr2_num = ARRAY_SIZE(qmp_v4_dp_serdes_tbl_hbr2), 1756 .serdes_tbl_hbr3 = qmp_v4_dp_serdes_tbl_hbr3, 1757 .serdes_tbl_hbr3_num = ARRAY_SIZE(qmp_v4_dp_serdes_tbl_hbr3), 1758 1759 .swing_hbr_rbr = &qmp_dp_v5_voltage_swing_hbr_rbr, 1760 .pre_emphasis_hbr_rbr = &qmp_dp_v5_pre_emphasis_hbr_rbr, 1761 .swing_hbr3_hbr2 = &qmp_dp_v5_voltage_swing_hbr3_hbr2, 1762 .pre_emphasis_hbr3_hbr2 = &qmp_dp_v5_pre_emphasis_hbr3_hbr2, 1763 1764 .dp_aux_init = qmp_v4_dp_aux_init, 1765 .configure_dp_tx = qmp_v4_configure_dp_tx, 1766 .configure_dp_phy = qmp_v4_configure_dp_phy, 1767 .calibrate_dp_phy = qmp_v4_calibrate_dp_phy, 1768 1769 .reset_list = msm8996_usb3phy_reset_l, 1770 .num_resets = ARRAY_SIZE(msm8996_usb3phy_reset_l), 1771 .vreg_list = qmp_phy_vreg_l, 1772 .num_vregs = ARRAY_SIZE(qmp_phy_vreg_l), 1773 .regs = qmp_v5_5nm_usb3phy_regs_layout, 1774}; 1775 1776static const struct qmp_phy_cfg x1e80100_usb3dpphy_cfg = { 1777 .offsets = &qmp_combo_offsets_v5, 1778 1779 .serdes_tbl = x1e80100_usb43dp_serdes_tbl, 1780 .serdes_tbl_num = ARRAY_SIZE(x1e80100_usb43dp_serdes_tbl), 1781 .tx_tbl = x1e80100_usb43dp_tx_tbl, 1782 .tx_tbl_num = ARRAY_SIZE(x1e80100_usb43dp_tx_tbl), 1783 .rx_tbl = x1e80100_usb43dp_rx_tbl, 1784 .rx_tbl_num = ARRAY_SIZE(x1e80100_usb43dp_rx_tbl), 1785 .pcs_tbl = x1e80100_usb43dp_pcs_tbl, 1786 .pcs_tbl_num = ARRAY_SIZE(x1e80100_usb43dp_pcs_tbl), 1787 .pcs_usb_tbl = x1e80100_usb43dp_pcs_usb_tbl, 1788 .pcs_usb_tbl_num = ARRAY_SIZE(x1e80100_usb43dp_pcs_usb_tbl), 1789 1790 .dp_serdes_tbl = qmp_v6_dp_serdes_tbl, 1791 .dp_serdes_tbl_num = ARRAY_SIZE(qmp_v6_dp_serdes_tbl), 1792 .dp_tx_tbl = qmp_v6_dp_tx_tbl, 1793 .dp_tx_tbl_num = ARRAY_SIZE(qmp_v6_dp_tx_tbl), 1794 1795 .serdes_tbl_rbr = qmp_v6_dp_serdes_tbl_rbr, 1796 .serdes_tbl_rbr_num = ARRAY_SIZE(qmp_v6_dp_serdes_tbl_rbr), 1797 .serdes_tbl_hbr = qmp_v6_dp_serdes_tbl_hbr, 1798 .serdes_tbl_hbr_num = ARRAY_SIZE(qmp_v6_dp_serdes_tbl_hbr), 1799 .serdes_tbl_hbr2 = qmp_v6_dp_serdes_tbl_hbr2, 1800 .serdes_tbl_hbr2_num = ARRAY_SIZE(qmp_v6_dp_serdes_tbl_hbr2), 1801 .serdes_tbl_hbr3 = qmp_v6_dp_serdes_tbl_hbr3, 1802 .serdes_tbl_hbr3_num = ARRAY_SIZE(qmp_v6_dp_serdes_tbl_hbr3), 1803 1804 .swing_hbr_rbr = &qmp_dp_v5_voltage_swing_hbr_rbr, 1805 .pre_emphasis_hbr_rbr = &qmp_dp_v5_pre_emphasis_hbr_rbr, 1806 .swing_hbr3_hbr2 = &qmp_dp_v5_voltage_swing_hbr3_hbr2, 1807 .pre_emphasis_hbr3_hbr2 = &qmp_dp_v5_pre_emphasis_hbr3_hbr2, 1808 1809 .dp_aux_init = qmp_v4_dp_aux_init, 1810 .configure_dp_tx = qmp_v4_configure_dp_tx, 1811 .configure_dp_phy = qmp_v4_configure_dp_phy, 1812 .calibrate_dp_phy = qmp_v4_calibrate_dp_phy, 1813 1814 .reset_list = msm8996_usb3phy_reset_l, 1815 .num_resets = ARRAY_SIZE(msm8996_usb3phy_reset_l), 1816 .vreg_list = qmp_phy_vreg_l, 1817 .num_vregs = ARRAY_SIZE(qmp_phy_vreg_l), 1818 .regs = qmp_v45_usb3phy_regs_layout, 1819}; 1820 1821static const struct qmp_phy_cfg sm6350_usb3dpphy_cfg = { 1822 .offsets = &qmp_combo_offsets_v3, 1823 1824 .serdes_tbl = qmp_v3_usb3_serdes_tbl, 1825 .serdes_tbl_num = ARRAY_SIZE(qmp_v3_usb3_serdes_tbl), 1826 .tx_tbl = qmp_v3_usb3_tx_tbl, 1827 .tx_tbl_num = ARRAY_SIZE(qmp_v3_usb3_tx_tbl), 1828 .rx_tbl = sm6350_usb3_rx_tbl, 1829 .rx_tbl_num = ARRAY_SIZE(sm6350_usb3_rx_tbl), 1830 .pcs_tbl = sm6350_usb3_pcs_tbl, 1831 .pcs_tbl_num = ARRAY_SIZE(sm6350_usb3_pcs_tbl), 1832 1833 .dp_serdes_tbl = qmp_v3_dp_serdes_tbl, 1834 .dp_serdes_tbl_num = ARRAY_SIZE(qmp_v3_dp_serdes_tbl), 1835 .dp_tx_tbl = qmp_v3_dp_tx_tbl, 1836 .dp_tx_tbl_num = ARRAY_SIZE(qmp_v3_dp_tx_tbl), 1837 1838 .serdes_tbl_rbr = qmp_v3_dp_serdes_tbl_rbr, 1839 .serdes_tbl_rbr_num = ARRAY_SIZE(qmp_v3_dp_serdes_tbl_rbr), 1840 .serdes_tbl_hbr = qmp_v3_dp_serdes_tbl_hbr, 1841 .serdes_tbl_hbr_num = ARRAY_SIZE(qmp_v3_dp_serdes_tbl_hbr), 1842 .serdes_tbl_hbr2 = qmp_v3_dp_serdes_tbl_hbr2, 1843 .serdes_tbl_hbr2_num = ARRAY_SIZE(qmp_v3_dp_serdes_tbl_hbr2), 1844 .serdes_tbl_hbr3 = qmp_v3_dp_serdes_tbl_hbr3, 1845 .serdes_tbl_hbr3_num = ARRAY_SIZE(qmp_v3_dp_serdes_tbl_hbr3), 1846 1847 .swing_hbr_rbr = &qmp_dp_v3_voltage_swing_hbr_rbr, 1848 .pre_emphasis_hbr_rbr = &qmp_dp_v3_pre_emphasis_hbr_rbr, 1849 .swing_hbr3_hbr2 = &qmp_dp_v3_voltage_swing_hbr3_hbr2, 1850 .pre_emphasis_hbr3_hbr2 = &qmp_dp_v3_pre_emphasis_hbr3_hbr2, 1851 1852 .dp_aux_init = qmp_v3_dp_aux_init, 1853 .configure_dp_tx = qmp_v3_configure_dp_tx, 1854 .configure_dp_phy = qmp_v3_configure_dp_phy, 1855 .calibrate_dp_phy = qmp_v3_calibrate_dp_phy, 1856 1857 .reset_list = msm8996_usb3phy_reset_l, 1858 .num_resets = ARRAY_SIZE(msm8996_usb3phy_reset_l), 1859 .vreg_list = qmp_phy_vreg_l, 1860 .num_vregs = ARRAY_SIZE(qmp_phy_vreg_l), 1861 .regs = qmp_v3_usb3phy_regs_layout, 1862}; 1863 1864static const struct qmp_phy_cfg sm8250_usb3dpphy_cfg = { 1865 .offsets = &qmp_combo_offsets_v3, 1866 1867 .serdes_tbl = sm8150_usb3_serdes_tbl, 1868 .serdes_tbl_num = ARRAY_SIZE(sm8150_usb3_serdes_tbl), 1869 .tx_tbl = sm8250_usb3_tx_tbl, 1870 .tx_tbl_num = ARRAY_SIZE(sm8250_usb3_tx_tbl), 1871 .rx_tbl = sm8250_usb3_rx_tbl, 1872 .rx_tbl_num = ARRAY_SIZE(sm8250_usb3_rx_tbl), 1873 .pcs_tbl = sm8250_usb3_pcs_tbl, 1874 .pcs_tbl_num = ARRAY_SIZE(sm8250_usb3_pcs_tbl), 1875 .pcs_usb_tbl = sm8250_usb3_pcs_usb_tbl, 1876 .pcs_usb_tbl_num = ARRAY_SIZE(sm8250_usb3_pcs_usb_tbl), 1877 1878 .dp_serdes_tbl = qmp_v4_dp_serdes_tbl, 1879 .dp_serdes_tbl_num = ARRAY_SIZE(qmp_v4_dp_serdes_tbl), 1880 .dp_tx_tbl = qmp_v4_dp_tx_tbl, 1881 .dp_tx_tbl_num = ARRAY_SIZE(qmp_v4_dp_tx_tbl), 1882 1883 .serdes_tbl_rbr = qmp_v4_dp_serdes_tbl_rbr, 1884 .serdes_tbl_rbr_num = ARRAY_SIZE(qmp_v4_dp_serdes_tbl_rbr), 1885 .serdes_tbl_hbr = qmp_v4_dp_serdes_tbl_hbr, 1886 .serdes_tbl_hbr_num = ARRAY_SIZE(qmp_v4_dp_serdes_tbl_hbr), 1887 .serdes_tbl_hbr2 = qmp_v4_dp_serdes_tbl_hbr2, 1888 .serdes_tbl_hbr2_num = ARRAY_SIZE(qmp_v4_dp_serdes_tbl_hbr2), 1889 .serdes_tbl_hbr3 = qmp_v4_dp_serdes_tbl_hbr3, 1890 .serdes_tbl_hbr3_num = ARRAY_SIZE(qmp_v4_dp_serdes_tbl_hbr3), 1891 1892 .swing_hbr_rbr = &qmp_dp_v3_voltage_swing_hbr_rbr, 1893 .pre_emphasis_hbr_rbr = &qmp_dp_v3_pre_emphasis_hbr_rbr, 1894 .swing_hbr3_hbr2 = &qmp_dp_v3_voltage_swing_hbr3_hbr2, 1895 .pre_emphasis_hbr3_hbr2 = &qmp_dp_v3_pre_emphasis_hbr3_hbr2, 1896 1897 .dp_aux_init = qmp_v4_dp_aux_init, 1898 .configure_dp_tx = qmp_v4_configure_dp_tx, 1899 .configure_dp_phy = qmp_v4_configure_dp_phy, 1900 .calibrate_dp_phy = qmp_v4_calibrate_dp_phy, 1901 1902 .reset_list = msm8996_usb3phy_reset_l, 1903 .num_resets = ARRAY_SIZE(msm8996_usb3phy_reset_l), 1904 .vreg_list = qmp_phy_vreg_l, 1905 .num_vregs = ARRAY_SIZE(qmp_phy_vreg_l), 1906 .regs = qmp_v45_usb3phy_regs_layout, 1907 .pcs_usb_offset = 0x300, 1908 1909 .has_pwrdn_delay = true, 1910}; 1911 1912static const struct qmp_phy_cfg sm8350_usb3dpphy_cfg = { 1913 .offsets = &qmp_combo_offsets_v3, 1914 1915 .serdes_tbl = sm8150_usb3_serdes_tbl, 1916 .serdes_tbl_num = ARRAY_SIZE(sm8150_usb3_serdes_tbl), 1917 .tx_tbl = sm8350_usb3_tx_tbl, 1918 .tx_tbl_num = ARRAY_SIZE(sm8350_usb3_tx_tbl), 1919 .rx_tbl = sm8350_usb3_rx_tbl, 1920 .rx_tbl_num = ARRAY_SIZE(sm8350_usb3_rx_tbl), 1921 .pcs_tbl = sm8350_usb3_pcs_tbl, 1922 .pcs_tbl_num = ARRAY_SIZE(sm8350_usb3_pcs_tbl), 1923 .pcs_usb_tbl = sm8350_usb3_pcs_usb_tbl, 1924 .pcs_usb_tbl_num = ARRAY_SIZE(sm8350_usb3_pcs_usb_tbl), 1925 1926 .dp_serdes_tbl = qmp_v4_dp_serdes_tbl, 1927 .dp_serdes_tbl_num = ARRAY_SIZE(qmp_v4_dp_serdes_tbl), 1928 .dp_tx_tbl = qmp_v5_dp_tx_tbl, 1929 .dp_tx_tbl_num = ARRAY_SIZE(qmp_v5_dp_tx_tbl), 1930 1931 .serdes_tbl_rbr = qmp_v4_dp_serdes_tbl_rbr, 1932 .serdes_tbl_rbr_num = ARRAY_SIZE(qmp_v4_dp_serdes_tbl_rbr), 1933 .serdes_tbl_hbr = qmp_v4_dp_serdes_tbl_hbr, 1934 .serdes_tbl_hbr_num = ARRAY_SIZE(qmp_v4_dp_serdes_tbl_hbr), 1935 .serdes_tbl_hbr2 = qmp_v4_dp_serdes_tbl_hbr2, 1936 .serdes_tbl_hbr2_num = ARRAY_SIZE(qmp_v4_dp_serdes_tbl_hbr2), 1937 .serdes_tbl_hbr3 = qmp_v4_dp_serdes_tbl_hbr3, 1938 .serdes_tbl_hbr3_num = ARRAY_SIZE(qmp_v4_dp_serdes_tbl_hbr3), 1939 1940 .swing_hbr_rbr = &qmp_dp_v4_voltage_swing_hbr_rbr, 1941 .pre_emphasis_hbr_rbr = &qmp_dp_v4_pre_emphasis_hbr_rbr, 1942 .swing_hbr3_hbr2 = &qmp_dp_v3_voltage_swing_hbr3_hbr2, 1943 .pre_emphasis_hbr3_hbr2 = &qmp_dp_v4_pre_emphasis_hbr3_hbr2, 1944 1945 .dp_aux_init = qmp_v4_dp_aux_init, 1946 .configure_dp_tx = qmp_v4_configure_dp_tx, 1947 .configure_dp_phy = qmp_v4_configure_dp_phy, 1948 .calibrate_dp_phy = qmp_v4_calibrate_dp_phy, 1949 1950 .reset_list = msm8996_usb3phy_reset_l, 1951 .num_resets = ARRAY_SIZE(msm8996_usb3phy_reset_l), 1952 .vreg_list = qmp_phy_vreg_l, 1953 .num_vregs = ARRAY_SIZE(qmp_phy_vreg_l), 1954 .regs = qmp_v45_usb3phy_regs_layout, 1955 1956 .has_pwrdn_delay = true, 1957}; 1958 1959static const struct qmp_phy_cfg sm8550_usb3dpphy_cfg = { 1960 .offsets = &qmp_combo_offsets_v3, 1961 1962 .serdes_tbl = sm8550_usb3_serdes_tbl, 1963 .serdes_tbl_num = ARRAY_SIZE(sm8550_usb3_serdes_tbl), 1964 .tx_tbl = sm8550_usb3_tx_tbl, 1965 .tx_tbl_num = ARRAY_SIZE(sm8550_usb3_tx_tbl), 1966 .rx_tbl = sm8550_usb3_rx_tbl, 1967 .rx_tbl_num = ARRAY_SIZE(sm8550_usb3_rx_tbl), 1968 .pcs_tbl = sm8550_usb3_pcs_tbl, 1969 .pcs_tbl_num = ARRAY_SIZE(sm8550_usb3_pcs_tbl), 1970 .pcs_usb_tbl = sm8550_usb3_pcs_usb_tbl, 1971 .pcs_usb_tbl_num = ARRAY_SIZE(sm8550_usb3_pcs_usb_tbl), 1972 1973 .dp_serdes_tbl = qmp_v6_dp_serdes_tbl, 1974 .dp_serdes_tbl_num = ARRAY_SIZE(qmp_v6_dp_serdes_tbl), 1975 .dp_tx_tbl = qmp_v6_dp_tx_tbl, 1976 .dp_tx_tbl_num = ARRAY_SIZE(qmp_v6_dp_tx_tbl), 1977 1978 .serdes_tbl_rbr = qmp_v6_dp_serdes_tbl_rbr, 1979 .serdes_tbl_rbr_num = ARRAY_SIZE(qmp_v6_dp_serdes_tbl_rbr), 1980 .serdes_tbl_hbr = qmp_v6_dp_serdes_tbl_hbr, 1981 .serdes_tbl_hbr_num = ARRAY_SIZE(qmp_v6_dp_serdes_tbl_hbr), 1982 .serdes_tbl_hbr2 = qmp_v6_dp_serdes_tbl_hbr2, 1983 .serdes_tbl_hbr2_num = ARRAY_SIZE(qmp_v6_dp_serdes_tbl_hbr2), 1984 .serdes_tbl_hbr3 = qmp_v6_dp_serdes_tbl_hbr3, 1985 .serdes_tbl_hbr3_num = ARRAY_SIZE(qmp_v6_dp_serdes_tbl_hbr3), 1986 1987 .swing_hbr_rbr = &qmp_dp_v5_voltage_swing_hbr_rbr, 1988 .pre_emphasis_hbr_rbr = &qmp_dp_v6_pre_emphasis_hbr_rbr, 1989 .swing_hbr3_hbr2 = &qmp_dp_v5_voltage_swing_hbr3_hbr2, 1990 .pre_emphasis_hbr3_hbr2 = &qmp_dp_v5_pre_emphasis_hbr3_hbr2, 1991 1992 .dp_aux_init = qmp_v4_dp_aux_init, 1993 .configure_dp_tx = qmp_v4_configure_dp_tx, 1994 .configure_dp_phy = qmp_v4_configure_dp_phy, 1995 .calibrate_dp_phy = qmp_v4_calibrate_dp_phy, 1996 1997 .regs = qmp_v6_usb3phy_regs_layout, 1998 .reset_list = msm8996_usb3phy_reset_l, 1999 .num_resets = ARRAY_SIZE(msm8996_usb3phy_reset_l), 2000 .vreg_list = qmp_phy_vreg_l, 2001 .num_vregs = ARRAY_SIZE(qmp_phy_vreg_l), 2002}; 2003 2004static int qmp_combo_dp_serdes_init(struct qmp_combo *qmp) 2005{ 2006 const struct qmp_phy_cfg *cfg = qmp->cfg; 2007 void __iomem *serdes = qmp->dp_serdes; 2008 const struct phy_configure_opts_dp *dp_opts = &qmp->dp_opts; 2009 2010 qmp_configure(serdes, cfg->dp_serdes_tbl, cfg->dp_serdes_tbl_num); 2011 2012 switch (dp_opts->link_rate) { 2013 case 1620: 2014 qmp_configure(serdes, cfg->serdes_tbl_rbr, 2015 cfg->serdes_tbl_rbr_num); 2016 break; 2017 case 2700: 2018 qmp_configure(serdes, cfg->serdes_tbl_hbr, 2019 cfg->serdes_tbl_hbr_num); 2020 break; 2021 case 5400: 2022 qmp_configure(serdes, cfg->serdes_tbl_hbr2, 2023 cfg->serdes_tbl_hbr2_num); 2024 break; 2025 case 8100: 2026 qmp_configure(serdes, cfg->serdes_tbl_hbr3, 2027 cfg->serdes_tbl_hbr3_num); 2028 break; 2029 default: 2030 /* Other link rates aren't supported */ 2031 return -EINVAL; 2032 } 2033 2034 return 0; 2035} 2036 2037static void qmp_v3_dp_aux_init(struct qmp_combo *qmp) 2038{ 2039 const struct qmp_phy_cfg *cfg = qmp->cfg; 2040 2041 writel(DP_PHY_PD_CTL_PWRDN | DP_PHY_PD_CTL_AUX_PWRDN | 2042 DP_PHY_PD_CTL_PLL_PWRDN | DP_PHY_PD_CTL_DP_CLAMP_EN, 2043 qmp->dp_dp_phy + QSERDES_DP_PHY_PD_CTL); 2044 2045 /* Turn on BIAS current for PHY/PLL */ 2046 writel(QSERDES_V3_COM_BIAS_EN | QSERDES_V3_COM_BIAS_EN_MUX | 2047 QSERDES_V3_COM_CLKBUF_L_EN | QSERDES_V3_COM_EN_SYSCLK_TX_SEL, 2048 qmp->dp_serdes + cfg->regs[QPHY_COM_BIAS_EN_CLKBUFLR_EN]); 2049 2050 writel(DP_PHY_PD_CTL_PSR_PWRDN, qmp->dp_dp_phy + QSERDES_DP_PHY_PD_CTL); 2051 2052 writel(DP_PHY_PD_CTL_PWRDN | DP_PHY_PD_CTL_AUX_PWRDN | 2053 DP_PHY_PD_CTL_LANE_0_1_PWRDN | 2054 DP_PHY_PD_CTL_LANE_2_3_PWRDN | DP_PHY_PD_CTL_PLL_PWRDN | 2055 DP_PHY_PD_CTL_DP_CLAMP_EN, 2056 qmp->dp_dp_phy + QSERDES_DP_PHY_PD_CTL); 2057 2058 writel(QSERDES_V3_COM_BIAS_EN | 2059 QSERDES_V3_COM_BIAS_EN_MUX | QSERDES_V3_COM_CLKBUF_R_EN | 2060 QSERDES_V3_COM_CLKBUF_L_EN | QSERDES_V3_COM_EN_SYSCLK_TX_SEL | 2061 QSERDES_V3_COM_CLKBUF_RX_DRIVE_L, 2062 qmp->dp_serdes + cfg->regs[QPHY_COM_BIAS_EN_CLKBUFLR_EN]); 2063 2064 writel(0x00, qmp->dp_dp_phy + QSERDES_DP_PHY_AUX_CFG0); 2065 writel(0x13, qmp->dp_dp_phy + QSERDES_DP_PHY_AUX_CFG1); 2066 writel(0x24, qmp->dp_dp_phy + QSERDES_DP_PHY_AUX_CFG2); 2067 writel(0x00, qmp->dp_dp_phy + QSERDES_DP_PHY_AUX_CFG3); 2068 writel(0x0a, qmp->dp_dp_phy + QSERDES_DP_PHY_AUX_CFG4); 2069 writel(0x26, qmp->dp_dp_phy + QSERDES_DP_PHY_AUX_CFG5); 2070 writel(0x0a, qmp->dp_dp_phy + QSERDES_DP_PHY_AUX_CFG6); 2071 writel(0x03, qmp->dp_dp_phy + QSERDES_DP_PHY_AUX_CFG7); 2072 writel(0xbb, qmp->dp_dp_phy + QSERDES_DP_PHY_AUX_CFG8); 2073 writel(0x03, qmp->dp_dp_phy + QSERDES_DP_PHY_AUX_CFG9); 2074 qmp->dp_aux_cfg = 0; 2075 2076 writel(PHY_AUX_STOP_ERR_MASK | PHY_AUX_DEC_ERR_MASK | 2077 PHY_AUX_SYNC_ERR_MASK | PHY_AUX_ALIGN_ERR_MASK | 2078 PHY_AUX_REQ_ERR_MASK, 2079 qmp->dp_dp_phy + QSERDES_V3_DP_PHY_AUX_INTERRUPT_MASK); 2080} 2081 2082static int qmp_combo_configure_dp_swing(struct qmp_combo *qmp) 2083{ 2084 const struct phy_configure_opts_dp *dp_opts = &qmp->dp_opts; 2085 const struct qmp_phy_cfg *cfg = qmp->cfg; 2086 unsigned int v_level = 0, p_level = 0; 2087 u8 voltage_swing_cfg, pre_emphasis_cfg; 2088 int i; 2089 2090 for (i = 0; i < dp_opts->lanes; i++) { 2091 v_level = max(v_level, dp_opts->voltage[i]); 2092 p_level = max(p_level, dp_opts->pre[i]); 2093 } 2094 2095 if (dp_opts->link_rate <= 2700) { 2096 voltage_swing_cfg = (*cfg->swing_hbr_rbr)[v_level][p_level]; 2097 pre_emphasis_cfg = (*cfg->pre_emphasis_hbr_rbr)[v_level][p_level]; 2098 } else { 2099 voltage_swing_cfg = (*cfg->swing_hbr3_hbr2)[v_level][p_level]; 2100 pre_emphasis_cfg = (*cfg->pre_emphasis_hbr3_hbr2)[v_level][p_level]; 2101 } 2102 2103 /* TODO: Move check to config check */ 2104 if (voltage_swing_cfg == 0xFF && pre_emphasis_cfg == 0xFF) 2105 return -EINVAL; 2106 2107 /* Enable MUX to use Cursor values from these registers */ 2108 voltage_swing_cfg |= DP_PHY_TXn_TX_DRV_LVL_MUX_EN; 2109 pre_emphasis_cfg |= DP_PHY_TXn_TX_EMP_POST1_LVL_MUX_EN; 2110 2111 writel(voltage_swing_cfg, qmp->dp_tx + cfg->regs[QPHY_TX_TX_DRV_LVL]); 2112 writel(pre_emphasis_cfg, qmp->dp_tx + cfg->regs[QPHY_TX_TX_EMP_POST1_LVL]); 2113 writel(voltage_swing_cfg, qmp->dp_tx2 + cfg->regs[QPHY_TX_TX_DRV_LVL]); 2114 writel(pre_emphasis_cfg, qmp->dp_tx2 + cfg->regs[QPHY_TX_TX_EMP_POST1_LVL]); 2115 2116 return 0; 2117} 2118 2119static void qmp_v3_configure_dp_tx(struct qmp_combo *qmp) 2120{ 2121 const struct phy_configure_opts_dp *dp_opts = &qmp->dp_opts; 2122 u32 bias_en, drvr_en; 2123 2124 if (qmp_combo_configure_dp_swing(qmp) < 0) 2125 return; 2126 2127 if (dp_opts->lanes == 1) { 2128 bias_en = 0x3e; 2129 drvr_en = 0x13; 2130 } else { 2131 bias_en = 0x3f; 2132 drvr_en = 0x10; 2133 } 2134 2135 writel(drvr_en, qmp->dp_tx + QSERDES_V3_TX_HIGHZ_DRVR_EN); 2136 writel(bias_en, qmp->dp_tx + QSERDES_V3_TX_TRANSCEIVER_BIAS_EN); 2137 writel(drvr_en, qmp->dp_tx2 + QSERDES_V3_TX_HIGHZ_DRVR_EN); 2138 writel(bias_en, qmp->dp_tx2 + QSERDES_V3_TX_TRANSCEIVER_BIAS_EN); 2139} 2140 2141static bool qmp_combo_configure_dp_mode(struct qmp_combo *qmp) 2142{ 2143 bool reverse = (qmp->orientation == TYPEC_ORIENTATION_REVERSE); 2144 const struct phy_configure_opts_dp *dp_opts = &qmp->dp_opts; 2145 u32 val; 2146 2147 val = DP_PHY_PD_CTL_PWRDN | DP_PHY_PD_CTL_AUX_PWRDN | 2148 DP_PHY_PD_CTL_PLL_PWRDN | DP_PHY_PD_CTL_DP_CLAMP_EN; 2149 2150 if (dp_opts->lanes == 4 || reverse) 2151 val |= DP_PHY_PD_CTL_LANE_0_1_PWRDN; 2152 if (dp_opts->lanes == 4 || !reverse) 2153 val |= DP_PHY_PD_CTL_LANE_2_3_PWRDN; 2154 2155 writel(val, qmp->dp_dp_phy + QSERDES_DP_PHY_PD_CTL); 2156 2157 if (reverse) 2158 writel(0x4c, qmp->dp_dp_phy + QSERDES_DP_PHY_MODE); 2159 else 2160 writel(0x5c, qmp->dp_dp_phy + QSERDES_DP_PHY_MODE); 2161 2162 return reverse; 2163} 2164 2165static int qmp_combo_configure_dp_clocks(struct qmp_combo *qmp) 2166{ 2167 const struct phy_configure_opts_dp *dp_opts = &qmp->dp_opts; 2168 u32 phy_vco_div; 2169 unsigned long pixel_freq; 2170 const struct qmp_phy_cfg *cfg = qmp->cfg; 2171 2172 switch (dp_opts->link_rate) { 2173 case 1620: 2174 phy_vco_div = 0x1; 2175 pixel_freq = 1620000000UL / 2; 2176 break; 2177 case 2700: 2178 phy_vco_div = 0x1; 2179 pixel_freq = 2700000000UL / 2; 2180 break; 2181 case 5400: 2182 phy_vco_div = 0x2; 2183 pixel_freq = 5400000000UL / 4; 2184 break; 2185 case 8100: 2186 phy_vco_div = 0x0; 2187 pixel_freq = 8100000000UL / 6; 2188 break; 2189 default: 2190 /* Other link rates aren't supported */ 2191 return -EINVAL; 2192 } 2193 writel(phy_vco_div, qmp->dp_dp_phy + cfg->regs[QPHY_DP_PHY_VCO_DIV]); 2194 2195 clk_set_rate(qmp->dp_link_hw.clk, dp_opts->link_rate * 100000); 2196 clk_set_rate(qmp->dp_pixel_hw.clk, pixel_freq); 2197 2198 return 0; 2199} 2200 2201static int qmp_v3_configure_dp_phy(struct qmp_combo *qmp) 2202{ 2203 const struct qmp_phy_cfg *cfg = qmp->cfg; 2204 u32 status; 2205 int ret; 2206 2207 qmp_combo_configure_dp_mode(qmp); 2208 2209 writel(0x05, qmp->dp_dp_phy + QSERDES_V3_DP_PHY_TX0_TX1_LANE_CTL); 2210 writel(0x05, qmp->dp_dp_phy + QSERDES_V3_DP_PHY_TX2_TX3_LANE_CTL); 2211 2212 ret = qmp_combo_configure_dp_clocks(qmp); 2213 if (ret) 2214 return ret; 2215 2216 writel(0x04, qmp->dp_dp_phy + QSERDES_DP_PHY_AUX_CFG2); 2217 writel(0x01, qmp->dp_dp_phy + QSERDES_DP_PHY_CFG); 2218 writel(0x05, qmp->dp_dp_phy + QSERDES_DP_PHY_CFG); 2219 writel(0x01, qmp->dp_dp_phy + QSERDES_DP_PHY_CFG); 2220 writel(0x09, qmp->dp_dp_phy + QSERDES_DP_PHY_CFG); 2221 2222 writel(0x20, qmp->dp_serdes + cfg->regs[QPHY_COM_RESETSM_CNTRL]); 2223 2224 if (readl_poll_timeout(qmp->dp_serdes + cfg->regs[QPHY_COM_C_READY_STATUS], 2225 status, 2226 ((status & BIT(0)) > 0), 2227 500, 2228 10000)) 2229 return -ETIMEDOUT; 2230 2231 writel(0x19, qmp->dp_dp_phy + QSERDES_DP_PHY_CFG); 2232 2233 if (readl_poll_timeout(qmp->dp_dp_phy + cfg->regs[QPHY_DP_PHY_STATUS], 2234 status, 2235 ((status & BIT(1)) > 0), 2236 500, 2237 10000)) 2238 return -ETIMEDOUT; 2239 2240 writel(0x18, qmp->dp_dp_phy + QSERDES_DP_PHY_CFG); 2241 udelay(2000); 2242 writel(0x19, qmp->dp_dp_phy + QSERDES_DP_PHY_CFG); 2243 2244 return readl_poll_timeout(qmp->dp_dp_phy + cfg->regs[QPHY_DP_PHY_STATUS], 2245 status, 2246 ((status & BIT(1)) > 0), 2247 500, 2248 10000); 2249} 2250 2251/* 2252 * We need to calibrate the aux setting here as many times 2253 * as the caller tries 2254 */ 2255static int qmp_v3_calibrate_dp_phy(struct qmp_combo *qmp) 2256{ 2257 static const u8 cfg1_settings[] = { 0x13, 0x23, 0x1d }; 2258 u8 val; 2259 2260 qmp->dp_aux_cfg++; 2261 qmp->dp_aux_cfg %= ARRAY_SIZE(cfg1_settings); 2262 val = cfg1_settings[qmp->dp_aux_cfg]; 2263 2264 writel(val, qmp->dp_dp_phy + QSERDES_DP_PHY_AUX_CFG1); 2265 2266 return 0; 2267} 2268 2269static void qmp_v4_dp_aux_init(struct qmp_combo *qmp) 2270{ 2271 const struct qmp_phy_cfg *cfg = qmp->cfg; 2272 2273 writel(DP_PHY_PD_CTL_PWRDN | DP_PHY_PD_CTL_PSR_PWRDN | DP_PHY_PD_CTL_AUX_PWRDN | 2274 DP_PHY_PD_CTL_PLL_PWRDN | DP_PHY_PD_CTL_DP_CLAMP_EN, 2275 qmp->dp_dp_phy + QSERDES_DP_PHY_PD_CTL); 2276 2277 /* Turn on BIAS current for PHY/PLL */ 2278 writel(0x17, qmp->dp_serdes + cfg->regs[QPHY_COM_BIAS_EN_CLKBUFLR_EN]); 2279 2280 writel(0x00, qmp->dp_dp_phy + QSERDES_DP_PHY_AUX_CFG0); 2281 writel(0x13, qmp->dp_dp_phy + QSERDES_DP_PHY_AUX_CFG1); 2282 writel(0xa4, qmp->dp_dp_phy + QSERDES_DP_PHY_AUX_CFG2); 2283 writel(0x00, qmp->dp_dp_phy + QSERDES_DP_PHY_AUX_CFG3); 2284 writel(0x0a, qmp->dp_dp_phy + QSERDES_DP_PHY_AUX_CFG4); 2285 writel(0x26, qmp->dp_dp_phy + QSERDES_DP_PHY_AUX_CFG5); 2286 writel(0x0a, qmp->dp_dp_phy + QSERDES_DP_PHY_AUX_CFG6); 2287 writel(0x03, qmp->dp_dp_phy + QSERDES_DP_PHY_AUX_CFG7); 2288 writel(0xb7, qmp->dp_dp_phy + QSERDES_DP_PHY_AUX_CFG8); 2289 writel(0x03, qmp->dp_dp_phy + QSERDES_DP_PHY_AUX_CFG9); 2290 qmp->dp_aux_cfg = 0; 2291 2292 writel(PHY_AUX_STOP_ERR_MASK | PHY_AUX_DEC_ERR_MASK | 2293 PHY_AUX_SYNC_ERR_MASK | PHY_AUX_ALIGN_ERR_MASK | 2294 PHY_AUX_REQ_ERR_MASK, 2295 qmp->dp_dp_phy + QSERDES_V4_DP_PHY_AUX_INTERRUPT_MASK); 2296} 2297 2298static void qmp_v4_configure_dp_tx(struct qmp_combo *qmp) 2299{ 2300 const struct qmp_phy_cfg *cfg = qmp->cfg; 2301 2302 /* Program default values before writing proper values */ 2303 writel(0x27, qmp->dp_tx + cfg->regs[QPHY_TX_TX_DRV_LVL]); 2304 writel(0x27, qmp->dp_tx2 + cfg->regs[QPHY_TX_TX_DRV_LVL]); 2305 2306 writel(0x20, qmp->dp_tx + cfg->regs[QPHY_TX_TX_EMP_POST1_LVL]); 2307 writel(0x20, qmp->dp_tx2 + cfg->regs[QPHY_TX_TX_EMP_POST1_LVL]); 2308 2309 qmp_combo_configure_dp_swing(qmp); 2310} 2311 2312static int qmp_v456_configure_dp_phy(struct qmp_combo *qmp) 2313{ 2314 const struct qmp_phy_cfg *cfg = qmp->cfg; 2315 u32 status; 2316 int ret; 2317 2318 writel(0x0f, qmp->dp_dp_phy + QSERDES_DP_PHY_CFG_1); 2319 2320 qmp_combo_configure_dp_mode(qmp); 2321 2322 writel(0x13, qmp->dp_dp_phy + QSERDES_DP_PHY_AUX_CFG1); 2323 writel(0xa4, qmp->dp_dp_phy + QSERDES_DP_PHY_AUX_CFG2); 2324 2325 writel(0x05, qmp->dp_dp_phy + QSERDES_V4_DP_PHY_TX0_TX1_LANE_CTL); 2326 writel(0x05, qmp->dp_dp_phy + QSERDES_V4_DP_PHY_TX2_TX3_LANE_CTL); 2327 2328 ret = qmp_combo_configure_dp_clocks(qmp); 2329 if (ret) 2330 return ret; 2331 2332 writel(0x01, qmp->dp_dp_phy + QSERDES_DP_PHY_CFG); 2333 writel(0x05, qmp->dp_dp_phy + QSERDES_DP_PHY_CFG); 2334 writel(0x01, qmp->dp_dp_phy + QSERDES_DP_PHY_CFG); 2335 writel(0x09, qmp->dp_dp_phy + QSERDES_DP_PHY_CFG); 2336 2337 writel(0x20, qmp->dp_serdes + cfg->regs[QPHY_COM_RESETSM_CNTRL]); 2338 2339 if (readl_poll_timeout(qmp->dp_serdes + cfg->regs[QPHY_COM_C_READY_STATUS], 2340 status, 2341 ((status & BIT(0)) > 0), 2342 500, 2343 10000)) 2344 return -ETIMEDOUT; 2345 2346 if (readl_poll_timeout(qmp->dp_serdes + cfg->regs[QPHY_COM_CMN_STATUS], 2347 status, 2348 ((status & BIT(0)) > 0), 2349 500, 2350 10000)) 2351 return -ETIMEDOUT; 2352 2353 if (readl_poll_timeout(qmp->dp_serdes + cfg->regs[QPHY_COM_CMN_STATUS], 2354 status, 2355 ((status & BIT(1)) > 0), 2356 500, 2357 10000)) 2358 return -ETIMEDOUT; 2359 2360 writel(0x19, qmp->dp_dp_phy + QSERDES_DP_PHY_CFG); 2361 2362 if (readl_poll_timeout(qmp->dp_dp_phy + cfg->regs[QPHY_DP_PHY_STATUS], 2363 status, 2364 ((status & BIT(0)) > 0), 2365 500, 2366 10000)) 2367 return -ETIMEDOUT; 2368 2369 if (readl_poll_timeout(qmp->dp_dp_phy + cfg->regs[QPHY_DP_PHY_STATUS], 2370 status, 2371 ((status & BIT(1)) > 0), 2372 500, 2373 10000)) 2374 return -ETIMEDOUT; 2375 2376 return 0; 2377} 2378 2379static int qmp_v4_configure_dp_phy(struct qmp_combo *qmp) 2380{ 2381 const struct qmp_phy_cfg *cfg = qmp->cfg; 2382 bool reverse = (qmp->orientation == TYPEC_ORIENTATION_REVERSE); 2383 const struct phy_configure_opts_dp *dp_opts = &qmp->dp_opts; 2384 u32 bias0_en, drvr0_en, bias1_en, drvr1_en; 2385 u32 status; 2386 int ret; 2387 2388 ret = qmp_v456_configure_dp_phy(qmp); 2389 if (ret < 0) 2390 return ret; 2391 2392 /* 2393 * At least for 7nm DP PHY this has to be done after enabling link 2394 * clock. 2395 */ 2396 2397 if (dp_opts->lanes == 1) { 2398 bias0_en = reverse ? 0x3e : 0x15; 2399 bias1_en = reverse ? 0x15 : 0x3e; 2400 drvr0_en = reverse ? 0x13 : 0x10; 2401 drvr1_en = reverse ? 0x10 : 0x13; 2402 } else if (dp_opts->lanes == 2) { 2403 bias0_en = reverse ? 0x3f : 0x15; 2404 bias1_en = reverse ? 0x15 : 0x3f; 2405 drvr0_en = 0x10; 2406 drvr1_en = 0x10; 2407 } else { 2408 bias0_en = 0x3f; 2409 bias1_en = 0x3f; 2410 drvr0_en = 0x10; 2411 drvr1_en = 0x10; 2412 } 2413 2414 writel(drvr0_en, qmp->dp_tx + cfg->regs[QPHY_TX_HIGHZ_DRVR_EN]); 2415 writel(bias0_en, qmp->dp_tx + cfg->regs[QPHY_TX_TRANSCEIVER_BIAS_EN]); 2416 writel(drvr1_en, qmp->dp_tx2 + cfg->regs[QPHY_TX_HIGHZ_DRVR_EN]); 2417 writel(bias1_en, qmp->dp_tx2 + cfg->regs[QPHY_TX_TRANSCEIVER_BIAS_EN]); 2418 2419 writel(0x18, qmp->dp_dp_phy + QSERDES_DP_PHY_CFG); 2420 udelay(2000); 2421 writel(0x19, qmp->dp_dp_phy + QSERDES_DP_PHY_CFG); 2422 2423 if (readl_poll_timeout(qmp->dp_dp_phy + cfg->regs[QPHY_DP_PHY_STATUS], 2424 status, 2425 ((status & BIT(1)) > 0), 2426 500, 2427 10000)) 2428 return -ETIMEDOUT; 2429 2430 writel(0x0a, qmp->dp_tx + cfg->regs[QPHY_TX_TX_POL_INV]); 2431 writel(0x0a, qmp->dp_tx2 + cfg->regs[QPHY_TX_TX_POL_INV]); 2432 2433 writel(0x27, qmp->dp_tx + cfg->regs[QPHY_TX_TX_DRV_LVL]); 2434 writel(0x27, qmp->dp_tx2 + cfg->regs[QPHY_TX_TX_DRV_LVL]); 2435 2436 writel(0x20, qmp->dp_tx + cfg->regs[QPHY_TX_TX_EMP_POST1_LVL]); 2437 writel(0x20, qmp->dp_tx2 + cfg->regs[QPHY_TX_TX_EMP_POST1_LVL]); 2438 2439 return 0; 2440 2441 return 0; 2442} 2443 2444/* 2445 * We need to calibrate the aux setting here as many times 2446 * as the caller tries 2447 */ 2448static int qmp_v4_calibrate_dp_phy(struct qmp_combo *qmp) 2449{ 2450 static const u8 cfg1_settings[] = { 0x20, 0x13, 0x23, 0x1d }; 2451 u8 val; 2452 2453 qmp->dp_aux_cfg++; 2454 qmp->dp_aux_cfg %= ARRAY_SIZE(cfg1_settings); 2455 val = cfg1_settings[qmp->dp_aux_cfg]; 2456 2457 writel(val, qmp->dp_dp_phy + QSERDES_DP_PHY_AUX_CFG1); 2458 2459 return 0; 2460} 2461 2462static int qmp_combo_dp_configure(struct phy *phy, union phy_configure_opts *opts) 2463{ 2464 const struct phy_configure_opts_dp *dp_opts = &opts->dp; 2465 struct qmp_combo *qmp = phy_get_drvdata(phy); 2466 const struct qmp_phy_cfg *cfg = qmp->cfg; 2467 2468 mutex_lock(&qmp->phy_mutex); 2469 2470 memcpy(&qmp->dp_opts, dp_opts, sizeof(*dp_opts)); 2471 if (qmp->dp_opts.set_voltages) { 2472 cfg->configure_dp_tx(qmp); 2473 qmp->dp_opts.set_voltages = 0; 2474 } 2475 2476 mutex_unlock(&qmp->phy_mutex); 2477 2478 return 0; 2479} 2480 2481static int qmp_combo_dp_calibrate(struct phy *phy) 2482{ 2483 struct qmp_combo *qmp = phy_get_drvdata(phy); 2484 const struct qmp_phy_cfg *cfg = qmp->cfg; 2485 int ret = 0; 2486 2487 mutex_lock(&qmp->phy_mutex); 2488 2489 if (cfg->calibrate_dp_phy) 2490 ret = cfg->calibrate_dp_phy(qmp); 2491 2492 mutex_unlock(&qmp->phy_mutex); 2493 2494 return ret; 2495} 2496 2497static int qmp_combo_com_init(struct qmp_combo *qmp, bool force) 2498{ 2499 const struct qmp_phy_cfg *cfg = qmp->cfg; 2500 void __iomem *com = qmp->com; 2501 int ret; 2502 u32 val; 2503 2504 if (!force && qmp->init_count++) 2505 return 0; 2506 2507 ret = regulator_bulk_enable(cfg->num_vregs, qmp->vregs); 2508 if (ret) { 2509 dev_err(qmp->dev, "failed to enable regulators, err=%d\n", ret); 2510 goto err_decrement_count; 2511 } 2512 2513 ret = reset_control_bulk_assert(cfg->num_resets, qmp->resets); 2514 if (ret) { 2515 dev_err(qmp->dev, "reset assert failed\n"); 2516 goto err_disable_regulators; 2517 } 2518 2519 ret = reset_control_bulk_deassert(cfg->num_resets, qmp->resets); 2520 if (ret) { 2521 dev_err(qmp->dev, "reset deassert failed\n"); 2522 goto err_disable_regulators; 2523 } 2524 2525 ret = clk_bulk_prepare_enable(qmp->num_clks, qmp->clks); 2526 if (ret) 2527 goto err_assert_reset; 2528 2529 qphy_setbits(com, QPHY_V3_DP_COM_POWER_DOWN_CTRL, SW_PWRDN); 2530 2531 /* override hardware control for reset of qmp phy */ 2532 qphy_setbits(com, QPHY_V3_DP_COM_RESET_OVRD_CTRL, 2533 SW_DPPHY_RESET_MUX | SW_DPPHY_RESET | 2534 SW_USB3PHY_RESET_MUX | SW_USB3PHY_RESET); 2535 2536 /* Use software based port select and switch on typec orientation */ 2537 val = SW_PORTSELECT_MUX; 2538 if (qmp->orientation == TYPEC_ORIENTATION_REVERSE) 2539 val |= SW_PORTSELECT_VAL; 2540 writel(val, com + QPHY_V3_DP_COM_TYPEC_CTRL); 2541 writel(USB3_MODE | DP_MODE, com + QPHY_V3_DP_COM_PHY_MODE_CTRL); 2542 2543 /* bring both QMP USB and QMP DP PHYs PCS block out of reset */ 2544 qphy_clrbits(com, QPHY_V3_DP_COM_RESET_OVRD_CTRL, 2545 SW_DPPHY_RESET_MUX | SW_DPPHY_RESET | 2546 SW_USB3PHY_RESET_MUX | SW_USB3PHY_RESET); 2547 2548 qphy_clrbits(com, QPHY_V3_DP_COM_SWI_CTRL, 0x03); 2549 qphy_clrbits(com, QPHY_V3_DP_COM_SW_RESET, SW_RESET); 2550 2551 qphy_setbits(qmp->pcs, cfg->regs[QPHY_PCS_POWER_DOWN_CONTROL], 2552 SW_PWRDN); 2553 2554 return 0; 2555 2556err_assert_reset: 2557 reset_control_bulk_assert(cfg->num_resets, qmp->resets); 2558err_disable_regulators: 2559 regulator_bulk_disable(cfg->num_vregs, qmp->vregs); 2560err_decrement_count: 2561 qmp->init_count--; 2562 2563 return ret; 2564} 2565 2566static int qmp_combo_com_exit(struct qmp_combo *qmp, bool force) 2567{ 2568 const struct qmp_phy_cfg *cfg = qmp->cfg; 2569 2570 if (!force && --qmp->init_count) 2571 return 0; 2572 2573 reset_control_bulk_assert(cfg->num_resets, qmp->resets); 2574 2575 clk_bulk_disable_unprepare(qmp->num_clks, qmp->clks); 2576 2577 regulator_bulk_disable(cfg->num_vregs, qmp->vregs); 2578 2579 return 0; 2580} 2581 2582static int qmp_combo_dp_init(struct phy *phy) 2583{ 2584 struct qmp_combo *qmp = phy_get_drvdata(phy); 2585 const struct qmp_phy_cfg *cfg = qmp->cfg; 2586 int ret; 2587 2588 mutex_lock(&qmp->phy_mutex); 2589 2590 ret = qmp_combo_com_init(qmp, false); 2591 if (ret) 2592 goto out_unlock; 2593 2594 cfg->dp_aux_init(qmp); 2595 2596 qmp->dp_init_count++; 2597 2598out_unlock: 2599 mutex_unlock(&qmp->phy_mutex); 2600 return ret; 2601} 2602 2603static int qmp_combo_dp_exit(struct phy *phy) 2604{ 2605 struct qmp_combo *qmp = phy_get_drvdata(phy); 2606 2607 mutex_lock(&qmp->phy_mutex); 2608 2609 qmp_combo_com_exit(qmp, false); 2610 2611 qmp->dp_init_count--; 2612 2613 mutex_unlock(&qmp->phy_mutex); 2614 2615 return 0; 2616} 2617 2618static int qmp_combo_dp_power_on(struct phy *phy) 2619{ 2620 struct qmp_combo *qmp = phy_get_drvdata(phy); 2621 const struct qmp_phy_cfg *cfg = qmp->cfg; 2622 void __iomem *tx = qmp->dp_tx; 2623 void __iomem *tx2 = qmp->dp_tx2; 2624 2625 mutex_lock(&qmp->phy_mutex); 2626 2627 qmp_combo_dp_serdes_init(qmp); 2628 2629 qmp_configure_lane(tx, cfg->dp_tx_tbl, cfg->dp_tx_tbl_num, 1); 2630 qmp_configure_lane(tx2, cfg->dp_tx_tbl, cfg->dp_tx_tbl_num, 2); 2631 2632 /* Configure special DP tx tunings */ 2633 cfg->configure_dp_tx(qmp); 2634 2635 /* Configure link rate, swing, etc. */ 2636 cfg->configure_dp_phy(qmp); 2637 2638 mutex_unlock(&qmp->phy_mutex); 2639 2640 return 0; 2641} 2642 2643static int qmp_combo_dp_power_off(struct phy *phy) 2644{ 2645 struct qmp_combo *qmp = phy_get_drvdata(phy); 2646 2647 mutex_lock(&qmp->phy_mutex); 2648 2649 /* Assert DP PHY power down */ 2650 writel(DP_PHY_PD_CTL_PSR_PWRDN, qmp->dp_dp_phy + QSERDES_DP_PHY_PD_CTL); 2651 2652 mutex_unlock(&qmp->phy_mutex); 2653 2654 return 0; 2655} 2656 2657static int qmp_combo_usb_power_on(struct phy *phy) 2658{ 2659 struct qmp_combo *qmp = phy_get_drvdata(phy); 2660 const struct qmp_phy_cfg *cfg = qmp->cfg; 2661 void __iomem *serdes = qmp->serdes; 2662 void __iomem *tx = qmp->tx; 2663 void __iomem *rx = qmp->rx; 2664 void __iomem *tx2 = qmp->tx2; 2665 void __iomem *rx2 = qmp->rx2; 2666 void __iomem *pcs = qmp->pcs; 2667 void __iomem *pcs_usb = qmp->pcs_usb; 2668 void __iomem *status; 2669 unsigned int val; 2670 int ret; 2671 2672 qmp_configure(serdes, cfg->serdes_tbl, cfg->serdes_tbl_num); 2673 2674 ret = clk_prepare_enable(qmp->pipe_clk); 2675 if (ret) { 2676 dev_err(qmp->dev, "pipe_clk enable failed err=%d\n", ret); 2677 return ret; 2678 } 2679 2680 /* Tx, Rx, and PCS configurations */ 2681 qmp_configure_lane(tx, cfg->tx_tbl, cfg->tx_tbl_num, 1); 2682 qmp_configure_lane(tx2, cfg->tx_tbl, cfg->tx_tbl_num, 2); 2683 2684 qmp_configure_lane(rx, cfg->rx_tbl, cfg->rx_tbl_num, 1); 2685 qmp_configure_lane(rx2, cfg->rx_tbl, cfg->rx_tbl_num, 2); 2686 2687 qmp_configure(pcs, cfg->pcs_tbl, cfg->pcs_tbl_num); 2688 2689 if (pcs_usb) 2690 qmp_configure(pcs_usb, cfg->pcs_usb_tbl, cfg->pcs_usb_tbl_num); 2691 2692 if (cfg->has_pwrdn_delay) 2693 usleep_range(10, 20); 2694 2695 /* Pull PHY out of reset state */ 2696 qphy_clrbits(pcs, cfg->regs[QPHY_SW_RESET], SW_RESET); 2697 2698 /* start SerDes and Phy-Coding-Sublayer */ 2699 qphy_setbits(pcs, cfg->regs[QPHY_START_CTRL], SERDES_START | PCS_START); 2700 2701 status = pcs + cfg->regs[QPHY_PCS_STATUS]; 2702 ret = readl_poll_timeout(status, val, !(val & PHYSTATUS), 200, 2703 PHY_INIT_COMPLETE_TIMEOUT); 2704 if (ret) { 2705 dev_err(qmp->dev, "phy initialization timed-out\n"); 2706 goto err_disable_pipe_clk; 2707 } 2708 2709 return 0; 2710 2711err_disable_pipe_clk: 2712 clk_disable_unprepare(qmp->pipe_clk); 2713 2714 return ret; 2715} 2716 2717static int qmp_combo_usb_power_off(struct phy *phy) 2718{ 2719 struct qmp_combo *qmp = phy_get_drvdata(phy); 2720 const struct qmp_phy_cfg *cfg = qmp->cfg; 2721 2722 clk_disable_unprepare(qmp->pipe_clk); 2723 2724 /* PHY reset */ 2725 qphy_setbits(qmp->pcs, cfg->regs[QPHY_SW_RESET], SW_RESET); 2726 2727 /* stop SerDes and Phy-Coding-Sublayer */ 2728 qphy_clrbits(qmp->pcs, cfg->regs[QPHY_START_CTRL], 2729 SERDES_START | PCS_START); 2730 2731 /* Put PHY into POWER DOWN state: active low */ 2732 qphy_clrbits(qmp->pcs, cfg->regs[QPHY_PCS_POWER_DOWN_CONTROL], 2733 SW_PWRDN); 2734 2735 return 0; 2736} 2737 2738static int qmp_combo_usb_init(struct phy *phy) 2739{ 2740 struct qmp_combo *qmp = phy_get_drvdata(phy); 2741 int ret; 2742 2743 mutex_lock(&qmp->phy_mutex); 2744 ret = qmp_combo_com_init(qmp, false); 2745 if (ret) 2746 goto out_unlock; 2747 2748 ret = qmp_combo_usb_power_on(phy); 2749 if (ret) { 2750 qmp_combo_com_exit(qmp, false); 2751 goto out_unlock; 2752 } 2753 2754 qmp->usb_init_count++; 2755 2756out_unlock: 2757 mutex_unlock(&qmp->phy_mutex); 2758 return ret; 2759} 2760 2761static int qmp_combo_usb_exit(struct phy *phy) 2762{ 2763 struct qmp_combo *qmp = phy_get_drvdata(phy); 2764 int ret; 2765 2766 mutex_lock(&qmp->phy_mutex); 2767 ret = qmp_combo_usb_power_off(phy); 2768 if (ret) 2769 goto out_unlock; 2770 2771 ret = qmp_combo_com_exit(qmp, false); 2772 if (ret) 2773 goto out_unlock; 2774 2775 qmp->usb_init_count--; 2776 2777out_unlock: 2778 mutex_unlock(&qmp->phy_mutex); 2779 return ret; 2780} 2781 2782static int qmp_combo_usb_set_mode(struct phy *phy, enum phy_mode mode, int submode) 2783{ 2784 struct qmp_combo *qmp = phy_get_drvdata(phy); 2785 2786 qmp->mode = mode; 2787 2788 return 0; 2789} 2790 2791static const struct phy_ops qmp_combo_usb_phy_ops = { 2792 .init = qmp_combo_usb_init, 2793 .exit = qmp_combo_usb_exit, 2794 .set_mode = qmp_combo_usb_set_mode, 2795 .owner = THIS_MODULE, 2796}; 2797 2798static const struct phy_ops qmp_combo_dp_phy_ops = { 2799 .init = qmp_combo_dp_init, 2800 .configure = qmp_combo_dp_configure, 2801 .power_on = qmp_combo_dp_power_on, 2802 .calibrate = qmp_combo_dp_calibrate, 2803 .power_off = qmp_combo_dp_power_off, 2804 .exit = qmp_combo_dp_exit, 2805 .owner = THIS_MODULE, 2806}; 2807 2808static void qmp_combo_enable_autonomous_mode(struct qmp_combo *qmp) 2809{ 2810 const struct qmp_phy_cfg *cfg = qmp->cfg; 2811 void __iomem *pcs_usb = qmp->pcs_usb ?: qmp->pcs; 2812 void __iomem *pcs_misc = qmp->pcs_misc; 2813 u32 intr_mask; 2814 2815 if (qmp->mode == PHY_MODE_USB_HOST_SS || 2816 qmp->mode == PHY_MODE_USB_DEVICE_SS) 2817 intr_mask = ARCVR_DTCT_EN | ALFPS_DTCT_EN; 2818 else 2819 intr_mask = ARCVR_DTCT_EN | ARCVR_DTCT_EVENT_SEL; 2820 2821 /* Clear any pending interrupts status */ 2822 qphy_setbits(pcs_usb, cfg->regs[QPHY_PCS_LFPS_RXTERM_IRQ_CLEAR], IRQ_CLEAR); 2823 /* Writing 1 followed by 0 clears the interrupt */ 2824 qphy_clrbits(pcs_usb, cfg->regs[QPHY_PCS_LFPS_RXTERM_IRQ_CLEAR], IRQ_CLEAR); 2825 2826 qphy_clrbits(pcs_usb, cfg->regs[QPHY_PCS_AUTONOMOUS_MODE_CTRL], 2827 ARCVR_DTCT_EN | ALFPS_DTCT_EN | ARCVR_DTCT_EVENT_SEL); 2828 2829 /* Enable required PHY autonomous mode interrupts */ 2830 qphy_setbits(pcs_usb, cfg->regs[QPHY_PCS_AUTONOMOUS_MODE_CTRL], intr_mask); 2831 2832 /* Enable i/o clamp_n for autonomous mode */ 2833 if (pcs_misc) 2834 qphy_clrbits(pcs_misc, QPHY_V3_PCS_MISC_CLAMP_ENABLE, CLAMP_EN); 2835} 2836 2837static void qmp_combo_disable_autonomous_mode(struct qmp_combo *qmp) 2838{ 2839 const struct qmp_phy_cfg *cfg = qmp->cfg; 2840 void __iomem *pcs_usb = qmp->pcs_usb ?: qmp->pcs; 2841 void __iomem *pcs_misc = qmp->pcs_misc; 2842 2843 /* Disable i/o clamp_n on resume for normal mode */ 2844 if (pcs_misc) 2845 qphy_setbits(pcs_misc, QPHY_V3_PCS_MISC_CLAMP_ENABLE, CLAMP_EN); 2846 2847 qphy_clrbits(pcs_usb, cfg->regs[QPHY_PCS_AUTONOMOUS_MODE_CTRL], 2848 ARCVR_DTCT_EN | ARCVR_DTCT_EVENT_SEL | ALFPS_DTCT_EN); 2849 2850 qphy_setbits(pcs_usb, cfg->regs[QPHY_PCS_LFPS_RXTERM_IRQ_CLEAR], IRQ_CLEAR); 2851 /* Writing 1 followed by 0 clears the interrupt */ 2852 qphy_clrbits(pcs_usb, cfg->regs[QPHY_PCS_LFPS_RXTERM_IRQ_CLEAR], IRQ_CLEAR); 2853} 2854 2855static int __maybe_unused qmp_combo_runtime_suspend(struct device *dev) 2856{ 2857 struct qmp_combo *qmp = dev_get_drvdata(dev); 2858 2859 dev_vdbg(dev, "Suspending QMP phy, mode:%d\n", qmp->mode); 2860 2861 if (!qmp->init_count) { 2862 dev_vdbg(dev, "PHY not initialized, bailing out\n"); 2863 return 0; 2864 } 2865 2866 qmp_combo_enable_autonomous_mode(qmp); 2867 2868 clk_disable_unprepare(qmp->pipe_clk); 2869 clk_bulk_disable_unprepare(qmp->num_clks, qmp->clks); 2870 2871 return 0; 2872} 2873 2874static int __maybe_unused qmp_combo_runtime_resume(struct device *dev) 2875{ 2876 struct qmp_combo *qmp = dev_get_drvdata(dev); 2877 int ret = 0; 2878 2879 dev_vdbg(dev, "Resuming QMP phy, mode:%d\n", qmp->mode); 2880 2881 if (!qmp->init_count) { 2882 dev_vdbg(dev, "PHY not initialized, bailing out\n"); 2883 return 0; 2884 } 2885 2886 ret = clk_bulk_prepare_enable(qmp->num_clks, qmp->clks); 2887 if (ret) 2888 return ret; 2889 2890 ret = clk_prepare_enable(qmp->pipe_clk); 2891 if (ret) { 2892 dev_err(dev, "pipe_clk enable failed, err=%d\n", ret); 2893 clk_bulk_disable_unprepare(qmp->num_clks, qmp->clks); 2894 return ret; 2895 } 2896 2897 qmp_combo_disable_autonomous_mode(qmp); 2898 2899 return 0; 2900} 2901 2902static const struct dev_pm_ops qmp_combo_pm_ops = { 2903 SET_RUNTIME_PM_OPS(qmp_combo_runtime_suspend, 2904 qmp_combo_runtime_resume, NULL) 2905}; 2906 2907static int qmp_combo_vreg_init(struct qmp_combo *qmp) 2908{ 2909 const struct qmp_phy_cfg *cfg = qmp->cfg; 2910 struct device *dev = qmp->dev; 2911 int num = cfg->num_vregs; 2912 int ret, i; 2913 2914 qmp->vregs = devm_kcalloc(dev, num, sizeof(*qmp->vregs), GFP_KERNEL); 2915 if (!qmp->vregs) 2916 return -ENOMEM; 2917 2918 for (i = 0; i < num; i++) 2919 qmp->vregs[i].supply = cfg->vreg_list[i].name; 2920 2921 ret = devm_regulator_bulk_get(dev, num, qmp->vregs); 2922 if (ret) { 2923 dev_err(dev, "failed at devm_regulator_bulk_get\n"); 2924 return ret; 2925 } 2926 2927 for (i = 0; i < num; i++) { 2928 ret = regulator_set_load(qmp->vregs[i].consumer, 2929 cfg->vreg_list[i].enable_load); 2930 if (ret) { 2931 dev_err(dev, "failed to set load at %s\n", 2932 qmp->vregs[i].supply); 2933 return ret; 2934 } 2935 } 2936 2937 return 0; 2938} 2939 2940static int qmp_combo_reset_init(struct qmp_combo *qmp) 2941{ 2942 const struct qmp_phy_cfg *cfg = qmp->cfg; 2943 struct device *dev = qmp->dev; 2944 int i; 2945 int ret; 2946 2947 qmp->resets = devm_kcalloc(dev, cfg->num_resets, 2948 sizeof(*qmp->resets), GFP_KERNEL); 2949 if (!qmp->resets) 2950 return -ENOMEM; 2951 2952 for (i = 0; i < cfg->num_resets; i++) 2953 qmp->resets[i].id = cfg->reset_list[i]; 2954 2955 ret = devm_reset_control_bulk_get_exclusive(dev, cfg->num_resets, qmp->resets); 2956 if (ret) 2957 return dev_err_probe(dev, ret, "failed to get resets\n"); 2958 2959 return 0; 2960} 2961 2962static int qmp_combo_clk_init(struct qmp_combo *qmp) 2963{ 2964 struct device *dev = qmp->dev; 2965 int num = ARRAY_SIZE(qmp_combo_phy_clk_l); 2966 int i; 2967 2968 qmp->clks = devm_kcalloc(dev, num, sizeof(*qmp->clks), GFP_KERNEL); 2969 if (!qmp->clks) 2970 return -ENOMEM; 2971 2972 for (i = 0; i < num; i++) 2973 qmp->clks[i].id = qmp_combo_phy_clk_l[i]; 2974 2975 qmp->num_clks = num; 2976 2977 return devm_clk_bulk_get_optional(dev, num, qmp->clks); 2978} 2979 2980static void phy_clk_release_provider(void *res) 2981{ 2982 of_clk_del_provider(res); 2983} 2984 2985/* 2986 * Register a fixed rate pipe clock. 2987 * 2988 * The <s>_pipe_clksrc generated by PHY goes to the GCC that gate 2989 * controls it. The <s>_pipe_clk coming out of the GCC is requested 2990 * by the PHY driver for its operations. 2991 * We register the <s>_pipe_clksrc here. The gcc driver takes care 2992 * of assigning this <s>_pipe_clksrc as parent to <s>_pipe_clk. 2993 * Below picture shows this relationship. 2994 * 2995 * +---------------+ 2996 * | PHY block |<<---------------------------------------+ 2997 * | | | 2998 * | +-------+ | +-----+ | 2999 * I/P---^-->| PLL |---^--->pipe_clksrc--->| GCC |--->pipe_clk---+ 3000 * clk | +-------+ | +-----+ 3001 * +---------------+ 3002 */ 3003static int phy_pipe_clk_register(struct qmp_combo *qmp, struct device_node *np) 3004{ 3005 struct clk_fixed_rate *fixed = &qmp->pipe_clk_fixed; 3006 struct clk_init_data init = { }; 3007 char name[64]; 3008 3009 snprintf(name, sizeof(name), "%s::pipe_clk", dev_name(qmp->dev)); 3010 init.name = name; 3011 init.ops = &clk_fixed_rate_ops; 3012 3013 /* controllers using QMP phys use 125MHz pipe clock interface */ 3014 fixed->fixed_rate = 125000000; 3015 fixed->hw.init = &init; 3016 3017 return devm_clk_hw_register(qmp->dev, &fixed->hw); 3018} 3019 3020/* 3021 * Display Port PLL driver block diagram for branch clocks 3022 * 3023 * +------------------------------+ 3024 * | DP_VCO_CLK | 3025 * | | 3026 * | +-------------------+ | 3027 * | | (DP PLL/VCO) | | 3028 * | +---------+---------+ | 3029 * | v | 3030 * | +----------+-----------+ | 3031 * | | hsclk_divsel_clk_src | | 3032 * | +----------+-----------+ | 3033 * +------------------------------+ 3034 * | 3035 * +---------<---------v------------>----------+ 3036 * | | 3037 * +--------v----------------+ | 3038 * | dp_phy_pll_link_clk | | 3039 * | link_clk | | 3040 * +--------+----------------+ | 3041 * | | 3042 * | | 3043 * v v 3044 * Input to DISPCC block | 3045 * for link clk, crypto clk | 3046 * and interface clock | 3047 * | 3048 * | 3049 * +--------<------------+-----------------+---<---+ 3050 * | | | 3051 * +----v---------+ +--------v-----+ +--------v------+ 3052 * | vco_divided | | vco_divided | | vco_divided | 3053 * | _clk_src | | _clk_src | | _clk_src | 3054 * | | | | | | 3055 * |divsel_six | | divsel_two | | divsel_four | 3056 * +-------+------+ +-----+--------+ +--------+------+ 3057 * | | | 3058 * v---->----------v-------------<------v 3059 * | 3060 * +----------+-----------------+ 3061 * | dp_phy_pll_vco_div_clk | 3062 * +---------+------------------+ 3063 * | 3064 * v 3065 * Input to DISPCC block 3066 * for DP pixel clock 3067 * 3068 */ 3069static int qmp_dp_pixel_clk_determine_rate(struct clk_hw *hw, struct clk_rate_request *req) 3070{ 3071 switch (req->rate) { 3072 case 1620000000UL / 2: 3073 case 2700000000UL / 2: 3074 /* 5.4 and 8.1 GHz are same link rate as 2.7GHz, i.e. div 4 and div 6 */ 3075 return 0; 3076 default: 3077 return -EINVAL; 3078 } 3079} 3080 3081static unsigned long qmp_dp_pixel_clk_recalc_rate(struct clk_hw *hw, unsigned long parent_rate) 3082{ 3083 const struct qmp_combo *qmp; 3084 const struct phy_configure_opts_dp *dp_opts; 3085 3086 qmp = container_of(hw, struct qmp_combo, dp_pixel_hw); 3087 dp_opts = &qmp->dp_opts; 3088 3089 switch (dp_opts->link_rate) { 3090 case 1620: 3091 return 1620000000UL / 2; 3092 case 2700: 3093 return 2700000000UL / 2; 3094 case 5400: 3095 return 5400000000UL / 4; 3096 case 8100: 3097 return 8100000000UL / 6; 3098 default: 3099 return 0; 3100 } 3101} 3102 3103static const struct clk_ops qmp_dp_pixel_clk_ops = { 3104 .determine_rate = qmp_dp_pixel_clk_determine_rate, 3105 .recalc_rate = qmp_dp_pixel_clk_recalc_rate, 3106}; 3107 3108static int qmp_dp_link_clk_determine_rate(struct clk_hw *hw, struct clk_rate_request *req) 3109{ 3110 switch (req->rate) { 3111 case 162000000: 3112 case 270000000: 3113 case 540000000: 3114 case 810000000: 3115 return 0; 3116 default: 3117 return -EINVAL; 3118 } 3119} 3120 3121static unsigned long qmp_dp_link_clk_recalc_rate(struct clk_hw *hw, unsigned long parent_rate) 3122{ 3123 const struct qmp_combo *qmp; 3124 const struct phy_configure_opts_dp *dp_opts; 3125 3126 qmp = container_of(hw, struct qmp_combo, dp_link_hw); 3127 dp_opts = &qmp->dp_opts; 3128 3129 switch (dp_opts->link_rate) { 3130 case 1620: 3131 case 2700: 3132 case 5400: 3133 case 8100: 3134 return dp_opts->link_rate * 100000; 3135 default: 3136 return 0; 3137 } 3138} 3139 3140static const struct clk_ops qmp_dp_link_clk_ops = { 3141 .determine_rate = qmp_dp_link_clk_determine_rate, 3142 .recalc_rate = qmp_dp_link_clk_recalc_rate, 3143}; 3144 3145static struct clk_hw *qmp_dp_clks_hw_get(struct of_phandle_args *clkspec, void *data) 3146{ 3147 struct qmp_combo *qmp = data; 3148 unsigned int idx = clkspec->args[0]; 3149 3150 if (idx >= 2) { 3151 pr_err("%s: invalid index %u\n", __func__, idx); 3152 return ERR_PTR(-EINVAL); 3153 } 3154 3155 if (idx == 0) 3156 return &qmp->dp_link_hw; 3157 3158 return &qmp->dp_pixel_hw; 3159} 3160 3161static int phy_dp_clks_register(struct qmp_combo *qmp, struct device_node *np) 3162{ 3163 struct clk_init_data init = { }; 3164 char name[64]; 3165 int ret; 3166 3167 snprintf(name, sizeof(name), "%s::link_clk", dev_name(qmp->dev)); 3168 init.ops = &qmp_dp_link_clk_ops; 3169 init.name = name; 3170 qmp->dp_link_hw.init = &init; 3171 ret = devm_clk_hw_register(qmp->dev, &qmp->dp_link_hw); 3172 if (ret) 3173 return ret; 3174 3175 snprintf(name, sizeof(name), "%s::vco_div_clk", dev_name(qmp->dev)); 3176 init.ops = &qmp_dp_pixel_clk_ops; 3177 init.name = name; 3178 qmp->dp_pixel_hw.init = &init; 3179 ret = devm_clk_hw_register(qmp->dev, &qmp->dp_pixel_hw); 3180 if (ret) 3181 return ret; 3182 3183 return 0; 3184} 3185 3186static struct clk_hw *qmp_combo_clk_hw_get(struct of_phandle_args *clkspec, void *data) 3187{ 3188 struct qmp_combo *qmp = data; 3189 3190 switch (clkspec->args[0]) { 3191 case QMP_USB43DP_USB3_PIPE_CLK: 3192 return &qmp->pipe_clk_fixed.hw; 3193 case QMP_USB43DP_DP_LINK_CLK: 3194 return &qmp->dp_link_hw; 3195 case QMP_USB43DP_DP_VCO_DIV_CLK: 3196 return &qmp->dp_pixel_hw; 3197 } 3198 3199 return ERR_PTR(-EINVAL); 3200} 3201 3202static int qmp_combo_register_clocks(struct qmp_combo *qmp, struct device_node *usb_np, 3203 struct device_node *dp_np) 3204{ 3205 int ret; 3206 3207 ret = phy_pipe_clk_register(qmp, usb_np); 3208 if (ret) 3209 return ret; 3210 3211 ret = phy_dp_clks_register(qmp, dp_np); 3212 if (ret) 3213 return ret; 3214 3215 /* 3216 * Register a single provider for bindings without child nodes. 3217 */ 3218 if (usb_np == qmp->dev->of_node) 3219 return devm_of_clk_add_hw_provider(qmp->dev, qmp_combo_clk_hw_get, qmp); 3220 3221 /* 3222 * Register multiple providers for legacy bindings with child nodes. 3223 */ 3224 ret = of_clk_add_hw_provider(usb_np, of_clk_hw_simple_get, 3225 &qmp->pipe_clk_fixed.hw); 3226 if (ret) 3227 return ret; 3228 3229 /* 3230 * Roll a devm action because the clock provider is the child node, but 3231 * the child node is not actually a device. 3232 */ 3233 ret = devm_add_action_or_reset(qmp->dev, phy_clk_release_provider, usb_np); 3234 if (ret) 3235 return ret; 3236 3237 ret = of_clk_add_hw_provider(dp_np, qmp_dp_clks_hw_get, qmp); 3238 if (ret) 3239 return ret; 3240 3241 return devm_add_action_or_reset(qmp->dev, phy_clk_release_provider, dp_np); 3242} 3243 3244#if IS_ENABLED(CONFIG_TYPEC) 3245static int qmp_combo_typec_switch_set(struct typec_switch_dev *sw, 3246 enum typec_orientation orientation) 3247{ 3248 struct qmp_combo *qmp = typec_switch_get_drvdata(sw); 3249 const struct qmp_phy_cfg *cfg = qmp->cfg; 3250 3251 if (orientation == qmp->orientation || orientation == TYPEC_ORIENTATION_NONE) 3252 return 0; 3253 3254 mutex_lock(&qmp->phy_mutex); 3255 qmp->orientation = orientation; 3256 3257 if (qmp->init_count) { 3258 if (qmp->usb_init_count) 3259 qmp_combo_usb_power_off(qmp->usb_phy); 3260 qmp_combo_com_exit(qmp, true); 3261 3262 qmp_combo_com_init(qmp, true); 3263 if (qmp->usb_init_count) 3264 qmp_combo_usb_power_on(qmp->usb_phy); 3265 if (qmp->dp_init_count) 3266 cfg->dp_aux_init(qmp); 3267 } 3268 mutex_unlock(&qmp->phy_mutex); 3269 3270 return 0; 3271} 3272 3273static void qmp_combo_typec_unregister(void *data) 3274{ 3275 struct qmp_combo *qmp = data; 3276 3277 typec_switch_unregister(qmp->sw); 3278} 3279 3280static int qmp_combo_typec_switch_register(struct qmp_combo *qmp) 3281{ 3282 struct typec_switch_desc sw_desc = {}; 3283 struct device *dev = qmp->dev; 3284 3285 sw_desc.drvdata = qmp; 3286 sw_desc.fwnode = dev->fwnode; 3287 sw_desc.set = qmp_combo_typec_switch_set; 3288 qmp->sw = typec_switch_register(dev, &sw_desc); 3289 if (IS_ERR(qmp->sw)) { 3290 dev_err(dev, "Unable to register typec switch: %pe\n", qmp->sw); 3291 return PTR_ERR(qmp->sw); 3292 } 3293 3294 return devm_add_action_or_reset(dev, qmp_combo_typec_unregister, qmp); 3295} 3296#else 3297static int qmp_combo_typec_switch_register(struct qmp_combo *qmp) 3298{ 3299 return 0; 3300} 3301#endif 3302 3303static int qmp_combo_parse_dt_lecacy_dp(struct qmp_combo *qmp, struct device_node *np) 3304{ 3305 struct device *dev = qmp->dev; 3306 3307 /* 3308 * Get memory resources from the DP child node: 3309 * Resources are indexed as: tx -> 0; rx -> 1; pcs -> 2; 3310 * tx2 -> 3; rx2 -> 4 3311 * 3312 * Note that only tx/tx2 and pcs (dp_phy) are used by the DP 3313 * implementation. 3314 */ 3315 qmp->dp_tx = devm_of_iomap(dev, np, 0, NULL); 3316 if (IS_ERR(qmp->dp_tx)) 3317 return PTR_ERR(qmp->dp_tx); 3318 3319 qmp->dp_dp_phy = devm_of_iomap(dev, np, 2, NULL); 3320 if (IS_ERR(qmp->dp_dp_phy)) 3321 return PTR_ERR(qmp->dp_dp_phy); 3322 3323 qmp->dp_tx2 = devm_of_iomap(dev, np, 3, NULL); 3324 if (IS_ERR(qmp->dp_tx2)) 3325 return PTR_ERR(qmp->dp_tx2); 3326 3327 return 0; 3328} 3329 3330static int qmp_combo_parse_dt_lecacy_usb(struct qmp_combo *qmp, struct device_node *np) 3331{ 3332 const struct qmp_phy_cfg *cfg = qmp->cfg; 3333 struct device *dev = qmp->dev; 3334 3335 /* 3336 * Get memory resources from the USB child node: 3337 * Resources are indexed as: tx -> 0; rx -> 1; pcs -> 2; 3338 * tx2 -> 3; rx2 -> 4; pcs_misc (optional) -> 5 3339 */ 3340 qmp->tx = devm_of_iomap(dev, np, 0, NULL); 3341 if (IS_ERR(qmp->tx)) 3342 return PTR_ERR(qmp->tx); 3343 3344 qmp->rx = devm_of_iomap(dev, np, 1, NULL); 3345 if (IS_ERR(qmp->rx)) 3346 return PTR_ERR(qmp->rx); 3347 3348 qmp->pcs = devm_of_iomap(dev, np, 2, NULL); 3349 if (IS_ERR(qmp->pcs)) 3350 return PTR_ERR(qmp->pcs); 3351 3352 if (cfg->pcs_usb_offset) 3353 qmp->pcs_usb = qmp->pcs + cfg->pcs_usb_offset; 3354 3355 qmp->tx2 = devm_of_iomap(dev, np, 3, NULL); 3356 if (IS_ERR(qmp->tx2)) 3357 return PTR_ERR(qmp->tx2); 3358 3359 qmp->rx2 = devm_of_iomap(dev, np, 4, NULL); 3360 if (IS_ERR(qmp->rx2)) 3361 return PTR_ERR(qmp->rx2); 3362 3363 qmp->pcs_misc = devm_of_iomap(dev, np, 5, NULL); 3364 if (IS_ERR(qmp->pcs_misc)) { 3365 dev_vdbg(dev, "PHY pcs_misc-reg not used\n"); 3366 qmp->pcs_misc = NULL; 3367 } 3368 3369 qmp->pipe_clk = devm_get_clk_from_child(dev, np, NULL); 3370 if (IS_ERR(qmp->pipe_clk)) { 3371 return dev_err_probe(dev, PTR_ERR(qmp->pipe_clk), 3372 "failed to get pipe clock\n"); 3373 } 3374 3375 return 0; 3376} 3377 3378static int qmp_combo_parse_dt_legacy(struct qmp_combo *qmp, struct device_node *usb_np, 3379 struct device_node *dp_np) 3380{ 3381 struct platform_device *pdev = to_platform_device(qmp->dev); 3382 int ret; 3383 3384 qmp->serdes = devm_platform_ioremap_resource(pdev, 0); 3385 if (IS_ERR(qmp->serdes)) 3386 return PTR_ERR(qmp->serdes); 3387 3388 qmp->com = devm_platform_ioremap_resource(pdev, 1); 3389 if (IS_ERR(qmp->com)) 3390 return PTR_ERR(qmp->com); 3391 3392 qmp->dp_serdes = devm_platform_ioremap_resource(pdev, 2); 3393 if (IS_ERR(qmp->dp_serdes)) 3394 return PTR_ERR(qmp->dp_serdes); 3395 3396 ret = qmp_combo_parse_dt_lecacy_usb(qmp, usb_np); 3397 if (ret) 3398 return ret; 3399 3400 ret = qmp_combo_parse_dt_lecacy_dp(qmp, dp_np); 3401 if (ret) 3402 return ret; 3403 3404 ret = devm_clk_bulk_get_all(qmp->dev, &qmp->clks); 3405 if (ret < 0) 3406 return ret; 3407 3408 qmp->num_clks = ret; 3409 3410 return 0; 3411} 3412 3413static int qmp_combo_parse_dt(struct qmp_combo *qmp) 3414{ 3415 struct platform_device *pdev = to_platform_device(qmp->dev); 3416 const struct qmp_phy_cfg *cfg = qmp->cfg; 3417 const struct qmp_combo_offsets *offs = cfg->offsets; 3418 struct device *dev = qmp->dev; 3419 void __iomem *base; 3420 int ret; 3421 3422 if (!offs) 3423 return -EINVAL; 3424 3425 base = devm_platform_ioremap_resource(pdev, 0); 3426 if (IS_ERR(base)) 3427 return PTR_ERR(base); 3428 3429 qmp->com = base + offs->com; 3430 qmp->tx = base + offs->txa; 3431 qmp->rx = base + offs->rxa; 3432 qmp->tx2 = base + offs->txb; 3433 qmp->rx2 = base + offs->rxb; 3434 3435 qmp->serdes = base + offs->usb3_serdes; 3436 qmp->pcs_misc = base + offs->usb3_pcs_misc; 3437 qmp->pcs = base + offs->usb3_pcs; 3438 qmp->pcs_usb = base + offs->usb3_pcs_usb; 3439 3440 qmp->dp_serdes = base + offs->dp_serdes; 3441 if (offs->dp_txa) { 3442 qmp->dp_tx = base + offs->dp_txa; 3443 qmp->dp_tx2 = base + offs->dp_txb; 3444 } else { 3445 qmp->dp_tx = base + offs->txa; 3446 qmp->dp_tx2 = base + offs->txb; 3447 } 3448 qmp->dp_dp_phy = base + offs->dp_dp_phy; 3449 3450 ret = qmp_combo_clk_init(qmp); 3451 if (ret) 3452 return ret; 3453 3454 qmp->pipe_clk = devm_clk_get(dev, "usb3_pipe"); 3455 if (IS_ERR(qmp->pipe_clk)) { 3456 return dev_err_probe(dev, PTR_ERR(qmp->pipe_clk), 3457 "failed to get usb3_pipe clock\n"); 3458 } 3459 3460 return 0; 3461} 3462 3463static struct phy *qmp_combo_phy_xlate(struct device *dev, const struct of_phandle_args *args) 3464{ 3465 struct qmp_combo *qmp = dev_get_drvdata(dev); 3466 3467 if (args->args_count == 0) 3468 return ERR_PTR(-EINVAL); 3469 3470 switch (args->args[0]) { 3471 case QMP_USB43DP_USB3_PHY: 3472 return qmp->usb_phy; 3473 case QMP_USB43DP_DP_PHY: 3474 return qmp->dp_phy; 3475 } 3476 3477 return ERR_PTR(-EINVAL); 3478} 3479 3480static int qmp_combo_probe(struct platform_device *pdev) 3481{ 3482 struct qmp_combo *qmp; 3483 struct device *dev = &pdev->dev; 3484 struct device_node *dp_np, *usb_np; 3485 struct phy_provider *phy_provider; 3486 int ret; 3487 3488 qmp = devm_kzalloc(dev, sizeof(*qmp), GFP_KERNEL); 3489 if (!qmp) 3490 return -ENOMEM; 3491 3492 qmp->dev = dev; 3493 3494 qmp->orientation = TYPEC_ORIENTATION_NORMAL; 3495 3496 qmp->cfg = of_device_get_match_data(dev); 3497 if (!qmp->cfg) 3498 return -EINVAL; 3499 3500 mutex_init(&qmp->phy_mutex); 3501 3502 ret = qmp_combo_reset_init(qmp); 3503 if (ret) 3504 return ret; 3505 3506 ret = qmp_combo_vreg_init(qmp); 3507 if (ret) 3508 return ret; 3509 3510 /* Check for legacy binding with child nodes. */ 3511 usb_np = of_get_child_by_name(dev->of_node, "usb3-phy"); 3512 if (usb_np) { 3513 dp_np = of_get_child_by_name(dev->of_node, "dp-phy"); 3514 if (!dp_np) { 3515 of_node_put(usb_np); 3516 return -EINVAL; 3517 } 3518 3519 ret = qmp_combo_parse_dt_legacy(qmp, usb_np, dp_np); 3520 } else { 3521 usb_np = of_node_get(dev->of_node); 3522 dp_np = of_node_get(dev->of_node); 3523 3524 ret = qmp_combo_parse_dt(qmp); 3525 } 3526 if (ret) 3527 goto err_node_put; 3528 3529 ret = qmp_combo_typec_switch_register(qmp); 3530 if (ret) 3531 goto err_node_put; 3532 3533 ret = drm_aux_bridge_register(dev); 3534 if (ret) 3535 goto err_node_put; 3536 3537 pm_runtime_set_active(dev); 3538 ret = devm_pm_runtime_enable(dev); 3539 if (ret) 3540 goto err_node_put; 3541 /* 3542 * Prevent runtime pm from being ON by default. Users can enable 3543 * it using power/control in sysfs. 3544 */ 3545 pm_runtime_forbid(dev); 3546 3547 ret = qmp_combo_register_clocks(qmp, usb_np, dp_np); 3548 if (ret) 3549 goto err_node_put; 3550 3551 qmp->usb_phy = devm_phy_create(dev, usb_np, &qmp_combo_usb_phy_ops); 3552 if (IS_ERR(qmp->usb_phy)) { 3553 ret = PTR_ERR(qmp->usb_phy); 3554 dev_err(dev, "failed to create USB PHY: %d\n", ret); 3555 goto err_node_put; 3556 } 3557 3558 phy_set_drvdata(qmp->usb_phy, qmp); 3559 3560 qmp->dp_phy = devm_phy_create(dev, dp_np, &qmp_combo_dp_phy_ops); 3561 if (IS_ERR(qmp->dp_phy)) { 3562 ret = PTR_ERR(qmp->dp_phy); 3563 dev_err(dev, "failed to create DP PHY: %d\n", ret); 3564 goto err_node_put; 3565 } 3566 3567 phy_set_drvdata(qmp->dp_phy, qmp); 3568 3569 dev_set_drvdata(dev, qmp); 3570 3571 if (usb_np == dev->of_node) 3572 phy_provider = devm_of_phy_provider_register(dev, qmp_combo_phy_xlate); 3573 else 3574 phy_provider = devm_of_phy_provider_register(dev, of_phy_simple_xlate); 3575 3576 of_node_put(usb_np); 3577 of_node_put(dp_np); 3578 3579 return PTR_ERR_OR_ZERO(phy_provider); 3580 3581err_node_put: 3582 of_node_put(usb_np); 3583 of_node_put(dp_np); 3584 return ret; 3585} 3586 3587static const struct of_device_id qmp_combo_of_match_table[] = { 3588 { 3589 .compatible = "qcom,sc7180-qmp-usb3-dp-phy", 3590 .data = &sc7180_usb3dpphy_cfg, 3591 }, 3592 { 3593 .compatible = "qcom,sc7280-qmp-usb3-dp-phy", 3594 .data = &sm8250_usb3dpphy_cfg, 3595 }, 3596 { 3597 .compatible = "qcom,sc8180x-qmp-usb3-dp-phy", 3598 .data = &sc8180x_usb3dpphy_cfg, 3599 }, 3600 { 3601 .compatible = "qcom,sc8280xp-qmp-usb43dp-phy", 3602 .data = &sc8280xp_usb43dpphy_cfg, 3603 }, 3604 { 3605 .compatible = "qcom,sdm845-qmp-usb3-dp-phy", 3606 .data = &sdm845_usb3dpphy_cfg, 3607 }, 3608 { 3609 .compatible = "qcom,sm6350-qmp-usb3-dp-phy", 3610 .data = &sm6350_usb3dpphy_cfg, 3611 }, 3612 { 3613 .compatible = "qcom,sm8150-qmp-usb3-dp-phy", 3614 .data = &sc8180x_usb3dpphy_cfg, 3615 }, 3616 { 3617 .compatible = "qcom,sm8250-qmp-usb3-dp-phy", 3618 .data = &sm8250_usb3dpphy_cfg, 3619 }, 3620 { 3621 .compatible = "qcom,sm8350-qmp-usb3-dp-phy", 3622 .data = &sm8350_usb3dpphy_cfg, 3623 }, 3624 { 3625 .compatible = "qcom,sm8450-qmp-usb3-dp-phy", 3626 .data = &sm8350_usb3dpphy_cfg, 3627 }, 3628 { 3629 .compatible = "qcom,sm8550-qmp-usb3-dp-phy", 3630 .data = &sm8550_usb3dpphy_cfg, 3631 }, 3632 { 3633 .compatible = "qcom,sm8650-qmp-usb3-dp-phy", 3634 .data = &sm8550_usb3dpphy_cfg, 3635 }, 3636 { 3637 .compatible = "qcom,x1e80100-qmp-usb3-dp-phy", 3638 .data = &x1e80100_usb3dpphy_cfg, 3639 }, 3640 { } 3641}; 3642MODULE_DEVICE_TABLE(of, qmp_combo_of_match_table); 3643 3644static struct platform_driver qmp_combo_driver = { 3645 .probe = qmp_combo_probe, 3646 .driver = { 3647 .name = "qcom-qmp-combo-phy", 3648 .pm = &qmp_combo_pm_ops, 3649 .of_match_table = qmp_combo_of_match_table, 3650 }, 3651}; 3652 3653module_platform_driver(qmp_combo_driver); 3654 3655MODULE_AUTHOR("Vivek Gautam <vivek.gautam@codeaurora.org>"); 3656MODULE_DESCRIPTION("Qualcomm QMP USB+DP combo PHY driver"); 3657MODULE_LICENSE("GPL v2"); 3658