#
bb87e511 |
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15-Feb-2024 |
Ilpo Järvinen <ilpo.jarvinen@linux.intel.com> |
drm/amdgpu: Use RMW accessors for changing LNKCTL2 Convert open coded RMW accesses for LNKCTL2 to use pcie_capability_clear_and_set_word() which makes its easier to understand what the code tries to do. LNKCTL2 is not really owned by any driver because it is a collection of control bits that PCI core might need to touch. RMW accessors already have support for proper locking for a selected set of registers (LNKCTL2 is not yet among them but likely will be in the future) to avoid losing concurrent updates. Acked-by: Alex Deucher <alexander.deucher@amd.com> Suggested-by: Lukas Wunner <lukas@wunner.de> Signed-off-by: Ilpo Järvinen <ilpo.jarvinen@linux.intel.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
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#
1a6513de |
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23-Oct-2023 |
Mario Limonciello <mario.limonciello@amd.com> |
drm/amd: Move AMD_IS_APU check for ASPM into top level function There is no need for every ASIC driver to perform the same check. Move the duplicated code into amdgpu_device_should_use_aspm(). Signed-off-by: Mario Limonciello <mario.limonciello@amd.com> Reviewed-by: Alex Deucher <alexander.deucher@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
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#
ce7d8811 |
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17-Jul-2023 |
Ilpo Järvinen <ilpo.jarvinen@linux.intel.com> |
drm/amdgpu: Use RMW accessors for changing LNKCTL Don't assume that only the driver would be accessing LNKCTL. ASPM policy changes can trigger write to LNKCTL outside of driver's control. And in the case of upstream bridge, the driver does not even own the device it's changing the registers for. Use RMW capability accessors which do proper locking to avoid losing concurrent updates to the register value. Suggested-by: Lukas Wunner <lukas@wunner.de> Fixes: a2e73f56fa62 ("drm/amdgpu: Add support for CIK parts") Fixes: 62a37553414a ("drm/amdgpu: add si implementation v10") Link: https://lore.kernel.org/r/20230717120503.15276-6-ilpo.jarvinen@linux.intel.com Signed-off-by: Ilpo Järvinen <ilpo.jarvinen@linux.intel.com> Signed-off-by: Bjorn Helgaas <bhelgaas@google.com> Acked-by: Alex Deucher <alexander.deucher@amd.com>
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#
d51ac6d0 |
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23-May-2022 |
Le Ma <le.ma@amd.com> |
drm/amdgpu: add xcc index argument to select_sh_se function v2 v1: To support multiple XCD case (Le) v2: introduce xcc index to gfx_v11_0_select_sh_se (Hawking) Signed-off-by: Le Ma <le.ma@amd.com> Reviewed-by: Hawking Zhang <Hawking.Zhang@amd.com> Signed-off-by: Hawking Zhang <Hawking.Zhang@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
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#
0ab5d711 |
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16-Feb-2022 |
Mario Limonciello <mario.limonciello@amd.com> |
drm/amd: Refactor `amdgpu_aspm` to be evaluated per device Evaluating `pcie_aspm_enabled` as part of driver probe has the implication that if one PCIe bridge with an AMD GPU connected doesn't support ASPM then none of them do. This is an invalid assumption as the PCIe core will configure ASPM for individual PCIe bridges. Create a new helper function that can be called by individual dGPUs to react to the `amdgpu_aspm` module parameter without having negative results for other dGPUs on the PCIe bus. Suggested-by: Lijo Lazar <lijo.lazar@amd.com> Reviewed-by: Lijo Lazar <lijo.lazar@amd.com> Signed-off-by: Mario Limonciello <mario.limonciello@amd.com> Reviewed-by: Alex Deucher <alexander.deucher@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
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#
733ee71a |
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18-Jun-2021 |
Ryan Taylor <Ryan.Taylor@amd.com> |
drm/amdgpu: replace dce_virtual with amdgpu_vkms (v3) Move dce_virtual into amdgpu_vkms and update all references to dce_virtual with amdgpu_vkms. v2: Removed more references to dce_virtual. v3: Restored display modes from previous implementation. Signed-off-by: Ryan Taylor <Ryan.Taylor@amd.com> Reported-by: kernel test robot <lkp@intel.com> Suggested-by: Alex Deucher <alexander.deucher@amd.com> Reviewed-by: Alex Deucher <alexander.deucher@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
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#
6f786950 |
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02-Feb-2021 |
Alex Deucher <alexander.deucher@amd.com> |
drm/amdgpu/codec: drop the internal codec index And just use the ioctl index. They are the same. Reviewed-by: Christian König <christian.koenig@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
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#
3b246e8b |
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07-Jan-2021 |
Alex Deucher <alexander.deucher@amd.com> |
drm/amdgpu: add video decode/encode cap tables and asic callbacks (v3) For each asic family. Will be used to populate tables for the new INFO ioctl query. v2: add max_pixels_per_frame to handle the portrait case v3: fix copy paste typos Reviewed-by: Christian König <christian.koenig@amd.com> Reviewed-by: Leo Liu <leo.liu@amd.com> (v1) Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
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#
ffbfd081 |
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04-Feb-2021 |
Alex Deucher <alexander.deucher@amd.com> |
drm/amdgpu/si: add PCI reset support Use generic PCI reset for GPU reset if the user specifies PCI reset as the reset mechanism. This should in general only be used for validation. Acked-by: Evan Quan <evan.quan@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
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#
25bd5527 |
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04-Feb-2021 |
Alex Deucher <alexander.deucher@amd.com> |
drm/amdgpu/si: minor clean up of reset code Drop duplicate reset method logging, whitespace changes. Acked-by: Evan Quan <evan.quan@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
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#
94ba290d |
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02-Nov-2020 |
Deepak R Varma <mh12gx2825@gmail.com> |
drm/amdgpu: improve code indentation and alignment General code indentation and alignment changes such as replace spaces by tabs or align function arguments as per the coding style guidelines. The patch covers various .c files for this driver. Issue reported by checkpatch script. Signed-off-by: Deepak R Varma <mh12gx2825@gmail.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
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#
e66cdf25 |
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09-Sep-2020 |
Zheng Bin <zhengbin13@huawei.com> |
drm/amd/amdgpu: fix comparison pointer to bool warning in si.c Fixes coccicheck warning: drivers/gpu/drm/amd/amdgpu/si.c:1342:5-10: WARNING: Comparison to bool Acked-by: Christian König <christian.koenig@amd.com> Signed-off-by: Zheng Bin <zhengbin13@huawei.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
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#
632d9f94 |
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19-Aug-2020 |
Alex Deucher <alexander.deucher@amd.com> |
drm/amdgpu: add pre_asic_init callback for SI Nothing to do for this family. Acked-by: Nirmoy Das <nirmoy.das@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
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#
11043b7a |
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10-Aug-2020 |
Alex Deucher <alexander.deucher@amd.com> |
drm/amdgpu: note what type of reset we are using When we reset the GPU, note what type of reset will be used. This makes debugging different reset scenarios more clear as the driver may use different reset methods depending on conditions on the system. Acked-by: Nirmoy Das <nirmoy.das@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
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#
6cd3c679 |
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27-Jul-2020 |
Alex Deucher <alexander.deucher@amd.com> |
drm/amdgpu/si: initial support for GPU reset Ported from radeon. Acked-by: Christian König <christian.koenig@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
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#
64200c46 |
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04-Oct-2018 |
Mauro Rossi <issor.oruam@gmail.com> |
drm/amdgpu: enable DC support for SI parts (v2) [Why] amdgpu_device.c requires changes for SI chipsets support si.c require changes for Display Manager IP block enabling [How] amdgpu_device.c: add SI families in amdgpu_device_asic_has_dc_support() si.c: changes in si_set_ip_blocks() for Display Manager IP blocks enablement (v1) NOTE: As per Kaveri and older amdgpu.dc=1 kernel cmdline is required (v2) fix for bc011f9350 ("drm/amdgpu: Change SI/CI gfx/sdma/smu init sequence") remove CHIP_HAINAN support since it does not have physical DCE6 module Reviewed-by: Alex Deucher <alexander.deucher@amd.com> Signed-off-by: Mauro Rossi <issor.oruam@gmail.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
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#
273da6ff |
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14-Jul-2020 |
Wenhui Sheng <Wenhui.Sheng@amd.com> |
drm/amdgpu: add module parameter choose reset mode Default value is auto, doesn't change original reset method logic. v2: change to use parameter reset_method v3: add warn msg if specified mode isn't supported Signed-off-by: Likun Gao <Likun.Gao@amd.com> Signed-off-by: Wenhui Sheng <Wenhui.Sheng@amd.com> Reviewed-by: Hawking Zhang <Hawking.Zhang@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
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#
fb40bceb |
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23-Jun-2020 |
Alex Jivin <alex.jivin@amd.com> |
drm/amdgpu: SI support for VCE clock control Port functionality from the Radeon driver to support VCE clock control. Signed-off-by: Alex Jivin <alex.jivin@amd.com> Reviewed-by: Alex Deucher <alexander.deucher@amd.com> Acked-by: Christian König <christian.koenig@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
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#
3b0627a4 |
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24-Jun-2020 |
Alex Jivin <alex.jivin@amd.com> |
drm/amdgpu: SI support for UVD clock control Port functionality from the Radeon driver to support UVD clock control. Signed-off-by: Alex Jivin <alex.jivin@amd.com> Reviewed-by: Alex Deucher <alexander.deucher@amd.com> Acked-by: Christian König <christian.koenig@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
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#
ee2e74f7 |
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10-Jun-2020 |
Sonny Jiang <sonny.jiang@amd.com> |
drm amdgpu: SI UVD enabled on Verde, Tahiti, Pitcairn Enable asic Verde, Tahiti and Pitcairn UVD block. Signed-off-by: Sonny Jiang <sonny.jiang@amd.com> Reviewed-by: Alex Deucher <alexander.deucher@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
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#
d375615c |
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10-Jun-2020 |
Sonny Jiang <sonny.jiang@amd.com> |
drm amdgpu: SI UVD enable for Oland Enable Oland UVD block. Signed-off-by: Sonny Jiang <sonny.jiang@amd.com> Reviewed-by: Alex Deucher <alexander.deucher@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
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#
80533a85 |
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10-Jun-2020 |
Sonny Jiang <sonny.jiang@amd.com> |
drm amdgpu: SI UVD context rreg/wreg Implement SI uvd_ctx_rreg/wreg functions. Signed-off-by: Sonny Jiang <sonny.jiang@amd.com> Reviewed-by: Alex Deucher <alexander.deucher@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
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#
9c39d77c |
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22-Jun-2020 |
Alex Deucher <alexander.deucher@amd.com> |
drm/amdgpu/uvd3.x: fix register definition warnings drop the duplicate register macros from sid.h and use the standard ones in the oss register headers. Acked-by: Christian König <christian.koenig@amd.com> Reviewed-by: Hawking Zhang <Hawking.Zhang@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
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#
3aa0115d |
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03-Mar-2020 |
Monk Liu <Monk.Liu@amd.com> |
drm/amdgpu: cleanup all virtualization detection routine we need to move virt detection much earlier because: 1) HW team confirms us that RCC_IOV_FUNC_IDENTIFIER will always be at DE5 (dw) mmio offset from vega10, this way there is no need to implement detect_hw_virt() routine in each nbio/chip file. for VI SRIOV chip (tonga & fiji), the BIF_IOV_FUNC_IDENTIFIER is at 0x1503 2) we need to acknowledged we are SRIOV VF before we do IP discovery because the IP discovery content will be updated by host everytime after it recieved a new coming "REQ_GPU_INIT_DATA" request from guest (there will be patches for this new handshake soon). Signed-off-by: Monk Liu <Monk.Liu@amd.com> Reviewed-by: Emily Deng <Emily.Deng@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
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#
88027c89 |
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17-Nov-2019 |
Frederick Lawler <fred@fredlawl.com> |
drm/amdgpu: Prefer pcie_capability_read_word() Commit 8c0d3a02c130 ("PCI: Add accessors for PCI Express Capability") added accessors for the PCI Express Capability so that drivers didn't need to be aware of differences between v1 and v2 of the PCI Express Capability. Replace pci_read_config_word() and pci_write_config_word() calls with pcie_capability_read_word() and pcie_capability_write_word(). [bhelgaas: fix a couple remaining instances in cik.c] Link: https://lore.kernel.org/r/20191118003513.10852-1-fred@fredlawl.com Signed-off-by: Frederick Lawler <fred@fredlawl.com> Signed-off-by: Bjorn Helgaas <bhelgaas@google.com> Reviewed-by: Alex Deucher <alexander.deucher@amd.com>
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#
35e768e2 |
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21-Nov-2019 |
Bjorn Helgaas <bhelgaas@google.com> |
drm/amdgpu: Replace numbers with PCI_EXP_LNKCTL2 definitions Replace hard-coded magic numbers with the descriptive PCI_EXP_LNKCTL2 definitions. No functional change intended. Link: https://lore.kernel.org/r/20191112173503.176611-4-helgaas@kernel.org Signed-off-by: Bjorn Helgaas <bhelgaas@google.com> Reviewed-by: Alex Deucher <alexander.deucher@amd.com>
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#
19d7a95a |
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20-Nov-2019 |
Bjorn Helgaas <bhelgaas@google.com> |
drm/amdgpu: Correct Transmit Margin masks Previously we masked PCIe Link Control 2 register values with "7 << 9", which was apparently intended to be the Transmit Margin field, but instead was the high order bit of Transmit Margin, the Enter Modified Compliance bit, and the Compliance SOS bit. Correct the mask to "7 << 7", which is the Transmit Margin field. Link: https://lore.kernel.org/r/20191112173503.176611-3-helgaas@kernel.org Signed-off-by: Bjorn Helgaas <bhelgaas@google.com> Reviewed-by: Alex Deucher <alexander.deucher@amd.com>
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#
3670c242 |
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04-Oct-2019 |
Alex Deucher <alexander.deucher@amd.com> |
drm/amdgpu: add supports_baco callback for SI asics. BACO - Bus Active, Chip Off Not supported. Reviewed-by: Evan Quan <evan.quan@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
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#
664fe85a |
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22-Oct-2019 |
Marek Olšák <marek.olsak@amd.com> |
drm/amdgpu: Allow reading more status registers on si/cik Allow userspace to read the same status registers for every family. Based on commit c7890fea, added any of these registers if defined in the include files of each architecture. Signed-off-by: Marek Olšák <marek.olsak@amd.com> Reviewed-by: Alex Deucher <alexander.deucher@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
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#
77efe48a |
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28-Aug-2019 |
Jean Delvare <jdelvare@suse.de> |
drm/amdgpu/si: fix ASIC tests Comparing adev->family with CHIP constants is not correct. adev->family can only be compared with AMDGPU_FAMILY constants and adev->asic_type is the struct member to compare with CHIP constants. They are separate identification spaces. Signed-off-by: Jean Delvare <jdelvare@suse.de> Fixes: 62a37553414a ("drm/amdgpu: add si implementation v10") Cc: Ken Wang <Qingqing.Wang@amd.com> Cc: Alex Deucher <alexander.deucher@amd.com> Cc: "Christian König" <christian.koenig@amd.com> Cc: "David (ChunMing) Zhou" <David1.Zhou@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
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#
dd81eede |
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23-Jul-2019 |
Alex Deucher <alexander.deucher@amd.com> |
drm/amdgpu: add reset_method asic callback for si SI always uses the legacy pci based reset. Reviewed-by: Evan Quan <evan.quan@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
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#
0172591e |
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24-Jun-2019 |
Ernst Sjöstrand <ernstp@gmail.com> |
drm/amd/amdgpu: Indent AMD_IS_APU properly Reported by smatch: drivers/gpu/drm/amd/amdgpu/soc15.c:715 soc15_get_pcie_usage() warn: inconsistent indenting And a similar one in si.c. Signed-off-by: Ernst Sjöstrand <ernstp@gmail.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
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#
47b757fb |
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09-Jun-2019 |
Sam Ravnborg <sam@ravnborg.org> |
drm/amd: drop use of drmP.h in remaining files With this commit drm/amd/ has no longer any uses of the deprecated drmP.h header file. Signed-off-by: Sam Ravnborg <sam@ravnborg.org> Reviewed-by: Alex Deucher <alexander.deucher@amd.com> Cc: "Christian König" <christian.koenig@amd.com> Cc: "David (ChunMing) Zhou" <David1.Zhou@amd.com> Cc: David Airlie <airlied@linux.ie> Cc: Daniel Vetter <daniel@ffwll.ch> Link: https://patchwork.freedesktop.org/patch/msgid/20190609220757.10862-11-sam@ravnborg.org
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#
dcea6e65 |
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30-Apr-2019 |
Kent Russell <kent.russell@amd.com> |
drm/amdgpu: Add PCIe replay count sysfs file Add a sysfs file for reporting the number of PCIe replays (NAKs). This returns the sum of NAKs received and NAKs generated Signed-off-by: Kent Russell <kent.russell@amd.com> Reviewed-by: Alex Deucher <alexander.deucher@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
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#
9b49c197 |
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12-Feb-2019 |
Colin Ian King <colin.king@canonical.com> |
drm/amdgpu: fix several indentation issues There are several statements that are incorrectly indented. Fix these. Reviewed-by: Christian König <christian.koenig@amd.com> Signed-off-by: Colin Ian King <colin.king@canonical.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
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#
7450bbe7 |
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31-Oct-2018 |
Alex Deucher <alexander.deucher@amd.com> |
drm/amdgpu/si: add need_reset_on_init asic callback for SI (v2) SI chips don't require a reset on reload due to the nature of the SMU on them. v2: rebase Reviewed-by: Evan Quan <evan.quan@amd.com> Reviewed-by: Felix Kuehling <Felix.Kuehling@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
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#
b45e18ac |
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03-Jan-2019 |
Kent Russell <kent.russell@amd.com> |
drm/amdgpu: Add sysfs file for PCIe usage v5 Add a sysfs file that reports the number of bytes transmitted and received in the last second. This can be used to approximate the PCIe bandwidth usage over the last second. v2: Clarify use of mps as estimation of bandwidth v3: Don't make the file on APUs v4: Early exit for APUs in the read function, change output to display "packets-received packets-sent mps" v5: fix missing header for si (Alex) Signed-off-by: Kent Russell <kent.russell@amd.com> Reviewed-by: Felix Kuehling <Felix.Kuehling@amd.com> Reviewed-by: Alex Deucher <alexander.deucher@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
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#
3089aa22 |
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30-Sep-2018 |
Rex Zhu <Rex.Zhu@amd.com> |
drm/amdgpu: Change SI/CI gfx/sdma/smu init sequence initialize gfx/sdma before dpm features enabled. Acked-by: Alex Deucher <alexander.deucher@amd.com> Signed-off-by: Rex Zhu <Rex.Zhu@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
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#
0a881af8 |
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03-Apr-2018 |
Alex Deucher <alexander.deucher@amd.com> |
drm/amdgpu/si: implement asic need_full_reset callback Used to check on a per SoC basis whether the SoC needs a full reset of a per IP soft reset. Reviewed-by: Christian König <christian.koenig@amd.com> Reviewed-by: Huang Rui <ray.huang@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
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#
20ca25e8 |
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02-Apr-2018 |
Alex Deucher <alexander.deucher@amd.com> |
drm/amdgpu/si: implement get/set pcie_lanes asic callback Required for dpm setup on some asics. Fixes a NULL dereference on asics that require it. Acked-by: Christian König <christian.koenig@amd.com> Bug: https://bugs.freedesktop.org/show_bug.cgi?id=102553 Tested-by: Abel Garcia Dorta <mercuriete@yahoo.es> Signed-off-by: Alex Deucher <alexander.deucher@amd.com> Cc: stable@vger.kernel.org
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#
b905090d |
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12-Mar-2018 |
Rex Zhu <Rex.Zhu@amd.com> |
drm/amdgpu: Remove wrapper layer of smu ip functions 1. delete amdgpu_powerplay.c used for wrapping smu ip functions 2. delete struct pp_instance, 3. make struct hwmgr as the smu hw handle. Reviewed-by: Alex Deucher <alexander.deucher@amd.com> Reviewed-by: Evan Quan <evan.quan@amd.com> Signed-off-by: Rex Zhu <Rex.Zhu@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
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#
05656e5e |
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26-Feb-2018 |
Alex Deucher <alexander.deucher@amd.com> |
drm/amdgpu: used cached pcie gen info for SI (v2) Rather than querying it every time we need it. Also fixes a crash in VM pass through if there is no root bridge because the cached value fetch already checks this properly. v2: fix includes Fixes: https://bugs.freedesktop.org/show_bug.cgi?id=105244 Acked-by: Christian König <christian.koenig@amd.com> Reviewed-by: Rex Zhu<rezhu@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com> Cc: stable@vger.kernel.org
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#
0bf67185 |
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26-Feb-2018 |
Alex Deucher <alexander.deucher@amd.com> |
drm/amdgpu: used cached pcie gen info for SI (v2) Rather than querying it every time we need it. Also fixes a crash in VM pass through if there is no root bridge because the cached value fetch already checks this properly. v2: fix includes Fixes: https://bugs.freedesktop.org/show_bug.cgi?id=105244 Acked-by: Christian König <christian.koenig@amd.com> Reviewed-by: Rex Zhu<rezhu@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com> Cc: stable@vger.kernel.org
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#
69882565 |
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19-Jan-2018 |
Christian König <christian.koenig@amd.com> |
drm/amdgpu: add optional ring to *_hdp callbacks This adds an optional ring to the invalidate_hdp and flush_hdp callbacks. If the ring isn't specified or the emit_wreg function not available the HDP operation will be done with the CPU otherwise by writing on the ring. Signed-off-by: Christian König <christian.koenig@amd.com> Acked-by: Chunming Zhou <david1.zhou@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
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#
2d5e0807 |
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06-Sep-2017 |
Alex Deucher <alexander.deucher@amd.com> |
drm/amdgpu: add HDP asic callbacks for SI Needed to flush and invalidate the HDP block using the CPU. Reviewed-by: Christian König <christian.koenig@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com> Signed-off-by: Samuel Li <Samuel.Li@amd.com>
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#
2990a1fc |
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15-Dec-2017 |
Alex Deucher <alexander.deucher@amd.com> |
drm/amdgpu: rename ip block helper functions add device to the name for consistency. Acked-by: Christian König <christian.koenig@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
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#
9c3f2b54 |
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14-Dec-2017 |
Alex Deucher <alexander.deucher@amd.com> |
drm/amdgpu: rename amdgpu_program_register_sequence add device for consistency with other functions in this file. Acked-by: Christian König <christian.koenig@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
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c47b41a7 |
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03-Nov-2017 |
Christian König <christian.koenig@amd.com> |
drm/amdgpu: remove nonsense const u32 cast on ARRAY_SIZE result Not sure what that should originally been good for, but it doesn't seem to make any sense any more. Signed-off-by: Christian König <christian.koenig@amd.com> Reviewed-by: Alex Deucher <alexander.deucher@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
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2db93bea |
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30-Jul-2017 |
Jean Delvare <jdelvare@suse.de> |
drm/amdgpu: Fix undue fallthroughs in golden registers initialization As I was staring at the si_init_golden_registers code, I noticed that the Pitcairn initialization silently falls through the Cape Verde initialization, and the Oland initialization falls through the Hainan initialization. However there is no comment stating that this is intentional, and the radeon driver doesn't have any such fallthrough, so I suspect this is not supposed to happen. Signed-off-by: Jean Delvare <jdelvare@suse.de> Fixes: 62a37553414a ("drm/amdgpu: add si implementation v10") Cc: Ken Wang <Qingqing.Wang@amd.com> Cc: Alex Deucher <alexander.deucher@amd.com> Cc: "Marek Olšák" <maraeo@gmail.com> Cc: "Christian König" <christian.koenig@amd.com> Cc: Flora Cui <Flora.Cui@amd.com> Reviewed-by: Marek Olšák <marek.olsak@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com> Cc: stable@vger.kernel.org
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5694785c |
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30-Jul-2017 |
Jean Delvare <jdelvare@suse.de> |
drm/amdgpu: Fix undue fallthroughs in golden registers initialization As I was staring at the si_init_golden_registers code, I noticed that the Pitcairn initialization silently falls through the Cape Verde initialization, and the Oland initialization falls through the Hainan initialization. However there is no comment stating that this is intentional, and the radeon driver doesn't have any such fallthrough, so I suspect this is not supposed to happen. Signed-off-by: Jean Delvare <jdelvare@suse.de> Fixes: 62a37553414a ("drm/amdgpu: add si implementation v10") Cc: Ken Wang <Qingqing.Wang@amd.com> Cc: Alex Deucher <alexander.deucher@amd.com> Cc: "Marek Olšák" <maraeo@gmail.com> Cc: "Christian König" <christian.koenig@amd.com> Cc: Flora Cui <Flora.Cui@amd.com> Reviewed-by: Marek Olšák <marek.olsak@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com> Cc: stable@vger.kernel.org
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6d949d24 |
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12-Jul-2017 |
Alex Deucher <alexander.deucher@amd.com> |
drm/amdgpu: implement si_read_bios_from_rom This allows us to read the vbios image directly from ROM. This is already implemented for other asics, but was not yet available for SI. Acked-by: Christian König <christian.koenig@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
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97fcc76b |
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11-Apr-2017 |
Christian König <christian.koenig@amd.com> |
drm/amdgpu: drop support for untouched registers I couldn't figure out what this was original good for, but we don't use it any more. Signed-off-by: Christian König <christian.koenig@amd.com> Reviewed-by: Alex Deucher <alexander.deucher@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
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248a1d6f |
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23-Apr-2017 |
Masahiro Yamada <yamada.masahiro@socionext.com> |
drm/amd: fix include notation and remove -Iinclude/drm flag Include <drm/*.h> instead of relative path from include/drm, then remove the -Iinclude/drm compiler flag. Signed-off-by: Masahiro Yamada <yamada.masahiro@socionext.com> Reviewed-by: Michel Dänzer <michel.daenzer@amd.com> Signed-off-by: Daniel Vetter <daniel.vetter@ffwll.ch> Link: http://patchwork.freedesktop.org/patch/msgid/1493009447-31524-4-git-send-email-yamada.masahiro@socionext.com
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bbf282d8 |
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03-Mar-2017 |
Alex Deucher <alexander.deucher@amd.com> |
drm/amdgpu: add asic callback to get memsize register Newer asics use different registers so abstract it. Reviewed-by: Christian König <christian.koenig@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
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dd5dfa61 |
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07-Feb-2017 |
Flora Cui <Flora.Cui@amd.com> |
drm/amdgpu: refine si_read_register Signed-off-by: Flora Cui <Flora.Cui@amd.com> Reviewed-by: Hawking Zhang <Hawking.Zhang@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
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689957b1 |
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24-Jan-2017 |
Alex Deucher <alexander.deucher@amd.com> |
drm/amdgpu: move misc si headers into amdgpu Move these to the amdgpu directory to match what we do for other asics. Acked-by: Christian König <christian.koenig@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
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c8394f38 |
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08-Jan-2017 |
Xiangliang Yu <Xiangliang.Yu@amd.com> |
drm/amdgpu: remove detect_hw_virtualization interface Call detection function driectly, so remove the interface. V2: ci and si also need to call the detect function. Reviewed-by: Alex Deucher <alexander.deucher@amd.com> Reviewed-by: Monk Liu <monk.liu@amd.com> Acked-by: Christian König <christian.koenig@amd.com> Signed-off-by: Xiangliang Yu <Xiangliang.Yu@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
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5a5099cb |
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09-Jan-2017 |
Xiangliang Yu <Xiangliang.Yu@amd.com> |
drm/amdgpu/virt: rename fieldes of virtualization structure Use acronym to rename fields to make easy to spell out. Signed-off-by: Xiangliang Yu <Xiangliang.Yu@amd.com> Reviewed-by: Alex Deucher <alexander.deucher@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
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78bbe771 |
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16-Dec-2016 |
Tom St Denis <tom.stdenis@amd.com> |
drm/amd/amdgpu: De-numberify golden SI registers Where possible replace numeric constants in the table with their register names. Compile tested + executed on a Tahiti. Signed-off-by: Tom St Denis <tom.stdenis@amd.com> Reviewed-by: Harry Wentland <harry.wentland@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
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f815b29c |
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15-Dec-2016 |
Flora Cui <Flora.Cui@amd.com> |
drm/amdgpu: update rev id for verde Signed-off-by: Flora Cui <Flora.Cui@amd.com> Reviewed-by: Junwei Zhang <Jerry.Zhang@amd.com> Reviewed-by: Alex Deucher <alexander.deucher@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com> Cc: stable@vger.kernel.org
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dae5c298 |
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15-Dec-2016 |
Flora Cui <Flora.Cui@amd.com> |
drm/amdgpu: update golden setting for verde Signed-off-by: Flora Cui <Flora.Cui@amd.com> Reviewed-by: Junwei Zhang <Jerry.Zhang@amd.com> Reviewed-by: Alex Deucher <alexander.deucher@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com> Cc: stable@vger.kernel.org
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8fd74cb4 |
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15-Dec-2016 |
Flora Cui <Flora.Cui@amd.com> |
drm/amdgpu: update rev id for oland Signed-off-by: Flora Cui <Flora.Cui@amd.com> Reviewed-by: Junwei Zhang <Jerry.Zhang@amd.com> Reviewed-by: Alex Deucher <alexander.deucher@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com> Cc: stable@vger.kernel.org
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6b7985ef |
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15-Dec-2016 |
Flora Cui <Flora.Cui@amd.com> |
drm/amdgpu: update golden setting for oland Signed-off-by: Flora Cui <Flora.Cui@amd.com> Reviewed-by: Junwei Zhang <Jerry.Zhang@amd.com> Reviewed-by: Alex Deucher <alexander.deucher@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com> Cc: stable@vger.kernel.org
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05319478 |
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14-Dec-2016 |
Flora Cui <Flora.Cui@amd.com> |
drm/amdgpu: update rev id for hainan Signed-off-by: Flora Cui <Flora.Cui@amd.com> Reviewed-by: Junwei Zhang <Jerry.Zhang@amd.com> Reviewed-by: Alex Deucher <alexander.deucher@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com> Cc: stable@vger.kernel.org
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bd27b678 |
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14-Dec-2016 |
Flora Cui <Flora.Cui@amd.com> |
drm/amdgpu: update golden setting for hainan Signed-off-by: Flora Cui <Flora.Cui@amd.com> Reviewed-by: Junwei Zhang <Jerry.Zhang@amd.com> Reviewed-by: Alex Deucher <alexander.deucher@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com> Cc: stable@vger.kernel.org
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e285a9a6 |
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15-Dec-2016 |
Flora Cui <Flora.Cui@amd.com> |
drm/amdgpu: update rev id for pitcairn Signed-off-by: Flora Cui <Flora.Cui@amd.com> Reviewed-by: Junwei Zhang <Jerry.Zhang@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com> Cc: stable@vger.kernel.org
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1245a694 |
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15-Dec-2016 |
Flora Cui <Flora.Cui@amd.com> |
drm/amdgpu: update golden setting for pitcairn Signed-off-by: Flora Cui <Flora.Cui@amd.com> Reviewed-by: Junwei Zhang <Jerry.Zhang@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com> Cc: stable@vger.kernel.org
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7c0a705e |
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13-Dec-2016 |
Flora Cui <Flora.Cui@amd.com> |
drm/amdgpu: update golden setting/tiling table of tahiti Signed-off-by: Flora Cui <Flora.Cui@amd.com> Reviewed-by: Hawking Zhang <Hawking.Zhang@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com> Cc: stable@vger.kernel.org
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d1936cc2 |
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22-Oct-2016 |
Baoyou Xie <baoyou.xie@linaro.org> |
drm/amdgpu: mark symbols static where possible We get 2 warnings when building kernel with W=1: drivers/gpu/drm/amd/amdgpu/si.c:908:5: warning: no previous prototype for 'si_pciep_rreg' [-Wmissing-prototypes] drivers/gpu/drm/amd/amdgpu/si.c:921:6: warning: no previous prototype for 'si_pciep_wreg' [-Wmissing-prototypes] In fact, both functions are only used in the file in which they are declared and don't need a declaration, but can be made static. So this patch marks these functions with 'static'. Acked-by: Edward O'Callaghan <funfunctor@folklore1984.net> Reviewed-by: Christian König <christian.koenig@amd.com> Signed-off-by: Baoyou Xie <baoyou.xie@linaro.org> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
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a1255107 |
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13-Oct-2016 |
Alex Deucher <alexander.deucher@amd.com> |
drm/amdgpu: rework IP block registration (v2) This makes it easier to replace specific IP blocks on asics for handling virtual_dce, DAL, etc. and for building IP lists for hw or tables. This also stored the status information in the same structure. v2: split out spelling fix into a separate patch add a function to add IPs to the list Reviewed-by: Christian König <christian.koenig@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
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2120df47 |
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13-Oct-2016 |
Alex Deucher <alexander.deucher@amd.com> |
drm/amdgpu: enable virtual dce on SI Add the proper IP module when requested. Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
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4e99a44e |
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30-Mar-2016 |
Monk Liu <Monk.Liu@amd.com> |
drm/amdgpu:changes of virtualization cases probe (v3) 1,Changes on virtualization detections 2,Don't load smu & mc firmware if using sr-iov bios 3,skip vPost for sriov & force vPost if dev pass-through v2: agd: squash in Rays's fix for the missed SI case v3: agd: squash in additional fixes for CIK, SI, cleanup Signed-off-by: Monk Liu <Monk.Liu@amd.com> Reviewed-by: Alex Deucher <alexander.deucher@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
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1919696e |
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26-Apr-2016 |
Maruthi Srinivas Bayyavarapu <Maruthi.Bayyavarapu@amd.com> |
drm/amdgpu: enable SI DPM Signed-off-by: Maruthi Bayyavarapu <maruthi.bayyavarapu@amd.com> Reviewed-by: Alex Deucher <alexander.deucher@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
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36b9a952 |
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30-Aug-2016 |
Huang Rui <ray.huang@amd.com> |
drm/amdgpu: introduce pcie port read/write entry This patch adds pcie port read/write entry, because it will be also used on si dpm part. Acked-by: Christian König <christian.koenig@amd.com> Reviewed-by: Alex Deucher <alexander.deucher@amd.com> Signed-off-by: Huang Rui <ray.huang@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
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62a37553 |
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18-Jan-2016 |
Ken Wang <Qingqing.Wang@amd.com> |
drm/amdgpu: add si implementation v10 v5: rebase fixes v6: add mgcg arrays v7: rebase fixes v8: rebase fixes v9: add get_disabled_bios(), make get_xclk static v10: fix oland and hainan asic specific handle at si_program_aspm Signed-off-by: Ken Wang <Qingqing.Wang@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
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