/linux-master/drivers/net/mdio/ |
H A D | mdio-ipq4019.c | 221 int div; local 234 for (div = 8; div <= 256; div *= 2) { 235 /* The requested rate is supported by the div */ 236 if (priv->mdc_rate == DIV_ROUND_UP(ahb_rate, div)) { 239 val |= MDIO_MODE_DIV(div); 285 int div; local 298 /* Check what is the current div set */ 300 div [all...] |
/linux-master/drivers/media/dvb-frontends/ |
H A D | bsru6.h | 91 u32 div; local 98 div = (p->frequency + (125 - 1)) / 125; /* round correctly */ 99 buf[0] = (div >> 8) & 0x7f; 100 buf[1] = div & 0xff; 101 buf[2] = 0x80 | ((div & 0x18000) >> 10) | 4;
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H A D | bsbe1.h | 60 u32 div; local 67 div = p->frequency / 1000; 68 data[0] = (div >> 8) & 0x7f; 69 data[1] = div & 0xff; 70 data[2] = 0x80 | ((div & 0x18000) >> 10) | 0x1;
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/linux-master/drivers/clk/mediatek/ |
H A D | clk-mt8516-apmixedsys.c | 51 { .div = 0, .freq = MT8516_PLL_FMAX }, 52 { .div = 1, .freq = 1000000000 }, 53 { .div = 2, .freq = 604500000 }, 54 { .div = 3, .freq = 253500000 }, 55 { .div = 4, .freq = 126750000 },
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H A D | clk-mt8183-apmixedsys.c | 93 { .div = 0, .freq = MT8183_PLL_FMAX }, 94 { .div = 1, .freq = 1500 * MHZ }, 95 { .div = 2, .freq = 750 * MHZ }, 96 { .div = 3, .freq = 375 * MHZ }, 97 { .div = 4, .freq = 187500000 }, 102 { .div = 0, .freq = MT8183_PLL_FMAX }, 103 { .div = 1, .freq = 1600 * MHZ }, 104 { .div = 2, .freq = 800 * MHZ }, 105 { .div = 3, .freq = 400 * MHZ }, 106 { .div [all...] |
/linux-master/drivers/cpufreq/ |
H A D | cpufreq-nforce2.c | 25 #define NFORCE2_PLL(mul, div) (0x100000 | (mul << 8) | div) 69 unsigned char mul, div; local 72 div = pll & 0xff; 74 if (div > 0) 75 return NFORCE2_XTAL * mul / div; 89 unsigned char mul = 0, div = 0; local 93 while (((mul == 0) || (div == 0)) && (tried <= 3)) { 99 div = xdiv; 104 if ((mul == 0) || (div [all...] |
/linux-master/drivers/clk/sunxi/ |
H A D | clk-sun9i-core.c | 101 u32 div; local 106 div = DIV_ROUND_UP(req->parent_rate, req->rate); 109 if (div > 4) 110 div = 4; 112 req->rate = req->parent_rate / div; 113 req->m = div; 236 u32 div; local 241 div = DIV_ROUND_UP(req->parent_rate, req->rate); 244 if (div > 256) 245 div [all...] |
H A D | clk-sun4i-display.c | 107 struct clk_divider *div = NULL; local 147 div = kzalloc(sizeof(*div), GFP_KERNEL); 148 if (!div) 151 div->reg = reg; 152 div->shift = data->offset_div; 153 div->width = data->width_div; 154 div->lock = &sun4i_a10_display_lock; 160 data->has_div ? &div->hw : NULL, 211 kfree(div); [all...] |
/linux-master/drivers/clk/imx/ |
H A D | clk-composite-93.c | 190 struct clk_divider *div = NULL; local 206 div = kzalloc(sizeof(*div), GFP_KERNEL); 207 if (!div) 210 div_hw = &div->hw; 211 div->reg = reg; 212 div->shift = CCM_DIV_SHIFT; 213 div->width = CCM_DIV_WIDTH; 214 div->lock = &imx_ccm_lock; 215 div [all...] |
/linux-master/drivers/clk/renesas/ |
H A D | r7s9210-cpg-mssr.c | 141 r7s9210_core_clks[i].div = ratio_tab[index].i; 144 r7s9210_core_clks[i].div = ratio_tab[index].g; 147 r7s9210_core_clks[i].div = ratio_tab[index].b; 151 r7s9210_core_clks[i].div = ratio_tab[index].p1; 154 r7s9210_core_clks[i].div = 32; 167 unsigned int div = 1; local 192 __clk_get_name(parent), 0, mult, div);
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H A D | rcar-cpg-lib.c | 127 struct clk_divider div; member in struct:rpc_clock 151 rpc->div.reg = rpcckcr; 152 rpc->div.width = 3; 153 rpc->div.table = cpg_rpc_div_table; 154 rpc->div.lock = &cpg_lock; 164 &rpc->div.hw, &clk_divider_ops, 193 rpcd2->fixed.div = 2;
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H A D | clk-r8a7740.c | 66 unsigned int div = 1; local 73 div = 2048; 78 div = 1024; 88 div = 2; 102 div = 2; 115 div = 2; 133 mult, div);
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H A D | rcar-gen4-cpg.c | 291 unsigned int div, 317 zclk->fixed_div = div; /* PLLVCO x 1/div x SYS-CPU divider */ 344 unsigned int div = 1; local 353 div = cpg_pll_config->extal_div; 358 div = cpg_pll_config->pll1_div; 372 div = cpg_pll_config->pll2_div; 377 div = cpg_pll_config->pll3_div; 382 div = cpg_pll_config->pll4_div; 387 div 288 cpg_z_clk_register(const char *name, const char *parent_name, void __iomem *reg, unsigned int div, unsigned int offset) argument [all...] |
/linux-master/drivers/clk/qcom/ |
H A D | clk-krait.c | 99 /* The divider can divide by 2, 4, 6 and 8. But we only really need div-2. */ 134 u32 div; local 136 div = krait_get_l2_indirect_reg(d->offset); 137 div >>= d->shift; 138 div &= mask; 139 div = (div + 1) * 2; 141 return DIV_ROUND_UP(parent_rate, div);
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H A D | clk-spmi-pmic-div.c | 46 static inline unsigned int div_to_div_factor(unsigned int div) argument 48 return min(ilog2(div) + 1, 7); 66 unsigned int div = div_factor_to_div(div_factor); local 74 ndelay((2 + 3 * div) * ns); 76 ndelay(3 * div * ns); 117 unsigned int div, div_factor; local 119 div = DIV_ROUND_UP(*parent_rate, rate); 120 div_factor = div_to_div_factor(div); 121 div = div_factor_to_div(div_factor); 123 return *parent_rate / div; [all...] |
/linux-master/drivers/pwm/ |
H A D | pwm-mxs.c | 32 #define PERIOD_CDIV(div) (((div) & 0x7) << 20) 53 int ret, div = 0; local 75 c = rate >> cdiv_shift[div]; 80 div++; 81 if (div >= PERIOD_CDIV_MAX) 101 writel(PERIOD_PERIOD(period_cycles) | pol_bits | PERIOD_CDIV(div),
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/linux-master/drivers/clk/stm32/ |
H A D | clk-stm32-core.c | 189 for (clkt = table; clkt->div; clkt++) 191 return clkt->div; 214 unsigned int div; local 218 div = _get_div(divider->table, val, divider->flags, divider->width); 220 if (!div) { 227 return DIV_ROUND_UP_ULL((u64)parent_rate, div); 338 struct clk_stm32_div *div = to_clk_stm32_divider(hw); local 342 if (div->div_id == NO_STM32_DIV) 345 spin_lock_irqsave(div->lock, flags); 347 ret = stm32_divider_set_rate(div 357 struct clk_stm32_div *div = to_clk_stm32_divider(hw); local 385 struct clk_stm32_div *div = to_clk_stm32_divider(hw); local 674 struct clk_stm32_div *div = cfg->clock_cfg; local [all...] |
/linux-master/drivers/staging/media/deprecated/atmel/ |
H A D | atmel-isc-clk.c | 67 dev_dbg(isc_clk->dev, "ISC CLK: %s, id = %d, div = %d, parent id = %d\n", 68 __func__, id, isc_clk->div, isc_clk->parent_id); 73 (isc_clk->div << ISC_CLKCFG_DIV_SHIFT(id)) | 119 return DIV_ROUND_CLOSEST(parent_rate, isc_clk->div + 1); 128 unsigned int i, div; local 142 for (div = 1; div < ISC_CLK_MAX_DIV + 2; div++) { 146 rate = DIV_ROUND_CLOSEST(parent_rate, div); 202 u32 div; local [all...] |
/linux-master/drivers/media/platform/microchip/ |
H A D | microchip-isc-clk.c | 67 dev_dbg(isc_clk->dev, "ISC CLK: %s, id = %d, div = %d, parent id = %d\n", 68 __func__, id, isc_clk->div, isc_clk->parent_id); 73 (isc_clk->div << ISC_CLKCFG_DIV_SHIFT(id)) | 119 return DIV_ROUND_CLOSEST(parent_rate, isc_clk->div + 1); 128 unsigned int i, div; local 142 for (div = 1; div < ISC_CLK_MAX_DIV + 2; div++) { 146 rate = DIV_ROUND_CLOSEST(parent_rate, div); 202 u32 div; local [all...] |
/linux-master/arch/m68k/math-emu/ |
H A D | multi_arith.h | 132 #define fp_div64(quot, rem, srch, srcl, div) \ 134 : "dm" (div), "1" (srch), "0" (srcl)) 183 struct fp_ext *div) 191 /* the algorithm below requires dest to be smaller than div, 193 if (src->mant.m64 >= div->mant.m64) { 194 fp_sub64(src->mant, div->mant); 210 dummy = div->mant.m32[1] / div->mant.m32[0] + 1; 216 if (src->mant.m32[0] == div->mant.m32[0]) { 217 fp_div64(first, rem, 0, src->mant.m32[1], div 182 fp_dividemant(union fp_mant128 *dest, struct fp_ext *src, struct fp_ext *div) argument [all...] |
/linux-master/drivers/hwmon/ |
H A D | max6620.c | 150 static u16 max6620_fan_rpm_to_tach(u8 div, int rpm) argument 152 return (60 * div * MAX6620_CLOCK_FREQ) / (rpm * MAX6620_PULSE_PER_REV); 155 static int max6620_fan_tach_to_rpm(u8 div, u16 tach) argument 157 return (60 * div * MAX6620_CLOCK_FREQ) / (tach * MAX6620_PULSE_PER_REV); 250 u8 div; local 296 div = max6620_fan_div_from_reg(data->fandyn[channel]); 297 *val = max6620_fan_tach_to_rpm(div, data->tach[channel]); 304 div = max6620_fan_div_from_reg(data->fandyn[channel]); 305 *val = max6620_fan_tach_to_rpm(div, data->target[channel]); 327 u8 div; local [all...] |
/linux-master/drivers/clk/ |
H A D | clk-qoriq.c | 44 struct clockgen_pll_div div[MAX_PLL_DIV]; member in struct:clockgen_pll 53 int div; /* PLL_DIVn */ member in struct:clockgen_sourceinfo 476 cg->fman[0] = cg->pll[CGA_PLL2].div[PLL_DIV2].clk; 478 cg->fman[0] = cg->pll[PLATFORM_PLL].div[PLL_DIV2].clk; 488 cg->fman[0] = cg->pll[CGA_PLL3].div[PLL_DIV2].clk; 490 cg->fman[0] = cg->pll[PLATFORM_PLL].div[PLL_DIV2].clk; 493 cg->fman[1] = cg->pll[CGA_PLL3].div[PLL_DIV2].clk; 495 cg->fman[1] = cg->pll[PLATFORM_PLL].div[PLL_DIV2].clk; 501 int div = PLL_DIV2; local 505 div 516 int div = PLL_DIV2; local 898 int pll, div; local 919 const struct clockgen_pll_div *div; local 973 const struct clockgen_pll_div *div; local [all...] |
/linux-master/drivers/clk/at91/ |
H A D | clk-generated.c | 110 unsigned long parent_rate, u32 div, 116 if (!div) 119 tmp_rate = parent_rate / div; 143 u32 div; local 165 div = DIV_ROUND_CLOSEST(parent_rate, req->rate); 166 if (div > GENERATED_MAX_DIV + 1) 167 div = GENERATED_MAX_DIV + 1; 169 clk_generated_best_diff(req, parent, parent_rate, div, 193 for (div = 1; div < GENERATED_MAX_DI 108 clk_generated_best_diff(struct clk_rate_request *req, struct clk_hw *parent, unsigned long parent_rate, u32 div, int *best_diff, long *best_rate) argument 248 u32 div; local [all...] |
/linux-master/arch/m68k/atari/ |
H A D | debug.c | 219 int clksrc, clkmode, div, reg3, reg5; local 229 div = div_table[baud]; 236 div = 0; 253 SCC_WRITE(12, div); /* BRG value */ 256 SCC_WRITE(14, brgsrc_table[baud] | (div ? 1 : 0)); 269 int div; local 276 div = ACIA_DIV64; /* really 7812.5 bps */ 278 div = ACIA_DIV1; /* really 500 kbps (does that work??) */ 280 div = ACIA_DIV16; /* 31250 bps, standard for MIDI */ 283 acia.mid_ctrl = div | csiz [all...] |
/linux-master/drivers/clk/nxp/ |
H A D | clk-lpc18xx-ccu.c | 207 struct clk_divider *div = NULL; local 211 div = kzalloc(sizeof(*div), GFP_KERNEL); 212 if (!div) 215 div->reg = branch->offset + reg_base; 216 div->flags = CLK_DIVIDER_READ_ONLY; 217 div->shift = 27; 218 div->width = 1; 220 div_hw = &div->hw; 232 kfree(div); [all...] |