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d5252d96 |
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28-Sep-2023 |
Dirk Behme <dirk.behme@de.bosch.com> |
clk: renesas: rcar-gen3: Extend SDnH divider table The clock dividers might be used with clock stop bit enabled or not. Current tables only support recommended values from the datasheet. This might result in warnings like below because no valid clock divider is found. Resulting in a 0 divider. There are Renesas ARM Trusted Firmware version out there which e.g. configure 0x201 (shifted logical right by 2: 0x80) and with this match the added { STPnHCK | 0, 1 }: https://github.com/renesas-rcar/arm-trusted-firmware/blob/rcar_gen3_v2.3/drivers/renesas/rcar/emmc/emmc_init.c#L108 ------------[ cut here ]------------ sd1h: Zero divisor and CLK_DIVIDER_ALLOW_ZERO not set WARNING: CPU: 1 PID: 1 at drivers/clk/clk-divider.c:141 divider_recalc_rate+0x48/0x70 Modules linked in: CPU: 1 PID: 1 Comm: swapper/0 Not tainted 6.1.52 #1 Hardware name: Custom board based on r8a7796 (DT) pstate: 40000005 (nZcv daif -PAN -UAO -TCO -DIT -SSBS BTYPE=--) pc : divider_recalc_rate+0x48/0x70 ... ------------[ cut here ]------------ Fixes: bb6d3fa98a41 ("clk: renesas: rcar-gen3: Switch to new SD clock handling") Signed-off-by: Dirk Behme <dirk.behme@de.bosch.com> [wsa: extended the table to 5 entries, added comments, reword commit message a little] Signed-off-by: Wolfram Sang <wsa+renesas@sang-engineering.com> Tested-by: Dirk Behme <dirk.behme@de.bosch.com> Reviewed-by: Geert Uytterhoeven <geert+renesas@glider.be> Link: https://lore.kernel.org/r/20230928080317.28224-1-wsa+renesas@sang-engineering.com Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
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bb6d3fa9 |
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10-Nov-2021 |
Wolfram Sang <wsa+renesas@sang-engineering.com> |
clk: renesas: rcar-gen3: Switch to new SD clock handling The old SD handling code was huge and could not handle all the details which showed up on R-Car Gen3 SoCs meanwhile. It is time to switch to another design. Have SDnH a separate clock, use the existing divider clocks and move the errata handling from the clock driver to the SDHI driver where it belongs. This patch removes the old SD handling code and switch to the new one. This updates the SDHI driver at the same time. Because the SDHI driver can only communicate with the clock driver via clk_set_rate(), I don't see an alternative to this flag-day-approach, so we cross subsystems here. The patch sadly looks messy for the CPG lib, but it is basically a huge chunk of code removed and smaller chunks added. It looks much better when you just view the resulting source file. Signed-off-by: Wolfram Sang <wsa+renesas@sang-engineering.com> Acked-by: Ulf Hansson <ulf.hansson@linaro.org> # For MMC Link: https://lore.kernel.org/r/20211110191610.5664-6-wsa+renesas@sang-engineering.com Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
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a31cf51b |
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10-Nov-2021 |
Wolfram Sang <wsa+renesas@sang-engineering.com> |
clk: renesas: rcar-gen3: Add dummy SDnH clock Currently, SDnH is handled together with SDn. This caused lots of problems, so we want SDnH as a separate clock. Introduce a dummy SDnH type here which creates a fixed-factor clock with factor 1. That allows us to convert the per-SoC CPG drivers while keeping the old behaviour for now. A later patch then will add the proper functionality. Signed-off-by: Wolfram Sang <wsa+renesas@sang-engineering.com> Link: https://lore.kernel.org/r/20211110191610.5664-2-wsa+renesas@sang-engineering.com Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
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6f21d145 |
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06-Oct-2021 |
Wolfram Sang <wsa+renesas@sang-engineering.com> |
clk: renesas: cpg-lib: Move RPC clock registration to the library We want to reuse this code for V3U soon. Because its RPCCKCR register is at a different offset, the moved functions do not use the base register as an argument anymore but the RPCCKCR register itself. Verified that an Eagle board with R-Car V3M still works. Signed-off-by: Wolfram Sang <wsa+renesas@sang-engineering.com> Link: https://lore.kernel.org/r/20211006085836.42155-2-wsa+renesas@sang-engineering.com Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
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f2fb4fe6 |
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26-Mar-2021 |
Geert Uytterhoeven <geert+renesas@glider.be> |
clk: renesas: Zero init clk_init_data As clk_core_populate_parent_map() checks clk_init_data.num_parents first, and checks clk_init_data.parent_names[] before clk_init_data.parent_data[] and clk_init_data.parent_hws[], leaving the latter uninitialized doesn't do harm for now. However, it is better to play it safe, and initialize all clk_init_data structures to zeroes, to avoid any current and future members containing uninitialized data. Remove a few explicit zero initializers, which are now superfluous. Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be> Acked-by: Stephen Boyd <sboyd@kernel.org> Link: https://lore.kernel.org/r/20210326105434.1574796-1-geert+renesas@glider.be
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8bb67d87 |
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27-Dec-2020 |
Wolfram Sang <wsa+renesas@sang-engineering.com> |
clk: renesas: rcar-gen3: Factor out CPG library R-Car V3U has a CPG different enough to not be a generic Gen3 CPG but similar enough to reuse code. Introduce a new CPG library, factor out the SD clock handling and hook it to the generic Gen3 CPG driver so we have an equal state. V3U will make use of it in the next patch then. Signed-off-by: Wolfram Sang <wsa+renesas@sang-engineering.com> Link: https://lore.kernel.org/r/20201227174202.40834-4-wsa+renesas@sang-engineering.com Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
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