1// SPDX-License-Identifier: GPL-2.0-only
2/*
3 * Copyright (c) 2019 MediaTek Inc.
4 *               James Liao <jamesjj.liao@mediatek.com>
5 *               Fabien Parent <fparent@baylibre.com>
6 *
7 * Copyright (c) 2023 Collabora, Ltd.
8 *               AngeloGioacchino Del Regno <angelogioacchino.delregno@collabora.com>
9 */
10
11#include <dt-bindings/clock/mt8516-clk.h>
12#include <linux/clk.h>
13#include <linux/of.h>
14#include <linux/platform_device.h>
15
16#include "clk-mtk.h"
17#include "clk-pll.h"
18
19#define MT8516_PLL_FMAX		(1502UL * MHZ)
20
21#define CON0_MT8516_RST_BAR	BIT(27)
22
23#define PLL_B(_id, _name, _reg, _pwr_reg, _en_mask, _flags, _pcwbits,	\
24			_pd_reg, _pd_shift, _tuner_reg, _pcw_reg,	\
25			_pcw_shift, _div_table) {			\
26		.id = _id,						\
27		.name = _name,						\
28		.reg = _reg,						\
29		.pwr_reg = _pwr_reg,					\
30		.en_mask = _en_mask,					\
31		.flags = _flags,					\
32		.rst_bar_mask = CON0_MT8516_RST_BAR,			\
33		.fmax = MT8516_PLL_FMAX,				\
34		.pcwbits = _pcwbits,					\
35		.pd_reg = _pd_reg,					\
36		.pd_shift = _pd_shift,					\
37		.tuner_reg = _tuner_reg,				\
38		.pcw_reg = _pcw_reg,					\
39		.pcw_shift = _pcw_shift,				\
40		.div_table = _div_table,				\
41	}
42
43#define PLL(_id, _name, _reg, _pwr_reg, _en_mask, _flags, _pcwbits,	\
44			_pd_reg, _pd_shift, _tuner_reg, _pcw_reg,	\
45			_pcw_shift)					\
46		PLL_B(_id, _name, _reg, _pwr_reg, _en_mask, _flags, _pcwbits, \
47			_pd_reg, _pd_shift, _tuner_reg, _pcw_reg, _pcw_shift, \
48			NULL)
49
50static const struct mtk_pll_div_table mmpll_div_table[] = {
51	{ .div = 0, .freq = MT8516_PLL_FMAX },
52	{ .div = 1, .freq = 1000000000 },
53	{ .div = 2, .freq = 604500000 },
54	{ .div = 3, .freq = 253500000 },
55	{ .div = 4, .freq = 126750000 },
56	{ } /* sentinel */
57};
58
59static const struct mtk_pll_data plls[] = {
60	PLL(CLK_APMIXED_ARMPLL, "armpll", 0x0100, 0x0110, 0, 0,
61	    21, 0x0104, 24, 0, 0x0104, 0),
62	PLL(CLK_APMIXED_MAINPLL, "mainpll", 0x0120, 0x0130, 0,
63	    HAVE_RST_BAR, 21, 0x0124, 24, 0, 0x0124, 0),
64	PLL(CLK_APMIXED_UNIVPLL, "univpll", 0x0140, 0x0150, 0x30000000,
65	    HAVE_RST_BAR, 7, 0x0144, 24, 0, 0x0144, 0),
66	PLL_B(CLK_APMIXED_MMPLL, "mmpll", 0x0160, 0x0170, 0, 0,
67	      21, 0x0164, 24, 0, 0x0164, 0, mmpll_div_table),
68	PLL(CLK_APMIXED_APLL1, "apll1", 0x0180, 0x0190, 0, 0,
69	    31, 0x0180, 1, 0x0194, 0x0184, 0),
70	PLL(CLK_APMIXED_APLL2, "apll2", 0x01A0, 0x01B0, 0, 0,
71	    31, 0x01A0, 1, 0x01B4, 0x01A4, 0),
72};
73
74static int clk_mt8516_apmixed_probe(struct platform_device *pdev)
75{
76	void __iomem *base;
77	struct clk_hw_onecell_data *clk_data;
78	struct device_node *node = pdev->dev.of_node;
79	struct device *dev = &pdev->dev;
80	int ret;
81
82	base = devm_platform_ioremap_resource(pdev, 0);
83	if (IS_ERR(base))
84		return PTR_ERR(base);
85
86	clk_data = mtk_devm_alloc_clk_data(dev, CLK_APMIXED_NR_CLK);
87	if (!clk_data)
88		return -ENOMEM;
89
90	ret = mtk_clk_register_plls(node, plls, ARRAY_SIZE(plls), clk_data);
91	if (ret)
92		return ret;
93
94	ret = of_clk_add_hw_provider(node, of_clk_hw_onecell_get, clk_data);
95	if (ret)
96		goto unregister_plls;
97
98	return 0;
99
100unregister_plls:
101	mtk_clk_unregister_plls(plls, ARRAY_SIZE(plls), clk_data);
102
103	return ret;
104}
105
106static const struct of_device_id of_match_clk_mt8516_apmixed[] = {
107	{ .compatible = "mediatek,mt8516-apmixedsys" },
108	{ /* sentinel */ }
109};
110MODULE_DEVICE_TABLE(of, of_match_clk_mt8516_apmixed);
111
112static struct platform_driver clk_mt8516_apmixed_drv = {
113	.probe = clk_mt8516_apmixed_probe,
114	.driver = {
115		.name = "clk-mt8516-apmixed",
116		.of_match_table = of_match_clk_mt8516_apmixed,
117	},
118};
119builtin_platform_driver(clk_mt8516_apmixed_drv)
120
121MODULE_DESCRIPTION("MediaTek MT8516 apmixedsys clocks driver");
122MODULE_LICENSE("GPL");
123