#
a96cbb14 |
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18-Jul-2023 |
Rob Herring <robh@kernel.org> |
clk: Explicitly include correct DT includes The DT of_device.h and of_platform.h date back to the separate of_platform_bus_type before it as merged into the regular platform bus. As part of that merge prepping Arm DT support 13 years ago, they "temporarily" include each other. They also include platform_device.h and of.h. As a result, there's a pretty much random mix of those include files used throughout the tree. In order to detangle these headers and replace the implicit includes with struct declarations, users need to explicitly include the correct includes. Acked-by: Dinh Nguyen <dinguyen@kernel.org> Acked-by: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org> # samsung Acked-by: Heiko Stuebner <heiko@sntech.de> #rockchip Acked-by: Chanwoo Choi <cw00.choi@samsung.com> Acked-by: Geert Uytterhoeven <geert+renesas@glider.be> Reviewed-by: AngeloGioacchino Del Regno <angelogioacchino.delregno@collabora.com> Reviewed-by: Luca Ceresoli <luca.ceresoli@bootlin.com> # versaclock5 Signed-off-by: Rob Herring <robh@kernel.org> Link: https://lore.kernel.org/r/20230718143156.1066339-1-robh@kernel.org Acked-by: Abel Vesa <abel.vesa@linaro.org> #imx Signed-off-by: Stephen Boyd <sboyd@kernel.org>
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#
4cbe6428 |
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05-May-2023 |
Maxime Ripard <mripard@kernel.org> |
clk: qoriq: Add a determine_rate hook The Qoriq mux clocks implement a mux with a set_parent hook, but doesn't provide a determine_rate implementation. This is a bit odd, since set_parent() is there to, as its name implies, change the parent of a clock. However, the most likely candidates to trigger that parent change are either the assigned-clock-parents device tree property or a call to clk_set_rate(), with determine_rate() figuring out which parent is the best suited for a given rate. The other trigger would be a call to clk_set_parent(), but it's far less used, and it doesn't look like there's any obvious user for that clock. Similarly, it doesn't look like the device tree using that clock driver uses any of the assigned-clock properties on that clock. So, the set_parent hook is effectively unused, possibly because of an oversight. However, it could also be an explicit decision by the original author to avoid any reparenting but through an explicit call to clk_set_parent(). The latter case would be equivalent to setting the determine_rate implementation to clk_hw_determine_rate_no_reparent(). Indeed, if no determine_rate implementation is provided, clk_round_rate() (through clk_core_round_rate_nolock()) will call itself on the parent if CLK_SET_RATE_PARENT is set, and will not change the clock rate otherwise. And if it was an oversight, then we are at least explicit about our behavior now and it can be further refined down the line. Signed-off-by: Maxime Ripard <maxime@cerno.tech> Link: https://lore.kernel.org/r/20221018-clk-range-checks-fixes-v4-18-971d5077e7d2@cerno.tech Signed-off-by: Stephen Boyd <sboyd@kernel.org>
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#
a8ea4273 |
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28-Jun-2022 |
Liang He <windhl@126.com> |
clk: qoriq: Hold reference returned by of_get_parent() In legacy_init_clockgen(), we need to hold the reference returned by of_get_parent() and use it to call of_node_put() for refcount balance. Beside, in create_sysclk(), we need to call of_node_put() on 'sysclk' also for refcount balance. Fixes: 0dfc86b3173f ("clk: qoriq: Move chip-specific knowledge into driver") Signed-off-by: Liang He <windhl@126.com> Link: https://lore.kernel.org/r/20220628143851.171299-1-windhl@126.com Signed-off-by: Stephen Boyd <sboyd@kernel.org>
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#
fa4dd53e |
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25-Jan-2021 |
Wasim Khan <wasim.khan@nxp.com> |
clk: qoriq: use macros to generate pll_mask Use macros to generate pll_mask to make code more readable. Signed-off-by: Wasim Khan <wasim.khan@nxp.com> Link: https://lore.kernel.org/r/20210125142513.3919014-1-wasim.khan@oss.nxp.com Signed-off-by: Stephen Boyd <sboyd@kernel.org>
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#
4cb15934 |
|
08-Nov-2020 |
Michael Walle <michael@walle.cc> |
clk: qoriq: provide constants for the type To avoid future mistakes in the device tree for the clockgen module, add constants for the clockgen subtype as well as a macro for the PLL divider. Signed-off-by: Michael Walle <michael@walle.cc> Acked-by: Rob Herring <robh@kernel.org> Link: https://lore.kernel.org/r/20201108185113.31377-4-michael@walle.cc Signed-off-by: Stephen Boyd <sboyd@kernel.org>
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#
e9501b97 |
|
15-Sep-2020 |
Zhao Qiang <qiang.zhao@nxp.com> |
clk: qoriq: modify MAX_PLL_DIV to 32 On LS2088A, Watchdog need clk divided by 32, so modify MAX_PLL_DIV to 32 Signed-off-by: Zhao Qiang <qiang.zhao@nxp.com> Link: https://lore.kernel.org/r/20200916030311.17280-1-qiang.zhao@nxp.com Signed-off-by: Stephen Boyd <sboyd@kernel.org>
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#
92df3a9b |
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10-Jun-2020 |
Michael Krummsdorf <michael.krummsdorf@tq-group.com> |
clk: qoriq: add LS1021A core pll mux options This allows to clock the cores with 1 GHz, 500 MHz and 250 MHz. Signed-off-by: Michael Krummsdorf <michael.krummsdorf@tq-group.com> Signed-off-by: Matthias Schiffer <matthias.schiffer@ew.tq-group.com> Link: https://lore.kernel.org/r/20200610113837.27117-1-matthias.schiffer@ew.tq-group.com Signed-off-by: Stephen Boyd <sboyd@kernel.org>
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#
cf1e0449 |
|
21-Apr-2020 |
Mian Yousaf Kaukab <ykaukab@suse.de> |
clk: qoriq: add cpufreq platform device Add a platform device for qoirq-cpufreq driver for the compatible clockgen blocks. Reviewed-by: Yuantian Tang <andy.tang@nxp.com> Acked-by: Viresh Kumar <viresh.kumar@linaro.org> Signed-off-by: Mian Yousaf Kaukab <ykaukab@suse.de> Acked-by: Stephen Boyd <sboyd@kernel.org> Signed-off-by: Viresh Kumar <viresh.kumar@linaro.org>
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#
a932872f |
|
16-Dec-2019 |
Yangbo Lu <yangbo.lu@nxp.com> |
clk: qoriq: add ls1088a hwaccel clocks support This patch is to add hwaccel clocks information for ls1088a. Signed-off-by: Yangbo Lu <yangbo.lu@nxp.com> Link: https://lkml.kernel.org/r/20191216100111.17122-1-yangbo.lu@nxp.com Signed-off-by: Stephen Boyd <sboyd@kernel.org>
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#
a95fb581 |
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27-Jun-2019 |
Nathan Huckleberry <nhuck@google.com> |
clk: qoriq: Fix -Wunused-const-variable drivers/clk/clk-qoriq.c:138:38: warning: unused variable 'p5020_cmux_grp1' [-Wunused-const-variable] static const struct clockgen_muxinfo p5020_cmux_grp1 drivers/clk/clk-qoriq.c:146:38: warning: unused variable 'p5020_cmux_grp2' [-Wunused-const-variable] static const struct clockgen_muxinfo p5020_cmux_grp2 In the definition of the p5020 chip, the p2041 chip's info was used instead. The p5020 and p2041 chips have different info. This is most likely a typo. Link: https://github.com/ClangBuiltLinux/linux/issues/525 Cc: clang-built-linux@googlegroups.com Signed-off-by: Nathan Huckleberry <nhuck@google.com> Link: https://lkml.kernel.org/r/20190627220642.78575-1-nhuck@google.com Reviewed-by: Nick Desaulniers <ndesaulniers@google.com> Acked-by: Scott Wood <oss@buserror.net> Signed-off-by: Stephen Boyd <sboyd@kernel.org>
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#
78a5ba8f |
|
26-Apr-2019 |
Vabhav Sharma <vabhav.sharma@nxp.com> |
clk: qoriq: add support for lx2160a Add clockgen support and configuration for NXP SoC lx2160a with compatible property as "fsl,lx2160a-clockgen". Signed-off-by: Tang Yuantian <andy.tang@nxp.com> Signed-off-by: Yogesh Gaur <yogeshnarayan.gaur@nxp.com> Signed-off-by: Vabhav Sharma <vabhav.sharma@nxp.com> Acked-by: Scott Wood <oss@buserror.net> Acked-by: Stephen Boyd <sboyd@kernel.org> Acked-by: Viresh Kumar <viresh.kumar@linaro.org> Signed-off-by: Stephen Boyd <sboyd@kernel.org>
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#
d2912cb1 |
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04-Jun-2019 |
Thomas Gleixner <tglx@linutronix.de> |
treewide: Replace GPLv2 boilerplate/reference with SPDX - rule 500 Based on 2 normalized pattern(s): this program is free software you can redistribute it and or modify it under the terms of the gnu general public license version 2 as published by the free software foundation this program is free software you can redistribute it and or modify it under the terms of the gnu general public license version 2 as published by the free software foundation # extracted by the scancode license scanner the SPDX license identifier GPL-2.0-only has been chosen to replace the boilerplate/reference in 4122 file(s). Signed-off-by: Thomas Gleixner <tglx@linutronix.de> Reviewed-by: Enrico Weigelt <info@metux.net> Reviewed-by: Kate Stewart <kstewart@linuxfoundation.org> Reviewed-by: Allison Randal <allison@lohutok.net> Cc: linux-spdx@vger.kernel.org Link: https://lkml.kernel.org/r/20190604081206.933168790@linutronix.de Signed-off-by: Greg Kroah-Hartman <gregkh@linuxfoundation.org>
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#
42614b5b |
|
25-Apr-2019 |
Yogesh Gaur <yogeshnarayan.gaur@nxp.com> |
clk: qoriq: increase array size of cmux_to_group Increase size of cmux_to_group array, to accomdate entry of -1 termination. Added -1, terminated, entry for 4080_cmux_grpX. Signed-off-by: Yogesh Gaur <yogeshnarayan.gaur@nxp.com> Signed-off-by: Vabhav Sharma <vabhav.sharma@nxp.com> Acked-by: Scott Wood <oss@buserror.net> Signed-off-by: Stephen Boyd <sboyd@kernel.org>
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#
95089f6a |
|
23-Apr-2019 |
Yuantian Tang <andy.tang@nxp.com> |
clk: qoriq: Add ls1028a clock configuration Enable clock driver by adding clock configuration for ls1028a chip. Signed-off-by: Yuantian Tang <andy.tang@nxp.com> Signed-off-by: Stephen Boyd <sboyd@kernel.org>
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#
cc61ab9b |
|
22-Apr-2019 |
Yuantian Tang <andy.tang@nxp.com> |
clk: qoriq: add more PLL divider clocks support More PLL divider clocks are needed by clock consumer IP. So enlarge the PLL divider array to accommodate more divider clocks. Signed-off-by: Yuantian Tang <andy.tang@nxp.com> Signed-off-by: Stephen Boyd <sboyd@kernel.org>
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#
8f99f5ea |
|
17-Feb-2019 |
Dan Carpenter <dan.carpenter@oracle.com> |
clk: qoriq: Improve an error message We intended to print "ret" but there is a copy and paste bug from the previous error message. Signed-off-by: Dan Carpenter <dan.carpenter@oracle.com> Signed-off-by: Stephen Boyd <sboyd@kernel.org>
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#
70af6c5b |
|
26-Dec-2018 |
Yangtao Li <tiny.windzz@gmail.com> |
clk: qoriq: fix refcount leak in clockgen_init() The of_find_compatible_node() returns a node pointer with refcount incremented, but there is the lack of use of the of_node_put() when done. Add the missing of_node_put() to release the refcount. Signed-off-by: Yangtao Li <tiny.windzz@gmail.com> Fixes: 0dfc86b3173f ("clk: qoriq: Move chip-specific knowledge into driver") Signed-off-by: Stephen Boyd <sboyd@kernel.org>
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#
b8b211ca |
|
31-Oct-2018 |
Yuantian Tang <andy.tang@nxp.com> |
clk: qoriq: add more chips support Add more chip-specific compatible strings to support more Socs. Signed-off-by: Yuantian Tang <andy.tang@nxp.com> Signed-off-by: Stephen Boyd <sboyd@kernel.org>
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#
e665f029 |
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28-Aug-2018 |
Rob Herring <robh@kernel.org> |
clk: Convert to using %pOFn instead of device_node.name In preparation to remove the node name pointer from struct device_node, convert printf users to use the %pOFn format specifier. Cc: Eugeniy Paltsev <Eugeniy.Paltsev@synopsys.com> Cc: Michael Turquette <mturquette@baylibre.com> Cc: Stephen Boyd <sboyd@kernel.org> Cc: linux-clk@vger.kernel.org Cc: linux-arm-kernel@lists.infradead.org Cc: linux-renesas-soc@vger.kernel.org Cc: linux-omap@vger.kernel.org Signed-off-by: Rob Herring <robh@kernel.org> Signed-off-by: Stephen Boyd <sboyd@kernel.org>
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#
36ab0467 |
|
21-Nov-2017 |
Yuantian Tang <andy.tang@nxp.com> |
clk: qoriq: add more divider clocks support More divider clocks are needed by IP. So enlarge the PLL divider array to accommodate more divider clocks. Signed-off-by: Tang Yuantian <andy.tang@nxp.com> Acked-by: Rob Herring <robh@kernel.org> Signed-off-by: Stephen Boyd <sboyd@codeaurora.org>
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#
16673931 |
|
18-Jul-2017 |
Rob Herring <robh@kernel.org> |
clk: Convert to using %pOF instead of full_name Now that we have a custom printf format specifier, convert users of full_name to use %pOF instead. This is preparation to remove storing of the full path string for each node. Signed-off-by: Rob Herring <robh@kernel.org> Cc: Michael Turquette <mturquette@baylibre.com> Cc: Stephen Boyd <sboyd@codeaurora.org> Cc: Maxime Coquelin <mcoquelin.stm32@gmail.com> Cc: Alexandre Torgue <alexandre.torgue@st.com> Cc: Russell King <linux@armlinux.org.uk> Cc: Matthias Brugger <matthias.bgg@gmail.com> Cc: Geert Uytterhoeven <geert+renesas@glider.be> Cc: Maxime Ripard <maxime.ripard@free-electrons.com> Cc: Chen-Yu Tsai <wens@csie.org> Cc: "Emilio López" <emilio@elopez.com.ar> Cc: Peter De Schrijver <pdeschrijver@nvidia.com> Cc: Prashant Gaikwad <pgaikwad@nvidia.com> Cc: Thierry Reding <thierry.reding@gmail.com> Cc: Jonathan Hunter <jonathanh@nvidia.com> Cc: Tero Kristo <t-kristo@ti.com> Cc: linux-clk@vger.kernel.org Cc: linux-arm-kernel@lists.infradead.org Cc: linux-mediatek@lists.infradead.org Cc: linux-renesas-soc@vger.kernel.org Cc: linux-tegra@vger.kernel.org Cc: linux-omap@vger.kernel.org Acked-by: Maxime Ripard <maxime.ripard@free-electrons.com> Reviewed-by: Geert Uytterhoeven <geert+renesas@glider.be> Acked-by: Geert Uytterhoeven <geert+renesas@glider.be> Acked-by: James Liao <jamesjj.liao@mediatek.com> Acked-by: Alexandre TORGUE <alexandre.torgue@st.com> Reviewed-by: Matthias Brugger <matthias.bgg@gmail.com> Signed-off-by: Stephen Boyd <sboyd@codeaurora.org>
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#
45899dc5 |
|
05-Apr-2017 |
Yuantian Tang <andy.tang@nxp.com> |
clk: qoriq: add pll clock to clock lookup table Register each PLL and its division clocks to clock lookup table to facilitate the clock look up for clock consumer. Signed-off-by: Tang Yuantian <andy.tang@nxp.com> Signed-off-by: Stephen Boyd <sboyd@codeaurora.org>
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#
e0c888c4 |
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05-Apr-2017 |
Yuantian Tang <andy.tang@nxp.com> |
clk: qoriq: add clock configuration for ls1088a soc Clock on ls1088a chip takes primary clocking input from the external SYSCLK signal. The SYSCLK input (frequency) is multiplied using multiple phase locked loops (PLL) to create a variety of frequencies which can then be passed to a variety of internal logic, including cores and peripheral IP modules. Signed-off-by: Tang Yuantian <andy.tang@nxp.com> Signed-off-by: Stephen Boyd <sboyd@codeaurora.org>
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#
80b4ae7a |
|
19-Mar-2017 |
Scott Wood <oss@buserror.net> |
clk: qoriq: Separate root input clock for core PLLs on ls1012a ls1012a has separate input root clocks for core PLLs versus the platform PLL, with the latter described as sysclk in the hw docs. If a second input clock, named "coreclk", is present, this clock will be used for the core PLLs. Signed-off-by: Scott Wood <oss@buserror.net> Signed-off-by: Tang Yuantian <andy.tang@nxp.com> Acked-by: Rob Herring <robh@kernel.org> Signed-off-by: Stephen Boyd <sboyd@codeaurora.org>
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#
44709358 |
|
23-Nov-2016 |
Tang Yuantian <Yuantian.Tang@nxp.com> |
clk: qoriq: added ls1012a clock configuration Acked-by: Scott Wood <oss@buserror.net> Signed-off-by: Tang Yuantian <yuantian.tang@nxp.com> [sboyd@codeaurora.org: Sorted list] Signed-off-by: Stephen Boyd <sboyd@codeaurora.org>
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#
80e52198 |
|
06-Sep-2016 |
Mingkai Hu <mingkai.hu@nxp.com> |
clk: qoriq: add ls1046a support Signed-off-by: Mingkai Hu <mingkai.hu@nxp.com> Signed-off-by: Shaohui Xie <Shaohui.Xie@nxp.com> Signed-off-by: Stephen Boyd <sboyd@codeaurora.org>
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#
7c1c5413 |
|
17-Oct-2016 |
Scott Wood <oss@buserror.net> |
clk: qoriq: Don't allow CPU clocks higher than starting value The boot-time frequency of a CPU is considered its rated maximum, as we have no other source of such information. However, this was previously only used for chips with 80% restrictions on secondary PLLs. This usually wasn't a problem because most chips/configs boot with a divider of /1, with other dividers being used only for dynamic frequency reduction. However, at least one config (LS1021A at less than 1 GHz) uses a different divider for top speed. This was causing cpufreq to set a frequency beyond the chip's rated speed. This is fixed by applying a 100%-of-initial-speed limit to all CPU PLLs, similar to the existing 80% limit that only applied to some. Signed-off-by: Scott Wood <oss@buserror.net> Cc: stable@vger.kernel.org Signed-off-by: Stephen Boyd <sboyd@codeaurora.org>
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#
8964193f |
|
15-Aug-2016 |
Tang Yuantian <Yuantian.Tang@nxp.com> |
clk: qoriq: fix a register offset error The offset of Core Cluster clock control/status register on cluster group V3 version is different from others, and should be plus 0x70000. Signed-off-by: Tang Yuantian <yuantian.tang@nxp.com> Reviewed-by: Scott Wood <oss@buserror.net> Fixes: 9e19ca2f627e ("clk: qoriq: Add ls2080a support.") Signed-off-by: Stephen Boyd <sboyd@codeaurora.org>
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#
3432a2e3 |
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18-Apr-2016 |
Julia Lawall <Julia.Lawall@lip6.fr> |
clk: qoriq: add __init attribute Add __init attribute on a function that is only called from other __init functions and that is not inlined, at least with gcc version 4.8.4 on an x86 machine with allyesconfig. Currently, the function is put in the .text.unlikely segment. Declaring it as __init will cause it to be put in the .init.text and to disappear after initialization. The result of objdump -x on the function before the change is as follows: 0000000000000000 l F .text.unlikely 0000000000000071 sysclk_from_fixed.constprop.5 And after the change it is as follows: 0000000000000480 l F .init.text 000000000000006c sysclk_from_fixed.constprop.5 Done with the help of Coccinelle. The semantic patch checks for local static non-init functions that are called from an __init function and are not called from any other function. Signed-off-by: Julia Lawall <Julia.Lawall@lip6.fr> Signed-off-by: Stephen Boyd <sboyd@codeaurora.org>
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#
ec3f2fcb |
|
01-Mar-2016 |
Stephen Boyd <sboyd@codeaurora.org> |
clk: qoriq: Remove CLK_IS_ROOT This flag is a no-op now. Remove usage of the flag. Cc: Hou Zhiqiang <B48286@freescale.com> Cc: Scott Wood <scottwood@freescale.com> Signed-off-by: Stephen Boyd <sboyd@codeaurora.org>
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#
279104e3 |
|
23-Nov-2015 |
Sudip Mukherjee <sudipm.mukherjee@gmail.com> |
clk: qoriq: fix memory leak If get_pll_div() fails we exited by returning NULL but we missed releasing hwc. Signed-off-by: Sudip Mukherjee <sudip@vectorindia.org> Fixes: 0dfc86b3173f ("clk: qoriq: Move chip-specific knowledge into driver") Signed-off-by: Stephen Boyd <sboyd@codeaurora.org>
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#
e994412c |
|
23-Oct-2015 |
Hou Zhiqiang <B48286@freescale.com> |
clk: qoriq: Add ls1043a support. Signed-off-by: Hou Zhiqiang <B48286@freescale.com> Acked-by: Stephen Boyd <sboyd@codeaurora.org> Signed-off-by: Scott Wood <scottwood@freescale.com>
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#
2c7693e0 |
|
22-Oct-2015 |
Scott Wood <scottwood@freescale.com> |
clk: qoriq: Fix wrong data in p2041_cmux_grp2 Signed-off-by: Scott Wood <scottwood@freescale.com>
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#
9e19ca2f |
|
19-Sep-2015 |
Scott Wood <scottwood@freescale.com> |
clk: qoriq: Add ls2080a support. LS2080A is the first implementation of the chassis 3 clockgen, which has a different register layout than previous chips. It is also little endian, unlike previous chips. Signed-off-by: Scott Wood <scottwood@freescale.com> Acked-by: Stephen Boyd <sboyd@codeaurora.org>
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#
0dfc86b3 |
|
19-Sep-2015 |
Scott Wood <scottwood@freescale.com> |
clk: qoriq: Move chip-specific knowledge into driver The device tree should describe the chips (or chip-like subblocks) in the system, but it generally does not describe individual registers -- it should identify, rather than describe, a programming interface. This has not been the case with the QorIQ clockgen nodes. The knowledge of what each bit setting of CLKCnCSR means is encoded in three places (binding, pll node, and mux node), and the last also needs to know which options are valid on a particular chip. All three of these locations are considered stable ABI, making it difficult to fix mistakes (of which I have found several), much less refactor the abstraction to be able to address problems, limitations, or new chips. Under the current binding, a pll clock specifier of 2 means that the PLL is divided by 4 -- and the driver implements this, unless there happen to be four clock-output-names rather than 3, in which case it interprets it as PLL divided by 3. This does not appear in the binding documentation at all. That hack is now considered stable ABI. The current device tree nodes contain errors, such as saying that T1040 can set a core clock to PLL/4 when only PLL and PLL/2 are options. The current binding also ignores some restrictions on clock selection, such as p5020's requirement that if a core uses the "wrong" PLL, that PLL must be clocked lower than the "correct" PLL and be at most 80% of the rated CPU frequency. Possibly because of the lack of the ability to express such nuance in the binding, some valid options are omitted from the device trees, such as the ability on p4080 to run cores 0-3 from PLL3 and cores 4-7 from PLL1 (again, only if they are at most 80% of rated CPU frequency). This omission, combined with excessive caution in the cpufreq driver (addressed in a subsequent patch), means that currently on a 1500 MHz p4080 with typical PLL configuration, cpufreq can lower the frequency to 1200 MHz on half the CPUs and do nothing on the others. With this patchset, all CPUs can be lowered to 1200 MHz on a rev2 p4080, and on a rev3 p4080 half can be lowered to 750 MHz and the other half to 600 MHz. The current binding only deals with CPU clocks. To describe FMan in the device tree, we need to describe its clock. Some chips have additional muxes that work like the CPU muxes, but are not described in the device tree. Others require inspecting the Reset Control Word to determine which PLL is used. Rather than continue to extend this mess, replace it. Have the driver bind to the chip-specific clockgen compatible, and keep the detailed description of quirky chip variations in the driver, where it can be easily fixed, refactored, and extended. Older device trees will continue to work (including a workaround for old ls1021a device trees that are missing compatible and reg in the clockgen node, which even the old binding required). The pll/mux details in old device trees will be ignored, but "clocks" properties pointing at the old nodes will still work, and be directed at the corresponding new clock. Signed-off-by: Scott Wood <scottwood@freescale.com> Acked-by: Stephen Boyd <sboyd@codeaurora.org>
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#
a513b72c |
|
21-Jan-2015 |
Emil Medve <Emilian.Medve@Freescale.com> |
clk: qoriq: Add support for the platform PLL Change-Id: Iac11ed95f274485a86d2c11f32a3dc502bcd020f Signed-off-by: Emil Medve <Emilian.Medve@Freescale.com> Acked-by: Tang Yuantian <Yuantian.Tang@freescale.com> Signed-off-by: Michael Turquette <mturquette@linaro.org>
|
#
c88b2b66 |
|
21-Jan-2015 |
Emil Medve <Emilian.Medve@Freescale.com> |
clk: qoriq: Use pr_fmt() Currently a mix of clk-qoriq/qoriq-clk and no prefix is used Signed-off-by: Emil Medve <Emilian.Medve@Freescale.com> Signed-off-by: Michael Turquette <mturquette@linaro.org>
|
#
6ef1ccac |
|
21-Jan-2015 |
Emil Medve <Emilian.Medve@Freescale.com> |
clk: qoriq: Replace kzalloc() with kmalloc() Where the memset() is not necessary Signed-off-by: Emil Medve <Emilian.Medve@Freescale.com> Signed-off-by: Michael Turquette <mturquette@linaro.org>
|
#
334680dd |
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21-Jan-2015 |
Emil Medve <Emilian.Medve@Freescale.com> |
clk: qoriq: Make local symbol 'static' drivers/clk/clk-qoriq.c:59:22: warning: symbol 'cmux_ops' was not declared. Should it be static? Signed-off-by: Emil Medve <Emilian.Medve@Freescale.com> Signed-off-by: Michael Turquette <mturquette@linaro.org>
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8002cab6 |
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21-Jan-2015 |
Emil Medve <Emilian.Medve@Freescale.com> |
clk: qoriq: Fix checkpatch type OOM_MESSAGE WARNING:OOM_MESSAGE: Possible unnecessary 'out of memory' message + if (!parent_names) { + pr_err("%s: could not allocate parent_names\n", __func__); WARNING:OOM_MESSAGE: Possible unnecessary 'out of memory' message + if (!cmux_clk) { + pr_err("%s: could not allocate cmux_clk\n", __func__); WARNING:OOM_MESSAGE: Possible unnecessary 'out of memory' message + if (!subclks) { + pr_err("%s: could not allocate subclks\n", __func__); WARNING:OOM_MESSAGE: Possible unnecessary 'out of memory' message + if (!onecell_data) { + pr_err("%s: could not allocate onecell_data\n", __func__); Signed-off-by: Emil Medve <Emilian.Medve@Freescale.com> Signed-off-by: Michael Turquette <mturquette@linaro.org>
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13c25f57 |
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21-Jan-2015 |
Emil Medve <Emilian.Medve@Freescale.com> |
clk: qoriq: Fix checkpatch type ALLOC_SIZEOF_STRUCT CHECK:ALLOC_SIZEOF_STRUCT: Prefer kzalloc(sizeof(*cmux_clk)...) over kzalloc(sizeof(struct cmux_clk)...) + cmux_clk = kzalloc(sizeof(struct cmux_clk), GFP_KERNEL); CHECK:ALLOC_SIZEOF_STRUCT: Prefer kzalloc(sizeof(*onecell_data)...) over kzalloc(sizeof(struct clk_onecell_data)...) + onecell_data = kzalloc(sizeof(struct clk_onecell_data), GFP_KERNEL); Signed-off-by: Emil Medve <Emilian.Medve@Freescale.com> Signed-off-by: Michael Turquette <mturquette@linaro.org>
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a9247225 |
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21-Jan-2015 |
Emil Medve <Emilian.Medve@Freescale.com> |
clk: qoriq: Fix checkpatch type ALLOC_WITH_MULTIPLY WARNING:ALLOC_WITH_MULTIPLY: Prefer kcalloc over kzalloc with multiply + subclks = kzalloc(sizeof(struct clk *) * count, GFP_KERNEL); Signed-off-by: Emil Medve <Emilian.Medve@Freescale.com> Signed-off-by: Michael Turquette <mturquette@linaro.org>
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78f4a63e |
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21-Jan-2015 |
Emil Medve <Emilian.Medve@Freescale.com> |
clk: qoriq: Fix checkpatch type PARENTHESIS_ALIGNMENT CHECK:PARENTHESIS_ALIGNMENT: Alignment should match open parenthesis + rc = of_property_read_string_index(np, "clock-output-names", + 0, &clk_name); CHECK:PARENTHESIS_ALIGNMENT: Alignment should match open parenthesis + pr_err("Could not register clock provider for node:%s\n", + np->name); CHECK:PARENTHESIS_ALIGNMENT: Alignment should match open parenthesis + rc = of_property_read_string_index(np, "clock-output-names", + i, &clk_name); CHECK:PARENTHESIS_ALIGNMENT: Alignment should match open parenthesis + pr_err("Could not register clk provider for node:%s\n", + np->name); Signed-off-by: Emil Medve <Emilian.Medve@Freescale.com> Signed-off-by: Michael Turquette <mturquette@linaro.org>
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93a17c05 |
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14-Jan-2015 |
Tang Yuantian <Yuantian.Tang@freescale.com> |
clk: ppc-corenet: rename driver to clk-qoriq Freescale introduced new ARM-based socs which using the compatible clock IP block with PowerPC-based socs'. So this driver can be used on both platforms. Updated relevant descriptions and renamed this driver to better represent its meaning and keep the function of driver untouched. Signed-off-by: Tang Yuantian <Yuantian.Tang@freescale.com> Signed-off-by: Michael Turquette <mturquette@linaro.org>
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