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00bd581b |
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14-Jun-2023 |
Claudiu Beznea <claudiu.beznea@microchip.com> |
clk: at91: clk-generated: add support for parent_hw Add support for parent_hw in generic clock drivers. With this parent-child relation is described with pointers rather than strings making registration a bit faster. All the SoC based drivers that rely on clk-generated were adapted to the new API change. The switch itself for SoCs will be done in subsequent patches. Signed-off-by: Claudiu Beznea <claudiu.beznea@microchip.com> Reviewed-by: Maxime Ripard <mripard@kernel.org> Link: https://lore.kernel.org/r/20230615093227.576102-3-claudiu.beznea@microchip.com
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#
262ca38f |
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16-Aug-2022 |
Maxime Ripard <maxime@cerno.tech> |
clk: Stop forwarding clk_rate_requests to the parent If the clock cannot modify its rate and has CLK_SET_RATE_PARENT, clk_mux_determine_rate_flags(), clk_core_round_rate_nolock() and a number of drivers will forward the clk_rate_request to the parent clock. clk_core_round_rate_nolock() will pass the pointer directly, which means that we pass a clk_rate_request to the parent that has the rate, min_rate and max_rate of the child, and the best_parent_rate and best_parent_hw fields will be relative to the child as well, so will point to our current clock and its rate. The most common case for CLK_SET_RATE_PARENT is that the child and parent clock rates will be equal, so the rate field isn't a worry, but the other fields are. Similarly, if the parent clock driver ever modifies the best_parent_rate or best_parent_hw, this will be applied to the child once the call to clk_core_round_rate_nolock() is done. best_parent_hw is probably not going to be a valid parent, and best_parent_rate might lead to a parent rate change different to the one that was initially computed. clk_mux_determine_rate_flags() and the affected drivers will copy the request before forwarding it to the parents, so they won't be affected by the latter issue, but the former is still going to be there and will lead to erroneous data and context being passed to the various clock drivers in the same sub-tree. Let's create two new functions, clk_core_forward_rate_req() and clk_hw_forward_rate_request() for the framework and the clock providers that will copy a request from a child clock and update the context to match the parent's. We also update the relevant call sites in the framework and drivers to use that new function. Let's also add a test to make sure we avoid regressions there. Tested-by: Alexander Stein <alexander.stein@ew.tq-group.com> # imx8mp Tested-by: Marek Szyprowski <m.szyprowski@samsung.com> # exynos4210, meson g12b Signed-off-by: Maxime Ripard <maxime@cerno.tech> Link: https://lore.kernel.org/r/20220816112530.1837489-22-maxime@cerno.tech Tested-by: Linux Kernel Functional Testing <lkft@linaro.org> Tested-by: Naresh Kamboju <naresh.kamboju@linaro.org> Signed-off-by: Stephen Boyd <sboyd@kernel.org>
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#
d0031e6f |
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13-Apr-2022 |
Codrin Ciubotariu <codrin.ciubotariu@microchip.com> |
clk: at91: generated: consider range when calculating best rate clk_generated_best_diff() helps in finding the parent and the divisor to compute a rate closest to the required one. However, it doesn't take into account the request's range for the new rate. Make sure the new rate is within the required range. Fixes: 8a8f4bf0c480 ("clk: at91: clk-generated: create function to find best_diff") Signed-off-by: Codrin Ciubotariu <codrin.ciubotariu@microchip.com> Link: https://lore.kernel.org/r/20220413071318.244912-1-codrin.ciubotariu@microchip.com Reviewed-by: Claudiu Beznea <claudiu.beznea@microchip.com> Signed-off-by: Stephen Boyd <sboyd@kernel.org>
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#
36971566 |
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11-Oct-2021 |
Claudiu Beznea <claudiu.beznea@microchip.com> |
clk: at91: re-factor clocks suspend/resume SAMA5D2 and SAMA7G5 have a special power saving mode (backup mode) where most of the SoC's components are powered off (including PMC). Resuming from this mode is done with the help of bootloader. Peripherals are not aware of the power saving mode thus most of them are disabling clocks in proper suspend API and re-enable them in resume API without taking into account the previously setup rate. Moreover some of the peripherals are acting as wakeup sources and are not disabling the clocks in this scenario, when suspending. Since backup mode cuts the power for peripherals, in resume part these clocks needs to be re-configured. The initial PMC suspend/resume code was designed only for SAMA5D2's PMC (as it was the only one supporting backup mode). SAMA7G supports also backup mode and its PMC is different (few new functionalities, different registers offsets, different offsets in registers for each functionalities). To address both SAMA5D2 and SAMA7G5 PMC add .save_context()/.resume_context() support to each clocks driver and call this from PMC driver. Signed-off-by: Claudiu Beznea <claudiu.beznea@microchip.com> Link: https://lore.kernel.org/r/20211011112719.3951784-2-claudiu.beznea@microchip.com Acked-by: Nicolas Ferre <nicolas.ferre@microchip.com> Signed-off-by: Stephen Boyd <sboyd@kernel.org>
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af7651e6 |
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07-Jul-2021 |
Codrin Ciubotariu <codrin.ciubotariu@microchip.com> |
clk: at91: clk-generated: Limit the requested rate to our range On clk_generated_determine_rate(), the requested rate could be outside of clk's range. Limit the rate to the clock's range to not return an error. Fixes: df70aeef6083 ("clk: at91: add generated clock driver") Signed-off-by: Codrin Ciubotariu <codrin.ciubotariu@microchip.com> Link: https://lore.kernel.org/r/20210707131213.3283509-1-codrin.ciubotariu@microchip.com Acked-by: Nicolas Ferre <nicolas.ferre@microchip.com> Signed-off-by: Stephen Boyd <sboyd@kernel.org>
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22a1dfe9 |
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22-Jul-2020 |
Claudiu Beznea <claudiu.beznea@microchip.com> |
clk: at91: clk-generated: add mux_table option Add mux table option. This is necessary for IP versions that has gaps in the range of available clock sources (e.g. SAMA7G5). Signed-off-by: Claudiu Beznea <claudiu.beznea@microchip.com> Link: https://lore.kernel.org/r/1595403506-8209-12-git-send-email-claudiu.beznea@microchip.com Signed-off-by: Stephen Boyd <sboyd@kernel.org>
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#
64c9247b |
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22-Jul-2020 |
Claudiu Beznea <claudiu.beznea@microchip.com> |
clk: at91: clk-generated: pass the id of changeable parent at registration Pass the ID of changeable parent at registration. This will allow the scalability of this clock driver with regards to the changeable parent ID for versions of this IP where changeable parent is not the last one in the parents list (e.g. SAMA7G5). With this the clock flags are set to zero in case we have no changeable parent. Also in clk_generated_best_diff() the *best_diff variable is check against tmp_diff variable using ">=" operator instead of ">" so that in case the requested frequency could be obtained using fix parents + gck dividers but the clock also supports changeable parent to be able to force the usage of the changeable parent. Signed-off-by: Claudiu Beznea <claudiu.beznea@microchip.com> Link: https://lore.kernel.org/r/1595403506-8209-11-git-send-email-claudiu.beznea@microchip.com Signed-off-by: Stephen Boyd <sboyd@kernel.org>
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42324d95 |
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22-Jul-2020 |
Claudiu Beznea <claudiu.beznea@microchip.com> |
clk: at91: replace conditional operator with double logical not Replace conditional operator with double logical not as code may be simpler to read. Signed-off-by: Claudiu Beznea <claudiu.beznea@microchip.com> Link: https://lore.kernel.org/r/1595403506-8209-10-git-send-email-claudiu.beznea@microchip.com Signed-off-by: Stephen Boyd <sboyd@kernel.org>
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#
83331bfc |
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22-Jul-2020 |
Claudiu Beznea <claudiu.beznea@microchip.com> |
clk: at91: clk-generated: check best_rate against ranges Check best_rate against available clock ranges. Fixes: df70aeef6083 ("clk: at91: add generated clock driver") Signed-off-by: Claudiu Beznea <claudiu.beznea@microchip.com> Reviewed-by: Alexandre Belloni <alexandre.belloni@bootlin.com> Link: https://lore.kernel.org/r/1595403506-8209-3-git-send-email-claudiu.beznea@microchip.com Signed-off-by: Stephen Boyd <sboyd@kernel.org>
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#
3a5c42b1 |
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22-Jul-2020 |
Claudiu Beznea <claudiu.beznea@microchip.com> |
clk: at91: clk-generated: continue if __clk_determine_rate() returns error __clk_determine_rate() may return error. Skip the current step in case of error. Fixes: 1a1a36d72e3d3 ("clk: at91: clk-generated: make gclk determine audio_pll rate") Signed-off-by: Claudiu Beznea <claudiu.beznea@microchip.com> Reviewed-by: Alexandre Belloni <alexandre.belloni@bootlin.com> Link: https://lore.kernel.org/r/1595403506-8209-2-git-send-email-claudiu.beznea@microchip.com Signed-off-by: Stephen Boyd <sboyd@kernel.org>
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#
1573eebe |
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24-Jun-2019 |
Codrin Ciubotariu <codrin.ciubotariu@microchip.com> |
clk: at91: generated: Truncate divisor to GENERATED_MAX_DIV + 1 In clk_generated_determine_rate(), if the divisor is greater than GENERATED_MAX_DIV + 1, then the wrong best_rate will be returned. If clk_generated_set_rate() will be called later with this wrong rate, it will return -EINVAL, so the generated clock won't change its value. Do no let the divisor be greater than GENERATED_MAX_DIV + 1. Fixes: 8c7aa6328947 ("clk: at91: clk-generated: remove useless divisor loop") Signed-off-by: Codrin Ciubotariu <codrin.ciubotariu@microchip.com> Acked-by: Nicolas Ferre <nicolas.ferre@microchip.com> Acked-by: Ludovic Desroches <ludovic.desroches@microchip.com> Signed-off-by: Stephen Boyd <sboyd@kernel.org>
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#
2874c5fd |
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27-May-2019 |
Thomas Gleixner <tglx@linutronix.de> |
treewide: Replace GPLv2 boilerplate/reference with SPDX - rule 152 Based on 1 normalized pattern(s): this program is free software you can redistribute it and or modify it under the terms of the gnu general public license as published by the free software foundation either version 2 of the license or at your option any later version extracted by the scancode license scanner the SPDX license identifier GPL-2.0-or-later has been chosen to replace the boilerplate/reference in 3029 file(s). Signed-off-by: Thomas Gleixner <tglx@linutronix.de> Reviewed-by: Allison Randal <allison@lohutok.net> Cc: linux-spdx@vger.kernel.org Link: https://lkml.kernel.org/r/20190527070032.746973796@linutronix.de Signed-off-by: Greg Kroah-Hartman <gregkh@linuxfoundation.org>
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e4cfb823 |
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02-Apr-2019 |
Alexandre Belloni <alexandre.belloni@bootlin.com> |
clk: at91: allow configuring generated PCR layout The PCR register layout for GCLKCSS is changing for the future SoCs, allow configuring it. Signed-off-by: Alexandre Belloni <alexandre.belloni@bootlin.com> Signed-off-by: Stephen Boyd <sboyd@kernel.org>
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#
62061d35 |
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16-Oct-2018 |
Alexandre Belloni <alexandre.belloni@bootlin.com> |
clk: at91: move DT compatibility code to its own file Move all the DT backward compatibility code to its own file so it can be deleted later. Signed-off-by: Alexandre Belloni <alexandre.belloni@bootlin.com> Signed-off-by: Stephen Boyd <sboyd@kernel.org>
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b2e39dc0 |
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16-Oct-2018 |
Alexandre Belloni <alexandre.belloni@bootlin.com> |
clk: at91: allow clock registration from C code Remove static keyword to allow functions to be used from other units. Also move some struct and function declarations to pmc.h Signed-off-by: Alexandre Belloni <alexandre.belloni@bootlin.com> [sboyd@kernel.org: Include pmc.h] Signed-off-by: Stephen Boyd <sboyd@kernel.org>
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#
c1e4580a |
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16-Oct-2018 |
Alexandre Belloni <alexandre.belloni@bootlin.com> |
clk: at91: generated: set audio_pll_allowed in at91_clk_register_generated() Set gck->audio_pll_allowed in at91_clk_register_generated. This makes it easier to do it from code that is not parsing device tree. Also, this fixes an issue where the resulting clk_hw can be dereferenced before being tested for error. Fixes: 1a1a36d72e3d ("clk: at91: clk-generated: make gclk determine audio_pll rate") Signed-off-by: Alexandre Belloni <alexandre.belloni@bootlin.com> Signed-off-by: Stephen Boyd <sboyd@kernel.org>
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#
6d631027 |
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16-Oct-2018 |
Alexandre Belloni <alexandre.belloni@bootlin.com> |
clk: at91: generated: SSCs don't have a gclk As the SSCs don't have gclk, don't check for their ID to allow them to set the audio pll rate. Signed-off-by: Alexandre Belloni <alexandre.belloni@bootlin.com> Signed-off-by: Stephen Boyd <sboyd@kernel.org>
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1a1a36d7 |
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10-Aug-2017 |
Quentin Schulz <quentin.schulz@free-electrons.com> |
clk: at91: clk-generated: make gclk determine audio_pll rate This allows gclk to determine audio_pll rate and set the parent rate accordingly. However, there are multiple children clocks that could technically change the rate of audio_pll (via gck). With the rate locking, the first consumer to enable the clock will be the one definitely setting the rate of the clock. Since audio IPs are most likely to request the same rate, we enforce that the only clks able to modify gck rate are those of audio IPs. To remain consistent, we deny other clocks to be children of audio_pll. Signed-off-by: Quentin Schulz <quentin.schulz@free-electrons.com> Acked-by: Boris Brezillon <boris.brezillon@free-electrons.com> Acked-by: Nicolas Ferre <nicolas.ferre@microchip.com> Signed-off-by: Stephen Boyd <sboyd@codeaurora.org>
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#
8a8f4bf0 |
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10-Aug-2017 |
Quentin Schulz <quentin.schulz@free-electrons.com> |
clk: at91: clk-generated: create function to find best_diff The way to find the best_diff and do the appropriate process afterwards can be re-used. This patch prepares the driver for an upcoming patch that will allow clk_generated to determine the rate of the audio_pll. Signed-off-by: Quentin Schulz <quentin.schulz@free-electrons.com> Acked-by: Boris Brezillon <boris.brezillon@free-electrons.com> Acked-by: Nicolas Ferre <nicolas.ferre@microchip.com> Signed-off-by: Stephen Boyd <sboyd@codeaurora.org>
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#
8c7aa632 |
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10-Aug-2017 |
Quentin Schulz <quentin.schulz@free-electrons.com> |
clk: at91: clk-generated: remove useless divisor loop The driver requests the current clk rate of each of its parent clocks to decide whether a clock rate is suitable or not. It does not request determine_rate from a parent clock which could request a rate change in parent clock (i.e. there is no parent rate propagation). We know the rate we want (passed along req argument of the function) and the parent clock rate, thus we know the closest rounded divisor, we don't need to iterate over the available divisors to find the best one for a given clock. Signed-off-by: Quentin Schulz <quentin.schulz@free-electrons.com> Acked-by: Boris Brezillon <boris.brezillon@free-electrons.com> Acked-by: Nicolas Ferre <nicolas.ferre@microchip.com> Signed-off-by: Stephen Boyd <sboyd@codeaurora.org>
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#
b3b02eac |
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07-Jun-2017 |
Alexandre Belloni <alexandre.belloni@bootlin.com> |
clk: at91: Add sama5d2 suspend/resume On sama5d2, VDD core maybe be cut while in suspend. This means registers will be lost. Ensure they are saved and restored properly. Signed-off-by: Alexandre Belloni <alexandre.belloni@free-electrons.com> Acked-by: Nicolas Ferre <nicolas.ferre@microchip.com> Signed-off-by: Stephen Boyd <sboyd@codeaurora.org>
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#
4a5f06a0 |
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04-Jun-2017 |
Alexandre Belloni <alexandre.belloni@bootlin.com> |
clk: at91: fix clk-generated compilation Fix missing } Signed-off-by: Alexandre Belloni <alexandre.belloni@free-electrons.com> Signed-off-by: Stephen Boyd <sboyd@codeaurora.org>
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#
8e56133e |
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12-May-2017 |
Alexandre Belloni <alexandre.belloni@bootlin.com> |
clk: at91: fix clk-generated parenting clk_generated_startup is called after clk_hw_register. So the first call to get_parent will not have the correct value (i.e. 0) and because this is cached, it may never be updated. Signed-off-by: Alexandre Belloni <alexandre.belloni@free-electrons.com> Fixes: df70aeef6083 ("clk: at91: add generated clock driver") Signed-off-by: Stephen Boyd <sboyd@codeaurora.org>
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#
f5644f10 |
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01-Jun-2016 |
Stephen Boyd <stephen.boyd@linaro.org> |
clk: at91: Migrate to clk_hw based registration and OF APIs Now that we have clk_hw based provider APIs to register clks, we can get rid of struct clk pointers in this driver, allowing us to move closer to a clear split of consumer and provider clk APIs. Signed-off-by: Stephen Boyd <stephen.boyd@linaro.org> Acked-by: Alexandre Belloni <alexandre.belloni@free-electrons.com> Tested-by: Alexandre Belloni <alexandre.belloni@free-electrons.com> Acked-by: Boris Brezillon <boris.brezillon@free-electrons.com> Signed-off-by: Stephen Boyd <sboyd@codeaurora.org>
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#
14755549 |
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07-Jun-2016 |
Ben Dooks <ben.dooks@codethink.co.uk> |
clk: at91: make of_sama5d2_clk_generated_setup() static The of_sama5d2_clk_generated_setup() is not exported outside of the driver, so make it static to fix the warning about it being not static: drivers/clk/at91/clk-generated.c:270:13: warning: symbol 'of_sama5d2_clk_generated_setup' was not declared. Should it be static? Signed-off-by: Ben Dooks <ben.dooks@codethink.co.uk> Acked-by: Boris Brezillon <boris.brezillon@free-electrons.com> Signed-off-by: Stephen Boyd <sboyd@codeaurora.org>
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#
8c1b1e54 |
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19-Feb-2016 |
Stephen Boyd <sboyd@codeaurora.org> |
clk: at91: Remove impossible checks for of_clk_get_parent_count() These checks for < 0 are impossible now that of_clk_get_parent_count() returns an unsigned int. Change the checks for == 0 and update the type. Cc: Boris Brezillon <boris.brezillon@free-electrons.com> Signed-off-by: Stephen Boyd <sboyd@codeaurora.org>
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#
0002ca16 |
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27-Jan-2016 |
Alexandre Belloni <alexandre.belloni@bootlin.com> |
clk: at91: remove useless includes Over time, some includes were copy pasted from other clocks drivers but are not necessary. Acked-by: Stephen Boyd <sboyd@codeaurora.org> Signed-off-by: Alexandre Belloni <alexandre.belloni@free-electrons.com>
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#
1bdf0232 |
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07-Sep-2014 |
Boris Brezillon <bbrezillon@kernel.org> |
clk: at91: make use of syscon/regmap internally Use the regmap coming from syscon to access the registers instead of using pmc_read/pmc_write. This allows to avoid passing the at91_pmc structure to the child nodes of the PMC. The final benefit is to have each clock register itself instead of having to iterate over the children. Signed-off-by: Boris Brezillon <boris.brezillon@free-electrons.com> Acked-by: Stephen Boyd <sboyd@codeaurora.org> Signed-off-by: Alexandre Belloni <alexandre.belloni@free-electrons.com>
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#
df70aeef |
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31-Jul-2015 |
Nicolas Ferre <nicolas.ferre@microchip.com> |
clk: at91: add generated clock driver Add a new type of clocks that can be provided to a peripheral. In addition to the peripheral clock, this new clock that can use several input clocks as parents can generate divided rates. This would allow a peripheral to have finer grained clocks for generating a baud rate, clocking an asynchronous part or having more options in frequency. Signed-off-by: Nicolas Ferre <nicolas.ferre@atmel.com> Signed-off-by: Boris Brezillon <boris.brezillon@free-electrons.com> [sboyd@codeaurora.org: Transition to new clk_hw provider APIs] Signed-off-by: Stephen Boyd <sboyd@codeaurora.org>
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