Searched refs:dc (Results 251 - 275 of 549) sorted by relevance

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/linux-master/drivers/gpu/drm/amd/display/dc/hwss/dcn10/
H A Ddcn10_init.c124 void dcn10_hw_sequencer_construct(struct dc *dc) argument
126 dc->hwss = dcn10_funcs;
127 dc->hwseq->funcs = dcn10_private_funcs;
/linux-master/drivers/gpu/drm/amd/display/dc/hwss/dcn20/
H A Ddcn20_init.c141 void dcn20_hw_sequencer_construct(struct dc *dc) argument
143 dc->hwss = dcn20_funcs;
144 dc->hwseq->funcs = dcn20_private_funcs;
/linux-master/drivers/gpu/drm/tegra/
H A Dplane.c16 #include "dc.h"
97 struct tegra_dc *dc = to_tegra_dc(crtc); local
99 if (!dc->soc->supports_sector_layout)
140 static int tegra_dc_pin(struct tegra_dc *dc, struct tegra_plane_state *state) argument
149 map = host1x_bo_pin(dc->dev, &bo->base, DMA_TO_DEVICE, &dc->client.cache);
155 if (!dc->client.group) {
178 dev_err(dc->dev, "failed to map plane %u: %d\n", i, err);
189 static void tegra_dc_unpin(struct tegra_dc *dc, struct tegra_plane_state *state) argument
203 struct tegra_dc *dc local
219 struct tegra_dc *dc = to_tegra_dc(state->crtc); local
771 struct tegra_dc *dc = plane->dc; local
[all...]
H A Dhub.h64 struct tegra_dc *dc; member in struct:tegra_display_hub_state
81 struct tegra_dc *dc,
/linux-master/drivers/gpu/drm/amd/display/dc/dml/dcn20/
H A Ddcn20_fpu.c39 dc->ctx->logger
990 void dcn20_populate_dml_writeback_from_context(struct dc *dc, argument
998 for (i = 0, pipe_cnt = 0; i < dc->res_pool->pipe_count; i++) {
1046 static bool is_dtbclk_required(struct dc *dc, struct dc_state *context) argument
1049 for (i = 0; i < dc->res_pool->pipe_count; i++) {
1052 if (dc->link_srv->dp_is_128b_132b_signal(&context->res_ctx.pipe_ctx[i]))
1058 static enum dcn_zstate_support_state decide_zstate_support(struct dc *dc, struc argument
1140 dcn20_calculate_dlg_params(struct dc *dc, struct dc_state *context, display_e2e_pipe_params_st *pipes, int pipe_cnt, int vlevel) argument
1314 dcn20_populate_dml_pipes_from_context(struct dc *dc, struct dc_state *context, display_e2e_pipe_params_st *pipes, bool fast_validate) argument
1728 dcn20_calculate_wm(struct dc *dc, struct dc_state *context, display_e2e_pipe_params_st *pipes, int *out_pipe_cnt, int *pipe_split_from, int vlevel, bool fast_validate) argument
1845 dcn20_update_bounding_box(struct dc *dc, struct _vcs_dpi_soc_bounding_box_st *bb, struct pp_smu_nv_clock_table *max_clocks, unsigned int *uclk_states, unsigned int num_states) argument
1979 dcn20_patch_bounding_box(struct dc *dc, struct _vcs_dpi_soc_bounding_box_st *bb) argument
2026 dcn20_validate_bandwidth_internal(struct dc *dc, struct dc_state *context, bool fast_validate, display_e2e_pipe_params_st *pipes) argument
2076 dcn20_validate_bandwidth_fp(struct dc *dc, struct dc_state *context, bool fast_validate, display_e2e_pipe_params_st *pipes) argument
2153 dcn21_populate_dml_pipes_from_context(struct dc *dc, struct dc_state *context, display_e2e_pipe_params_st *pipes, bool fast_validate) argument
2174 patch_bounding_box(struct dc *dc, struct _vcs_dpi_soc_bounding_box_st *bb) argument
2234 dcn21_calculate_wm(struct dc *dc, struct dc_state *context, display_e2e_pipe_params_st *pipes, int *out_pipe_cnt, int *pipe_split_from, int vlevel_req, bool fast_validate) argument
2318 dcn21_validate_bandwidth_fp(struct dc *dc, struct dc_state *context, bool fast_validate, display_e2e_pipe_params_st *pipes) argument
2400 dcn21_update_bw_bounding_box(struct dc *dc, struct clk_bw_params *bw_params) argument
2473 dcn201_populate_dml_writeback_from_context_fpu(struct dc *dc, struct resource_context *res_ctx, display_e2e_pipe_params_st *pipes) argument
[all...]
/linux-master/drivers/gpu/drm/amd/display/dc/resource/dce100/
H A Ddce100_resource.c688 ctx->dc->caps.extended_aux_timeout_support);
823 const struct dc *dc,
840 struct dc *dc,
847 for (i = 0; i < dc->res_pool->pipe_count; i++) {
885 struct dc *dc,
895 struct dc *dc,
822 build_mapped_resource( const struct dc *dc, struct dc_state *context, struct dc_stream_state *stream) argument
839 dce100_validate_bandwidth( struct dc *dc, struct dc_state *context, bool fast_validate) argument
884 dce100_validate_global( struct dc *dc, struct dc_state *context) argument
894 dce100_add_stream_to_ctx( struct dc *dc, struct dc_state *new_ctx, struct dc_stream_state *dc_stream) argument
982 dce100_resource_construct( uint8_t num_virtual_links, struct dc *dc, struct dce110_resource_pool *pool) argument
1162 dce100_create_resource_pool( uint8_t num_virtual_links, struct dc *dc) argument
[all...]
/linux-master/drivers/gpu/drm/amd/display/dc/inc/
H A Ddcn_calcs.h37 struct dc;
623 struct dc *dc,
628 const struct dc *dc,
632 struct dc *dc,
638 struct dc *dc,
641 struct dc *d
[all...]
/linux-master/tools/perf/scripts/python/Perf-Trace-Util/lib/Perf/Trace/
H A DSchedGui.py86 dc = self.dc
92 dc.SetBrush(brush)
93 dc.DrawRectangle(offset_px, offset_py, width_px, RootFrame.EVENT_MARKING_WIDTH)
100 dc.SetBrush(brush)
101 dc.DrawRectangle(offset_px, offset_py, width_px, width_py)
103 def update_rectangles(self, dc, start, end):
109 dc = wx.PaintDC(self.scroll_panel)
110 self.dc = dc
[all...]
/linux-master/drivers/gpu/drm/amd/display/dc/dce/
H A Ddmub_psr.c27 #include "dc.h"
141 struct dc_context *dc = dmub->ctx; local
169 dc_wake_and_execute_dmub_cmd(dc, &cmd, DM_DMUB_WAIT_TYPE_WAIT);
180 struct dc_context *dc = dmub->ctx; local
197 dc_wake_and_execute_dmub_cmd(dc->dmub_srv->ctx, &cmd, DM_DMUB_WAIT_TYPE_WAIT);
232 struct dc_context *dc = dmub->ctx; local
246 dc_wake_and_execute_dmub_cmd(dc, &cmd, DM_DMUB_WAIT_TYPE_WAIT);
256 struct dc_context *dc = dmub->ctx; local
265 dc_wake_and_execute_dmub_cmd(dc, &cmd, DM_DMUB_WAIT_TYPE_WAIT);
274 struct dc_context *dc local
296 struct dc_context *dc = dmub->ctx; local
432 struct dc_context *dc = dmub->ctx; local
[all...]
/linux-master/drivers/gpu/drm/amd/display/amdgpu_dm/
H A Damdgpu_dm_irq.c27 #include "dc.h"
497 dc_interrupt_set(adev->dm.dc, src, false);
532 dc_interrupt_set(adev->dm.dc, src, true);
558 dc_interrupt_set(adev->dm.dc, src, true);
659 adev->dm.dc,
663 dc_interrupt_ack(adev->dm.dc, src);
701 dc_interrupt_set(adev->dm.dc, src, st);
714 struct dc *dc = adev->dm.dc; local
[all...]
/linux-master/drivers/gpu/drm/amd/display/dc/dcn31/
H A Ddcn31_afmt.c31 #include "dc/dc.h"
61 if (afmt->ctx->dc->debug.enable_mem_low_power.bits.afmt == false)
71 if (afmt->ctx->dc->debug.enable_mem_low_power.bits.afmt == false)
H A Ddcn31_vpg.c30 #include "dc/dc.h"
56 if (vpg->ctx->dc->debug.enable_mem_low_power.bits.vpg == false)
70 if (vpg->ctx->dc->debug.enable_mem_low_power.bits.vpg == false &&
/linux-master/drivers/gpu/drm/amd/display/dc/link/hwss/
H A Dlink_hwss_dio.c47 pipe_ctx->stream->ctx->dc->link_srv->dp_trace_source_sequence(pipe_ctx->stream->link,
69 pipe_ctx->stream->ctx->dc->link_srv->dp_trace_source_sequence(
112 link->dc->link_srv->dp_trace_source_sequence(link,
134 link->dc->link_srv->dp_trace_source_sequence(link,
145 link->dc->link_srv->dp_trace_source_sequence(link,
156 link->dc->link_srv->dp_trace_source_sequence(link, DPCD_SOURCE_SEQ_AFTER_SET_SOURCE_PATTERN);
205 pipe_ctx->stream->ctx->dc->link_srv->dp_trace_source_sequence(
225 pipe_ctx->stream->ctx->dc->link_srv->dp_trace_source_sequence(
H A Dlink_hwss_dpia.c47 status = dc_process_dmub_set_mst_slots(link->dc, link->link_index,
78 link->dc->res_pool->funcs->link_encs_assign;
/linux-master/drivers/gpu/drm/amd/display/dc/hwss/dce/
H A Ddce_hwseq.c47 void dce_pipe_control_lock(struct dc *dc, argument
53 struct dce_hwseq *hws = dc->hwseq;
89 void dce60_pipe_control_lock(struct dc *dc, argument
/linux-master/drivers/gpu/drm/amd/display/dc/dcn32/
H A Ddcn32_dio_stream_encoder.c70 if (!enc->ctx->dc->debug.avoid_vbios_exec_table) {
111 if (!enc->ctx->dc->debug.avoid_vbios_exec_table) {
270 static bool is_dp_dig_pixel_rate_div_policy(struct dc *dc, const struct dc_crtc_timing *timing) argument
274 dc->debug.enable_dp_dig_pixel_rate_div_policy;
283 struct dc *dc = enc->ctx->dc; local
294 || is_dp_dig_pixel_rate_div_policy(dc, &param->timing)) {
380 link->dc
[all...]
/linux-master/drivers/gpu/drm/amd/display/dc/dcn35/
H A Ddcn35_dio_stream_encoder.c59 if (!enc->ctx->dc->debug.avoid_vbios_exec_table) {
99 if (!enc->ctx->dc->debug.avoid_vbios_exec_table) {
302 static bool is_dp_dig_pixel_rate_div_policy(struct dc *dc, const struct dc_crtc_timing *timing) argument
306 dc->debug.enable_dp_dig_pixel_rate_div_policy;
315 struct dc *dc = enc->ctx->dc; local
326 || is_dp_dig_pixel_rate_div_policy(dc, &param->timing)) {
398 link->dc
[all...]
/linux-master/fs/reiserfs/
H A Dibalance.c136 struct disk_child *dc; local
151 dc = B_N_CHILD(cur, to + 1);
153 memmove(dc + count, dc, (nr + 1 - (to + 1)) * DC_SIZE);
161 memcpy(dc, new_dc, DC_SIZE * count);
213 struct disk_child *dc; local
243 dc = B_N_CHILD(cur, first_p);
245 memmove(dc, dc + del_num, (nr + 1 - first_p - del_num) * DC_SIZE);
312 struct disk_child *dc; local
883 struct disk_child *dc; local
952 struct disk_child *dc; local
1003 struct disk_child *dc; local
1098 struct disk_child *dc; local
[all...]
/linux-master/drivers/gpu/drm/amd/display/dc/clk_mgr/dcn20/
H A Ddcn20_clk_mgr.c110 for (i = 0; i < clk_mgr->base.ctx->dc->res_pool->pipe_count; i++) {
152 for (i = 0; i < clk_mgr->base.ctx->dc->res_pool->pipe_count; i++) {
155 struct dccg *dccg = clk_mgr->base.ctx->dc->res_pool->dccg;
183 for (i = 0; i < clk_mgr->base.ctx->dc->res_pool->pipe_count; i++) {
185 struct dccg *dccg = clk_mgr->base.ctx->dc->res_pool->dccg;
222 struct dc *dc = clk_mgr_base->ctx->dc; local
229 struct dmcu *dmcu = clk_mgr_base->ctx->dc->res_pool->dmcu;
234 if (dc
[all...]
/linux-master/drivers/gpu/drm/amd/display/dc/clk_mgr/dcn30/
H A Ddcn30_clk_mgr.c198 struct dc *dc = clk_mgr_base->ctx->dc; local
205 struct dmcu *dmcu = clk_mgr_base->ctx->dc->res_pool->dmcu;
210 if (dc->work_arounds.skip_clock_update || !clk_mgr->smu_present)
214 (dc->debug.force_clock_mode & 0x1)) {
222 display_count = clk_mgr_helper_get_active_display_cnt(dc, context);
230 if (dc->debug.force_min_dcfclk_mhz > 0)
231 new_clocks->dcfclk_khz = (new_clocks->dcfclk_khz > (dc->debug.force_min_dcfclk_mhz * 1000)) ?
232 new_clocks->dcfclk_khz : (dc
[all...]
/linux-master/drivers/gpu/drm/amd/display/dc/clk_mgr/dcn35/
H A Ddcn35_clk_mgr.c91 struct dc *dc,
107 for (i = 0; i < dc->link_count; i++) {
108 const struct dc_link *link = dc->links[i];
127 struct dc *dc = clk_mgr_base->ctx->dc; local
130 for (i = 0; i < dc->res_pool->pipe_count; ++i) {
133 : &dc->current_state->res_ctx.pipe_ctx[i];
143 reset_sync_context_for_pipe(dc, contex
90 dcn35_get_active_display_cnt_wa( struct dc *dc, struct dc_state *context, int *all_active_disps) argument
228 struct dc *dc = clk_mgr_base->ctx->dc; local
882 struct dc *dc = clk_mgr_base->ctx->dc; local
[all...]
/linux-master/drivers/gpu/drm/amd/display/dc/clk_mgr/dcn316/
H A Ddcn316_clk_mgr.c70 struct dc *dc,
86 for (i = 0; i < dc->link_count; i++) {
87 const struct dc_link *link = dc->links[i];
105 struct dc *dc = clk_mgr_base->ctx->dc; local
108 for (i = 0; i < dc->res_pool->pipe_count; ++i) {
111 : &dc->current_state->res_ctx.pipe_ctx[i];
121 reset_sync_context_for_pipe(dc, contex
69 dcn316_get_active_display_cnt_wa( struct dc *dc, struct dc_state *context) argument
142 struct dc *dc = clk_mgr_base->ctx->dc; local
[all...]
/linux-master/drivers/gpu/drm/tiny/
H A Dili9486.c63 gpiod_set_value_cansleep(mipi->dc, 0);
85 gpiod_set_value_cansleep(mipi->dc, 1);
204 struct gpio_desc *dc; local
220 dc = devm_gpiod_get(dev, "dc", GPIOD_OUT_LOW);
221 if (IS_ERR(dc))
222 return dev_err_probe(dev, PTR_ERR(dc), "Failed to get GPIO 'dc'\n");
230 ret = mipi_dbi_spi_init(spi, dbi, dc);
/linux-master/arch/arm64/mm/
H A Dcache.S151 dc civac, x1 // clean & invalidate D / U line
155 dc civac, x0 // clean & invalidate D / U line
157 2: dc ivac, x0 // invalidate D / U line
/linux-master/drivers/gpu/drm/loongson/
H A Dlsdc_debugfs.c73 pci_read_config_word(ldev->dc, PCI_COMMAND, &cmd);
79 pci_write_config_word(ldev->dc, PCI_COMMAND, cmd);
81 pci_read_config_word(ldev->dc, PCI_COMMAND, &cmd);

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