/linux-master/drivers/usb/c67x00/ |
H A D | c67x00-sched.c | 48 u8 ctrl_reg; /* Byte 6 */ member in struct:c67x00_td 125 !(td->ctrl_reg & SEQ_SEL))) 148 dev_dbg(dev, "ctrl_reg: 0x%02x\n", td->ctrl_reg); 620 td->ctrl_reg = cmd; 1032 !(td->ctrl_reg & SEQ_SEL));
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/linux-master/drivers/scsi/ |
H A D | zorro_esp.c | 102 #define ctrl_reg cond_reg /* DMA control (wo) [0x402] */ macro 115 #define ctrl_reg cond_reg /* DMA control (wo) [0x000] */ macro 130 #define ctrl_reg cond_reg /* DMA control (wo) [0x0000] */ macro 161 unsigned char ctrl_data; /* shadow copy of ctrl_reg */ 445 writeb(*ctrl_data, &dregs->ctrl_reg); 538 writeb(*ctrl_data, &dregs->ctrl_reg);
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/linux-master/drivers/pmdomain/mediatek/ |
H A D | mtk-scpsys.c | 154 struct scp_ctrl_reg ctrl_reg; member in struct:scp 176 u32 status = readl(scp->base + scp->ctrl_reg.pwr_sta_offs) & 178 u32 status2 = readl(scp->base + scp->ctrl_reg.pwr_sta2nd_offs) & 436 scp->ctrl_reg.pwr_sta_offs = scp_ctrl_reg->pwr_sta_offs; 437 scp->ctrl_reg.pwr_sta2nd_offs = scp_ctrl_reg->pwr_sta2nd_offs;
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/linux-master/drivers/gpu/drm/bridge/imx/ |
H A D | imx8qxp-ldb.c | 186 regmap_write(ldb->regmap, ldb->ctrl_reg, ldb->ldb_ctrl); 614 ldb->ctrl_reg = 0xe0; 692 regmap_write(ldb->regmap, ldb->ctrl_reg, 0);
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H A D | imx8qm-ldb.c | 475 ldb->ctrl_reg = 0xe0; 556 regmap_write(ldb->regmap, ldb->ctrl_reg, 0);
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/linux-master/drivers/net/ethernet/intel/e1000e/ |
H A D | ethtool.c | 1311 u32 ctrl_reg = 0; local 1322 ctrl_reg = er32(CTRL); 1323 ctrl_reg &= ~E1000_CTRL_SPD_SEL; /* Clear the speed sel bits */ 1324 ctrl_reg |= (E1000_CTRL_FRCSPD | /* Set the Force Speed Bit */ 1329 ew32(CTRL, ctrl_reg); 1401 ctrl_reg = er32(CTRL); 1402 ctrl_reg &= ~E1000_CTRL_SPD_SEL; /* Clear the speed sel bits */ 1403 ctrl_reg |= (E1000_CTRL_FRCSPD | /* Set the Force Speed Bit */ 1409 ctrl_reg |= E1000_CTRL_SLU; /* Set Link Up */ 1413 ctrl_reg | [all...] |
/linux-master/drivers/iio/adc/ |
H A D | pac1934.c | 921 u8 ctrl_reg; local 931 ctrl_reg = FIELD_PREP(PAC1934_CRTL_SAMPLE_RATE_MASK, ret); 932 ret = i2c_smbus_write_byte_data(client, PAC1934_CTRL_REG_ADDR, ctrl_reg); 1225 u8 regs[PAC1934_CTRL_STATUS_INFO_LEN], idx, ctrl_reg; local 1279 ctrl_reg = FIELD_PREP(PAC1934_CRTL_SAMPLE_RATE_MASK, PAC1934_SAMP_1024SPS); 1281 ret = i2c_smbus_write_byte_data(client, PAC1934_CTRL_REG_ADDR, ctrl_reg);
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/linux-master/drivers/spi/ |
H A D | spi-ti-qspi.c | 48 unsigned int ctrl_reg; member in struct:ti_qspi 533 regmap_update_bits(qspi->ctrl_base, qspi->ctrl_reg, 547 regmap_update_bits(qspi->ctrl_base, qspi->ctrl_reg, 837 1, &qspi->ctrl_reg);
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/linux-master/drivers/gpu/drm/mediatek/ |
H A D | mtk_hdmi.c | 306 u32 ctrl_reg = GRL_CTRL; local 328 ctrl_reg = GRL_CTRL; 332 ctrl_reg = GRL_CTRL; 336 ctrl_reg = GRL_CTRL; 340 ctrl_reg = GRL_ACP_ISRC_CTRL; 346 mtk_hdmi_clear_bits(hdmi, ctrl_reg, ctrl_frame_en); 355 mtk_hdmi_set_bits(hdmi, ctrl_reg, ctrl_frame_en);
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/linux-master/drivers/regulator/ |
H A D | qcom_spmi-regulator.c | 248 /* Used for indexing into ctrl_reg. These are offets from 0x40 */ 1847 u8 ctrl_reg[8], reg, mask; local 1851 ret = spmi_vreg_read(vreg, SPMI_COMMON_REG_VOLTAGE_RANGE, ctrl_reg, 8); 1861 ctrl_reg[SPMI_COMMON_IDX_ENABLE] &= 1863 ctrl_reg[SPMI_COMMON_IDX_ENABLE] |= 1876 ctrl_reg[SPMI_COMMON_IDX_MODE] &= 1878 ctrl_reg[SPMI_COMMON_IDX_MODE] |= 1885 ctrl_reg[SPMI_COMMON_IDX_MODE] &= 1887 ctrl_reg[SPMI_COMMON_IDX_MODE] |= 1896 ret = spmi_vreg_write(vreg, SPMI_COMMON_REG_VOLTAGE_RANGE, ctrl_reg, [all...] |
/linux-master/drivers/atm/ |
H A D | iphase.c | 2444 static u32 ctrl_reg; local 2447 ctrl_reg = readl(ia_dev[i]->reg+IPHASE5575_BUS_CONTROL_REG); 2450 ctrl_reg &= (~CTRL_LED); 2451 writel(ctrl_reg, ia_dev[i]->reg+IPHASE5575_BUS_CONTROL_REG); 2456 ctrl_reg |= CTRL_LED; 2457 writel(ctrl_reg, ia_dev[i]->reg+IPHASE5575_BUS_CONTROL_REG); 2513 u32 ctrl_reg; local 2540 ctrl_reg = readl(iadev->reg+IPHASE5575_BUS_CONTROL_REG); 2541 ctrl_reg = (ctrl_reg [all...] |
/linux-master/drivers/gpu/drm/i915/gt/ |
H A D | intel_engine_types.h | 229 * @ctrl_reg: the enhanced execlists control register, used to load the 232 u32 __iomem *ctrl_reg; member in struct:intel_engine_execlists
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/linux-master/drivers/net/wwan/t7xx/ |
H A D | t7xx_pci.c | 139 void __iomem *ctrl_reg = IREG_BASE(t7xx_dev) + T7XX_PCIE_MISC_CTRL; local 142 value = ioread32(ctrl_reg); 149 iowrite32(value, ctrl_reg);
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/linux-master/drivers/iommu/ |
H A D | mtk_iommu_v1.c | 92 u32 ctrl_reg; member in struct:mtk_iommu_v1_suspend_reg 728 reg->ctrl_reg = readl_relaxed(base + REG_MMU_CTRL_REG); 743 writel_relaxed(reg->ctrl_reg, base + REG_MMU_CTRL_REG);
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H A D | mtk_iommu.c | 187 u32 ctrl_reg; member in struct:mtk_iommu_suspend_reg 1447 reg->ctrl_reg = readl_relaxed(base + REG_MMU_CTRL_REG); 1486 writel_relaxed(reg->ctrl_reg, base + REG_MMU_CTRL_REG);
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/linux-master/drivers/pinctrl/cirrus/ |
H A D | pinctrl-lochnagar.c | 375 .ctrl_reg = LOCHNAGAR1_##CTRL, \ 387 .ctrl_reg = LOCHNAGAR2_##ID##_CTRL, \ 401 u16 ctrl_reg; member in struct:lochnagar_aif 880 ret = regmap_update_bits(regmap, aif->ctrl_reg, 1005 ret = regmap_update_bits(regmap, aif->ctrl_reg, aif->master_mask, val);
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/linux-master/drivers/net/ethernet/intel/igb/ |
H A D | e1000_82575.c | 1654 u32 ctrl_ext, ctrl_reg, reg, anadv_reg; local 1677 ctrl_reg = rd32(E1000_CTRL); 1678 ctrl_reg |= E1000_CTRL_SLU; 1682 ctrl_reg |= E1000_CTRL_SWDPIN0 | E1000_CTRL_SWDPIN1; 1723 ctrl_reg |= E1000_CTRL_SPD_1000 | E1000_CTRL_FRCSPD | 1731 wr32(E1000_CTRL, ctrl_reg);
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H A D | igb_ethtool.c | 1624 u32 ctrl_reg = 0; local 1653 ctrl_reg = rd32(E1000_CTRL); 1654 ctrl_reg &= ~E1000_CTRL_SPD_SEL; /* Clear the speed sel bits */ 1655 ctrl_reg |= (E1000_CTRL_FRCSPD | /* Set the Force Speed Bit */ 1662 ctrl_reg |= E1000_CTRL_ILOS; /* Invert Loss of Signal */ 1664 wr32(E1000_CTRL, ctrl_reg);
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/linux-master/drivers/clk/xilinx/ |
H A D | clk-xlnx-clock-wizard.c | 974 void __iomem *ctrl_reg; local 1129 ctrl_reg = clk_wzrd->base + WZRD_CLK_CFG_REG(is_versal, 0); 1133 flags, ctrl_reg, 0, 8, CLK_DIVIDER_ONE_BASED |
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/linux-master/drivers/gpu/drm/i915/display/ |
H A D | vlv_dsi.c | 139 i915_reg_t data_reg, ctrl_reg; local 151 ctrl_reg = MIPI_LP_GEN_CTRL(display, port); 156 ctrl_reg = MIPI_HS_GEN_CTRL(display, port); 182 intel_de_write(display, ctrl_reg,
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/linux-master/drivers/iio/accel/ |
H A D | sca3000.c | 394 * @ctrl_reg: Which ctrl register do we want to read. 399 u8 ctrl_reg) 412 ret = sca3000_write_reg(st, SCA3000_REG_CTRL_SEL_ADDR, ctrl_reg); 398 sca3000_read_ctrl_reg(struct sca3000_state *st, u8 ctrl_reg) argument
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/linux-master/drivers/gpu/drm/i915/gvt/ |
H A D | cmd_parser.c | 1271 i915_reg_t ctrl_reg; member in struct:mi_display_flip_command_info 1317 info->ctrl_reg = DSPCNTR(info->pipe); 1321 info->ctrl_reg = SPRCTL(info->pipe); 1383 info->ctrl_reg = DSPCNTR(info->pipe); 1400 tile = (vgpu_vreg_t(s->vgpu, info->ctrl_reg) & 1405 tile = (vgpu_vreg_t(s->vgpu, info->ctrl_reg) & (1 << 10)) >> 10; 1429 set_mask_bits(&vgpu_vreg_t(vgpu, info->ctrl_reg), GENMASK(12, 10), 1434 set_mask_bits(&vgpu_vreg_t(vgpu, info->ctrl_reg), GENMASK(10, 10),
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/linux-master/drivers/staging/media/atomisp/pci/ |
H A D | atomisp_gmin_platform.c | 717 int ctrl_reg, int shift, bool on) 728 ret = gmin_i2c_write(dev, gs->pwm_i2c_addr, ctrl_reg, val, 1 << shift); 715 axp_regulator_set(struct device *dev, struct gmin_subdev *gs, int sel_reg, u8 setting, int ctrl_reg, int shift, bool on) argument
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/linux-master/drivers/dma/xilinx/ |
H A D | xilinx_dma.c | 1468 u32 ctrl_reg = dma_read(chan, XILINX_DMA_REG_DMACR); local 1487 ctrl_reg &= ~XILINX_DMA_CR_COALESCE_MAX; 1488 ctrl_reg |= chan->desc_pendingcount << 1490 dma_ctrl_write(chan, XILINX_DMA_REG_DMACR, ctrl_reg);
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/linux-master/drivers/net/ethernet/sun/ |
H A D | niu.c | 776 unsigned long ctrl_reg, test_cfg_reg, i; local 782 ctrl_reg = ENET_SERDES_0_CTRL_CFG; 786 ctrl_reg = ENET_SERDES_1_CTRL_CFG; 818 nw64(ctrl_reg, ctrl_val); 929 unsigned long ctrl_reg, test_cfg_reg, pll_cfg, i; local 940 ctrl_reg = ENET_SERDES_0_CTRL_CFG; 946 ctrl_reg = ENET_SERDES_1_CTRL_CFG; 984 nw64(ctrl_reg, ctrl_val); 2372 unsigned long ctrl_reg, test_cfg_reg, pll_cfg, i; local 2377 ctrl_reg [all...] |