Searched refs:csr (Results 51 - 75 of 223) sorted by relevance

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/linux-master/tools/arch/riscv/include/asm/
H A Dcsr.h479 #define csr_swap(csr, val) \
482 __asm__ __volatile__ ("csrrw %0, " __ASM_STR(csr) ", %1"\
488 #define csr_read(csr) \
491 __asm__ __volatile__ ("csrr %0, " __ASM_STR(csr) \
497 #define csr_write(csr, val) \
500 __asm__ __volatile__ ("csrw " __ASM_STR(csr) ", %0" \
505 #define csr_read_set(csr, val) \
508 __asm__ __volatile__ ("csrrs %0, " __ASM_STR(csr) ", %1"\
514 #define csr_set(csr, val) \
517 __asm__ __volatile__ ("csrs " __ASM_STR(csr) ",
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/linux-master/drivers/net/wireless/ralink/rt2x00/
H A Drt2x00pci.c33 if (rt2x00dev->csr.base) {
34 iounmap(rt2x00dev->csr.base);
35 rt2x00dev->csr.base = NULL;
43 rt2x00dev->csr.base = pci_ioremap_bar(pci_dev, 0);
44 if (!rt2x00dev->csr.base)
H A Drt2x00soc.c31 iounmap(rt2x00dev->csr.base);
43 rt2x00dev->csr.base = ioremap(res->start, resource_size(res));
44 if (!rt2x00dev->csr.base)
/linux-master/arch/mips/kernel/
H A Dirq_txx9.c34 u32 csr; member in struct:txx9_irc_reg
173 u32 csr = __raw_readl(&txx9_ircptr->csr); local
175 if (likely(!(csr & TXx9_IRCSR_IF)))
176 return TXX9_IRQ_BASE + (csr & (TXx9_MAX_IR - 1));
H A Dsignal.c75 uint32_t __user *csr = sc + abi->off_sc_fpc_csr; local
85 err |= __put_user(current->thread.fpu.fcr31, csr);
94 uint32_t __user *csr = sc + abi->off_sc_fpc_csr; local
104 err |= __get_user(current->thread.fpu.fcr31, csr);
130 uint32_t __user *csr = sc + abi->off_sc_fpc_csr; local
132 return _save_fp_context(fpregs, csr);
139 uint32_t __user *csr = sc + abi->off_sc_fpc_csr; local
141 return _restore_fp_context(fpregs, csr);
188 err = __put_user(read_msa_csr(), &msa->csr);
195 err = __put_user(current->thread.fpu.msacsr, &msa->csr);
213 unsigned int csr; local
329 uint32_t __user *csr = sc + abi->off_sc_fpc_csr; local
382 uint32_t __user *csr = sc + abi->off_sc_fpc_csr; local
500 unsigned int csr, enabled; local
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/linux-master/arch/alpha/kernel/
H A Dcore_marvel.c64 q = ev7csr->csr;
76 ev7csr->csr = q;
187 csrs->POx_ERR_SUM.csr = -1UL;
188 csrs->POx_TLB_ERR.csr = -1UL;
189 csrs->POx_SPL_COMPLT.csr = -1UL;
190 csrs->POx_TRANS_SUM.csr = -1UL;
198 p7csrs->PO7_ERROR_SUM.csr = -1UL;
199 p7csrs->PO7_UNCRR_SYM.csr = -1UL;
200 p7csrs->PO7_CRRCT_SYM.csr = -1UL;
272 io7_port->saved_wbase[i] = csrs->POx_WBASE[i].csr;
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H A Derr_marvel.c818 err_sum |= io7->csrs->PO7_ERROR_SUM.csr;
822 err_sum |= io7->ports[i].csrs->POx_ERR_SUM.csr;
843 io->io_asic_rev = io7->csrs->IO_ASIC_REV.csr;
844 io->io_sys_rev = io7->csrs->IO_SYS_REV.csr;
845 io->io7_uph = io7->csrs->IO7_UPH.csr;
846 io->hpi_ctl = io7->csrs->HPI_CTL.csr;
847 io->crd_ctl = io7->csrs->CRD_CTL.csr;
848 io->hei_ctl = io7->csrs->HEI_CTL.csr;
849 io->po7_error_sum = io7->csrs->PO7_ERROR_SUM.csr;
850 io->po7_uncrr_sym = io7->csrs->PO7_UNCRR_SYM.csr;
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H A Dsys_dp264.c68 dim0 = &cchip->dim0.csr;
69 dim1 = &cchip->dim1.csr;
70 dim2 = &cchip->dim2.csr;
71 dim3 = &cchip->dim3.csr;
88 if (bcpu == 0) dimB = &cchip->dim0.csr;
89 else if (bcpu == 1) dimB = &cchip->dim1.csr;
90 else if (bcpu == 2) dimB = &cchip->dim2.csr;
91 else dimB = &cchip->dim3.csr;
197 pld = TSUNAMI_cchip->dir0.csr;
/linux-master/drivers/scsi/
H A Dsun_esp.c323 u32 csr; local
329 csr = dma_read32(DMA_CSR);
330 if (!(csr & DMA_FIFO_ISDRAIN))
334 dma_write32(csr | DMA_FIFO_STDRAIN, DMA_CSR);
389 u32 csr; local
401 csr = esp->prev_hme_dmacsr;
402 csr |= DMA_SCSI_DISAB | DMA_ENABLE;
404 csr |= DMA_ST_WRITE;
406 csr &= ~DMA_ST_WRITE;
407 esp->prev_hme_dmacsr = csr;
433 u32 csr = dma_read32(DMA_CSR); local
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/linux-master/drivers/usb/mtu3/
H A Dmtu3_gadget_ep0.c139 u32 csr; local
142 csr = mtu3_readl(mbase, U3D_EP0CSR) & EP0_W1C_BITS;
144 csr |= EP0_SENDSTALL | pktrdy;
146 csr = (csr & ~EP0_SENDSTALL) | EP0_SENTSTALL;
147 mtu3_writel(mtu->mac_base, U3D_EP0CSR, csr);
515 u32 csr; local
520 csr = mtu3_readl(mbase, U3D_EP0CSR) & EP0_W1C_BITS;
537 csr |= EP0_RXPKTRDY;
545 csr |
567 u32 csr; local
607 u32 csr; local
702 u32 csr; local
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/linux-master/drivers/crypto/cavium/nitrox/
H A Dnitrox_mbx.c124 DECLARE_BITMAP(csr, BITS_PER_TYPE(u64));
134 bitmap_from_u64(csr, value);
135 for_each_set_bit(i, csr, BITS_PER_TYPE(csr)) {
157 bitmap_from_u64(csr, value);
158 for_each_set_bit(i, csr, BITS_PER_TYPE(csr)) {
/linux-master/arch/riscv/kernel/
H A Dvector.c18 #include <asm/csr.h>
72 u32 width, csr; local
93 csr = RVG_EXTRACT_SYSTEM_CSR(insn_buf);
94 if ((csr >= CSR_VSTART && csr <= CSR_VCSR) ||
95 (csr >= CSR_VL && csr <= CSR_VLENB))
H A Dhibernate-asm.S13 #include <asm/csr.h>
/linux-master/arch/loongarch/kvm/
H A Dmain.c19 int get_gcsr_flag(int csr) argument
21 if (csr < CSR_MAX_NUMS)
22 return gcsr_flag[csr];
27 static inline void set_gcsr_sw_flag(int csr) argument
29 if (csr < CSR_MAX_NUMS)
30 gcsr_flag[csr] |= SW_GCSR;
33 static inline void set_gcsr_hw_flag(int csr) argument
35 if (csr < CSR_MAX_NUMS)
36 gcsr_flag[csr] |= HW_GCSR;
44 * else use software csr t
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/linux-master/drivers/mtd/devices/
H A Dms02-nv.h96 struct resource *csr; member in struct:ms02nv_private::__anon688
/linux-master/arch/riscv/include/asm/
H A Dtimex.h9 #include <asm/csr.h>
H A Dcsr.h486 #define csr_swap(csr, val) \
489 __asm__ __volatile__ ("csrrw %0, " __ASM_STR(csr) ", %1"\
495 #define csr_read(csr) \
498 __asm__ __volatile__ ("csrr %0, " __ASM_STR(csr) \
504 #define csr_write(csr, val) \
507 __asm__ __volatile__ ("csrw " __ASM_STR(csr) ", %0" \
512 #define csr_read_set(csr, val) \
515 __asm__ __volatile__ ("csrrs %0, " __ASM_STR(csr) ", %1"\
521 #define csr_set(csr, val) \
524 __asm__ __volatile__ ("csrs " __ASM_STR(csr) ",
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/linux-master/tools/testing/selftests/kvm/include/riscv/
H A Darch_timer.h11 #include <asm/csr.h>
/linux-master/include/linux/irqchip/
H A Driscv-imsic.h11 #include <asm/csr.h>
/linux-master/drivers/dma/
H A Dfsl-edma-trace.h75 __field(u16, csr)
89 __entry->csr = fsl_edma_get_tcd_to_cpu(chan, tcd, csr),
102 " csr: 0x%04x\n"
113 __entry->csr,
/linux-master/arch/loongarch/include/asm/
H A Dkvm_host.h170 struct loongarch_csrs *csr; member in struct:kvm_vcpu_arch
206 static inline unsigned long readl_sw_gcsr(struct loongarch_csrs *csr, int reg) argument
208 return csr->csrs[reg];
211 static inline void writel_sw_gcsr(struct loongarch_csrs *csr, int reg, unsigned long val) argument
213 csr->csrs[reg] = val;
285 int get_gcsr_flag(int csr);
/linux-master/drivers/net/wireless/ath/wil6210/
H A Dinterrupt.c293 isr = wil_ioread32_and_clear(wil->csr +
355 isr = wil_ioread32_and_clear(wil->csr +
406 isr = wil_ioread32_and_clear(wil->csr +
452 isr = wil_ioread32_and_clear(wil->csr +
508 wil_memcpy_fromio_32(&wil->mbox_ctl, wil->csr + HOST_MBOX,
540 isr = wil_ioread32_and_clear(wil->csr +
683 icm_rx = wil_ioread32_and_clear(wil->csr +
686 icr_rx = wil_ioread32_and_clear(wil->csr +
691 icm_tx = wil_ioread32_and_clear(wil->csr +
694 icr_tx = wil_ioread32_and_clear(wil->csr
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/linux-master/drivers/crypto/intel/qat/qat_common/
H A Dqat_hal.c77 unsigned char ae, unsigned int csr)
83 value = GET_AE_CSR(handle, ae, csr);
93 unsigned char ae, unsigned int csr,
99 SET_AE_CSR(handle, ae, csr, value);
125 unsigned int csr = (1 << ACS_ABO_BITPOS); local
133 csr = qat_hal_rd_ae_csr(handle, ae, ACTIVE_CTX_STATUS);
143 if (elapsed_cycles >= 8 && !(csr & (1 << ACS_ABO_BITPOS)))
159 unsigned int csr, new_csr; local
167 csr = qat_hal_rd_ae_csr(handle, ae, CTX_ENABLES);
168 csr
76 qat_hal_rd_ae_csr(struct icp_qat_fw_loader_handle *handle, unsigned char ae, unsigned int csr) argument
92 qat_hal_wr_ae_csr(struct icp_qat_fw_loader_handle *handle, unsigned char ae, unsigned int csr, unsigned int value) argument
179 unsigned int csr, new_csr; local
198 unsigned int csr, new_csr; local
236 unsigned int csr, new_csr; local
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/linux-master/drivers/usb/musb/
H A Dtusb6010_omap.c166 u16 csr; local
171 csr = musb_readw(hw_ep->regs, MUSB_TXCSR);
172 csr |= MUSB_TXCSR_MODE | MUSB_TXCSR_TXPKTRDY
174 musb_writew(hw_ep->regs, MUSB_TXCSR, csr);
193 u16 csr; local
328 csr = musb_readw(hw_ep->regs, MUSB_TXCSR);
329 csr |= (MUSB_TXCSR_AUTOSET | MUSB_TXCSR_DMAENAB
331 csr &= ~MUSB_TXCSR_P_UNDERRUN;
332 musb_writew(hw_ep->regs, MUSB_TXCSR, csr);
334 csr
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/linux-master/drivers/edac/
H A Dedac_mc.c181 struct csrow_info *csr; local
192 csr = mci->csrows[row];
193 if (!csr)
196 if (csr->channels) {
198 kfree(csr->channels[chn]);
199 kfree(csr->channels);
201 kfree(csr);
224 struct csrow_info *csr; local
226 csr = kzalloc(sizeof(**mci->csrows), GFP_KERNEL);
227 if (!csr)
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