1/* SPDX-License-Identifier: GPL-2.0-only */ 2/* 3 * Copyright (C) 2015 Regents of the University of California 4 */ 5 6#ifndef _ASM_RISCV_CSR_H 7#define _ASM_RISCV_CSR_H 8 9#include <asm/asm.h> 10#include <linux/bits.h> 11 12/* Status register flags */ 13#define SR_SIE _AC(0x00000002, UL) /* Supervisor Interrupt Enable */ 14#define SR_MIE _AC(0x00000008, UL) /* Machine Interrupt Enable */ 15#define SR_SPIE _AC(0x00000020, UL) /* Previous Supervisor IE */ 16#define SR_MPIE _AC(0x00000080, UL) /* Previous Machine IE */ 17#define SR_SPP _AC(0x00000100, UL) /* Previously Supervisor */ 18#define SR_MPP _AC(0x00001800, UL) /* Previously Machine */ 19#define SR_SUM _AC(0x00040000, UL) /* Supervisor User Memory Access */ 20 21#define SR_FS _AC(0x00006000, UL) /* Floating-point Status */ 22#define SR_FS_OFF _AC(0x00000000, UL) 23#define SR_FS_INITIAL _AC(0x00002000, UL) 24#define SR_FS_CLEAN _AC(0x00004000, UL) 25#define SR_FS_DIRTY _AC(0x00006000, UL) 26 27#define SR_VS _AC(0x00000600, UL) /* Vector Status */ 28#define SR_VS_OFF _AC(0x00000000, UL) 29#define SR_VS_INITIAL _AC(0x00000200, UL) 30#define SR_VS_CLEAN _AC(0x00000400, UL) 31#define SR_VS_DIRTY _AC(0x00000600, UL) 32 33#define SR_XS _AC(0x00018000, UL) /* Extension Status */ 34#define SR_XS_OFF _AC(0x00000000, UL) 35#define SR_XS_INITIAL _AC(0x00008000, UL) 36#define SR_XS_CLEAN _AC(0x00010000, UL) 37#define SR_XS_DIRTY _AC(0x00018000, UL) 38 39#define SR_FS_VS (SR_FS | SR_VS) /* Vector and Floating-Point Unit */ 40 41#ifndef CONFIG_64BIT 42#define SR_SD _AC(0x80000000, UL) /* FS/VS/XS dirty */ 43#else 44#define SR_SD _AC(0x8000000000000000, UL) /* FS/VS/XS dirty */ 45#endif 46 47#ifdef CONFIG_64BIT 48#define SR_UXL _AC(0x300000000, UL) /* XLEN mask for U-mode */ 49#define SR_UXL_32 _AC(0x100000000, UL) /* XLEN = 32 for U-mode */ 50#define SR_UXL_64 _AC(0x200000000, UL) /* XLEN = 64 for U-mode */ 51#endif 52 53/* SATP flags */ 54#ifndef CONFIG_64BIT 55#define SATP_PPN _AC(0x003FFFFF, UL) 56#define SATP_MODE_32 _AC(0x80000000, UL) 57#define SATP_MODE_SHIFT 31 58#define SATP_ASID_BITS 9 59#define SATP_ASID_SHIFT 22 60#define SATP_ASID_MASK _AC(0x1FF, UL) 61#else 62#define SATP_PPN _AC(0x00000FFFFFFFFFFF, UL) 63#define SATP_MODE_39 _AC(0x8000000000000000, UL) 64#define SATP_MODE_48 _AC(0x9000000000000000, UL) 65#define SATP_MODE_57 _AC(0xa000000000000000, UL) 66#define SATP_MODE_SHIFT 60 67#define SATP_ASID_BITS 16 68#define SATP_ASID_SHIFT 44 69#define SATP_ASID_MASK _AC(0xFFFF, UL) 70#endif 71 72/* Exception cause high bit - is an interrupt if set */ 73#define CAUSE_IRQ_FLAG (_AC(1, UL) << (__riscv_xlen - 1)) 74 75/* Interrupt causes (minus the high bit) */ 76#define IRQ_S_SOFT 1 77#define IRQ_VS_SOFT 2 78#define IRQ_M_SOFT 3 79#define IRQ_S_TIMER 5 80#define IRQ_VS_TIMER 6 81#define IRQ_M_TIMER 7 82#define IRQ_S_EXT 9 83#define IRQ_VS_EXT 10 84#define IRQ_M_EXT 11 85#define IRQ_S_GEXT 12 86#define IRQ_PMU_OVF 13 87#define IRQ_LOCAL_MAX (IRQ_PMU_OVF + 1) 88#define IRQ_LOCAL_MASK GENMASK((IRQ_LOCAL_MAX - 1), 0) 89 90/* Exception causes */ 91#define EXC_INST_MISALIGNED 0 92#define EXC_INST_ACCESS 1 93#define EXC_INST_ILLEGAL 2 94#define EXC_BREAKPOINT 3 95#define EXC_LOAD_MISALIGNED 4 96#define EXC_LOAD_ACCESS 5 97#define EXC_STORE_MISALIGNED 6 98#define EXC_STORE_ACCESS 7 99#define EXC_SYSCALL 8 100#define EXC_HYPERVISOR_SYSCALL 9 101#define EXC_SUPERVISOR_SYSCALL 10 102#define EXC_INST_PAGE_FAULT 12 103#define EXC_LOAD_PAGE_FAULT 13 104#define EXC_STORE_PAGE_FAULT 15 105#define EXC_INST_GUEST_PAGE_FAULT 20 106#define EXC_LOAD_GUEST_PAGE_FAULT 21 107#define EXC_VIRTUAL_INST_FAULT 22 108#define EXC_STORE_GUEST_PAGE_FAULT 23 109 110/* PMP configuration */ 111#define PMP_R 0x01 112#define PMP_W 0x02 113#define PMP_X 0x04 114#define PMP_A 0x18 115#define PMP_A_TOR 0x08 116#define PMP_A_NA4 0x10 117#define PMP_A_NAPOT 0x18 118#define PMP_L 0x80 119 120/* HSTATUS flags */ 121#ifdef CONFIG_64BIT 122#define HSTATUS_VSXL _AC(0x300000000, UL) 123#define HSTATUS_VSXL_SHIFT 32 124#endif 125#define HSTATUS_VTSR _AC(0x00400000, UL) 126#define HSTATUS_VTW _AC(0x00200000, UL) 127#define HSTATUS_VTVM _AC(0x00100000, UL) 128#define HSTATUS_VGEIN _AC(0x0003f000, UL) 129#define HSTATUS_VGEIN_SHIFT 12 130#define HSTATUS_HU _AC(0x00000200, UL) 131#define HSTATUS_SPVP _AC(0x00000100, UL) 132#define HSTATUS_SPV _AC(0x00000080, UL) 133#define HSTATUS_GVA _AC(0x00000040, UL) 134#define HSTATUS_VSBE _AC(0x00000020, UL) 135 136/* HGATP flags */ 137#define HGATP_MODE_OFF _AC(0, UL) 138#define HGATP_MODE_SV32X4 _AC(1, UL) 139#define HGATP_MODE_SV39X4 _AC(8, UL) 140#define HGATP_MODE_SV48X4 _AC(9, UL) 141#define HGATP_MODE_SV57X4 _AC(10, UL) 142 143#define HGATP32_MODE_SHIFT 31 144#define HGATP32_VMID_SHIFT 22 145#define HGATP32_VMID GENMASK(28, 22) 146#define HGATP32_PPN GENMASK(21, 0) 147 148#define HGATP64_MODE_SHIFT 60 149#define HGATP64_VMID_SHIFT 44 150#define HGATP64_VMID GENMASK(57, 44) 151#define HGATP64_PPN GENMASK(43, 0) 152 153#define HGATP_PAGE_SHIFT 12 154 155#ifdef CONFIG_64BIT 156#define HGATP_PPN HGATP64_PPN 157#define HGATP_VMID_SHIFT HGATP64_VMID_SHIFT 158#define HGATP_VMID HGATP64_VMID 159#define HGATP_MODE_SHIFT HGATP64_MODE_SHIFT 160#else 161#define HGATP_PPN HGATP32_PPN 162#define HGATP_VMID_SHIFT HGATP32_VMID_SHIFT 163#define HGATP_VMID HGATP32_VMID 164#define HGATP_MODE_SHIFT HGATP32_MODE_SHIFT 165#endif 166 167/* VSIP & HVIP relation */ 168#define VSIP_TO_HVIP_SHIFT (IRQ_VS_SOFT - IRQ_S_SOFT) 169#define VSIP_VALID_MASK ((_AC(1, UL) << IRQ_S_SOFT) | \ 170 (_AC(1, UL) << IRQ_S_TIMER) | \ 171 (_AC(1, UL) << IRQ_S_EXT)) 172 173/* AIA CSR bits */ 174#define TOPI_IID_SHIFT 16 175#define TOPI_IID_MASK GENMASK(11, 0) 176#define TOPI_IPRIO_MASK GENMASK(7, 0) 177#define TOPI_IPRIO_BITS 8 178 179#define TOPEI_ID_SHIFT 16 180#define TOPEI_ID_MASK GENMASK(10, 0) 181#define TOPEI_PRIO_MASK GENMASK(10, 0) 182 183#define ISELECT_IPRIO0 0x30 184#define ISELECT_IPRIO15 0x3f 185#define ISELECT_MASK GENMASK(8, 0) 186 187#define HVICTL_VTI BIT(30) 188#define HVICTL_IID GENMASK(27, 16) 189#define HVICTL_IID_SHIFT 16 190#define HVICTL_DPR BIT(9) 191#define HVICTL_IPRIOM BIT(8) 192#define HVICTL_IPRIO GENMASK(7, 0) 193 194/* xENVCFG flags */ 195#define ENVCFG_STCE (_AC(1, ULL) << 63) 196#define ENVCFG_PBMTE (_AC(1, ULL) << 62) 197#define ENVCFG_CBZE (_AC(1, UL) << 7) 198#define ENVCFG_CBCFE (_AC(1, UL) << 6) 199#define ENVCFG_CBIE_SHIFT 4 200#define ENVCFG_CBIE (_AC(0x3, UL) << ENVCFG_CBIE_SHIFT) 201#define ENVCFG_CBIE_ILL _AC(0x0, UL) 202#define ENVCFG_CBIE_FLUSH _AC(0x1, UL) 203#define ENVCFG_CBIE_INV _AC(0x3, UL) 204#define ENVCFG_FIOM _AC(0x1, UL) 205 206/* Smstateen bits */ 207#define SMSTATEEN0_AIA_IMSIC_SHIFT 58 208#define SMSTATEEN0_AIA_IMSIC (_ULL(1) << SMSTATEEN0_AIA_IMSIC_SHIFT) 209#define SMSTATEEN0_AIA_SHIFT 59 210#define SMSTATEEN0_AIA (_ULL(1) << SMSTATEEN0_AIA_SHIFT) 211#define SMSTATEEN0_AIA_ISEL_SHIFT 60 212#define SMSTATEEN0_AIA_ISEL (_ULL(1) << SMSTATEEN0_AIA_ISEL_SHIFT) 213#define SMSTATEEN0_HSENVCFG_SHIFT 62 214#define SMSTATEEN0_HSENVCFG (_ULL(1) << SMSTATEEN0_HSENVCFG_SHIFT) 215#define SMSTATEEN0_SSTATEEN0_SHIFT 63 216#define SMSTATEEN0_SSTATEEN0 (_ULL(1) << SMSTATEEN0_SSTATEEN0_SHIFT) 217 218/* symbolic CSR names: */ 219#define CSR_CYCLE 0xc00 220#define CSR_TIME 0xc01 221#define CSR_INSTRET 0xc02 222#define CSR_HPMCOUNTER3 0xc03 223#define CSR_HPMCOUNTER4 0xc04 224#define CSR_HPMCOUNTER5 0xc05 225#define CSR_HPMCOUNTER6 0xc06 226#define CSR_HPMCOUNTER7 0xc07 227#define CSR_HPMCOUNTER8 0xc08 228#define CSR_HPMCOUNTER9 0xc09 229#define CSR_HPMCOUNTER10 0xc0a 230#define CSR_HPMCOUNTER11 0xc0b 231#define CSR_HPMCOUNTER12 0xc0c 232#define CSR_HPMCOUNTER13 0xc0d 233#define CSR_HPMCOUNTER14 0xc0e 234#define CSR_HPMCOUNTER15 0xc0f 235#define CSR_HPMCOUNTER16 0xc10 236#define CSR_HPMCOUNTER17 0xc11 237#define CSR_HPMCOUNTER18 0xc12 238#define CSR_HPMCOUNTER19 0xc13 239#define CSR_HPMCOUNTER20 0xc14 240#define CSR_HPMCOUNTER21 0xc15 241#define CSR_HPMCOUNTER22 0xc16 242#define CSR_HPMCOUNTER23 0xc17 243#define CSR_HPMCOUNTER24 0xc18 244#define CSR_HPMCOUNTER25 0xc19 245#define CSR_HPMCOUNTER26 0xc1a 246#define CSR_HPMCOUNTER27 0xc1b 247#define CSR_HPMCOUNTER28 0xc1c 248#define CSR_HPMCOUNTER29 0xc1d 249#define CSR_HPMCOUNTER30 0xc1e 250#define CSR_HPMCOUNTER31 0xc1f 251#define CSR_CYCLEH 0xc80 252#define CSR_TIMEH 0xc81 253#define CSR_INSTRETH 0xc82 254#define CSR_HPMCOUNTER3H 0xc83 255#define CSR_HPMCOUNTER4H 0xc84 256#define CSR_HPMCOUNTER5H 0xc85 257#define CSR_HPMCOUNTER6H 0xc86 258#define CSR_HPMCOUNTER7H 0xc87 259#define CSR_HPMCOUNTER8H 0xc88 260#define CSR_HPMCOUNTER9H 0xc89 261#define CSR_HPMCOUNTER10H 0xc8a 262#define CSR_HPMCOUNTER11H 0xc8b 263#define CSR_HPMCOUNTER12H 0xc8c 264#define CSR_HPMCOUNTER13H 0xc8d 265#define CSR_HPMCOUNTER14H 0xc8e 266#define CSR_HPMCOUNTER15H 0xc8f 267#define CSR_HPMCOUNTER16H 0xc90 268#define CSR_HPMCOUNTER17H 0xc91 269#define CSR_HPMCOUNTER18H 0xc92 270#define CSR_HPMCOUNTER19H 0xc93 271#define CSR_HPMCOUNTER20H 0xc94 272#define CSR_HPMCOUNTER21H 0xc95 273#define CSR_HPMCOUNTER22H 0xc96 274#define CSR_HPMCOUNTER23H 0xc97 275#define CSR_HPMCOUNTER24H 0xc98 276#define CSR_HPMCOUNTER25H 0xc99 277#define CSR_HPMCOUNTER26H 0xc9a 278#define CSR_HPMCOUNTER27H 0xc9b 279#define CSR_HPMCOUNTER28H 0xc9c 280#define CSR_HPMCOUNTER29H 0xc9d 281#define CSR_HPMCOUNTER30H 0xc9e 282#define CSR_HPMCOUNTER31H 0xc9f 283 284#define CSR_SSCOUNTOVF 0xda0 285 286#define CSR_SSTATUS 0x100 287#define CSR_SIE 0x104 288#define CSR_STVEC 0x105 289#define CSR_SCOUNTEREN 0x106 290#define CSR_SENVCFG 0x10a 291#define CSR_SSTATEEN0 0x10c 292#define CSR_SSCRATCH 0x140 293#define CSR_SEPC 0x141 294#define CSR_SCAUSE 0x142 295#define CSR_STVAL 0x143 296#define CSR_SIP 0x144 297#define CSR_SATP 0x180 298 299#define CSR_STIMECMP 0x14D 300#define CSR_STIMECMPH 0x15D 301 302/* Supervisor-Level Window to Indirectly Accessed Registers (AIA) */ 303#define CSR_SISELECT 0x150 304#define CSR_SIREG 0x151 305 306/* Supervisor-Level Interrupts (AIA) */ 307#define CSR_STOPEI 0x15c 308#define CSR_STOPI 0xdb0 309 310/* Supervisor-Level High-Half CSRs (AIA) */ 311#define CSR_SIEH 0x114 312#define CSR_SIPH 0x154 313 314#define CSR_VSSTATUS 0x200 315#define CSR_VSIE 0x204 316#define CSR_VSTVEC 0x205 317#define CSR_VSSCRATCH 0x240 318#define CSR_VSEPC 0x241 319#define CSR_VSCAUSE 0x242 320#define CSR_VSTVAL 0x243 321#define CSR_VSIP 0x244 322#define CSR_VSATP 0x280 323#define CSR_VSTIMECMP 0x24D 324#define CSR_VSTIMECMPH 0x25D 325 326#define CSR_HSTATUS 0x600 327#define CSR_HEDELEG 0x602 328#define CSR_HIDELEG 0x603 329#define CSR_HIE 0x604 330#define CSR_HTIMEDELTA 0x605 331#define CSR_HCOUNTEREN 0x606 332#define CSR_HGEIE 0x607 333#define CSR_HENVCFG 0x60a 334#define CSR_HTIMEDELTAH 0x615 335#define CSR_HENVCFGH 0x61a 336#define CSR_HTVAL 0x643 337#define CSR_HIP 0x644 338#define CSR_HVIP 0x645 339#define CSR_HTINST 0x64a 340#define CSR_HGATP 0x680 341#define CSR_HGEIP 0xe12 342 343/* Virtual Interrupts and Interrupt Priorities (H-extension with AIA) */ 344#define CSR_HVIEN 0x608 345#define CSR_HVICTL 0x609 346#define CSR_HVIPRIO1 0x646 347#define CSR_HVIPRIO2 0x647 348 349/* VS-Level Window to Indirectly Accessed Registers (H-extension with AIA) */ 350#define CSR_VSISELECT 0x250 351#define CSR_VSIREG 0x251 352 353/* VS-Level Interrupts (H-extension with AIA) */ 354#define CSR_VSTOPEI 0x25c 355#define CSR_VSTOPI 0xeb0 356 357/* Hypervisor and VS-Level High-Half CSRs (H-extension with AIA) */ 358#define CSR_HIDELEGH 0x613 359#define CSR_HVIENH 0x618 360#define CSR_HVIPH 0x655 361#define CSR_HVIPRIO1H 0x656 362#define CSR_HVIPRIO2H 0x657 363#define CSR_VSIEH 0x214 364#define CSR_VSIPH 0x254 365 366/* Hypervisor stateen CSRs */ 367#define CSR_HSTATEEN0 0x60c 368#define CSR_HSTATEEN0H 0x61c 369 370#define CSR_MSTATUS 0x300 371#define CSR_MISA 0x301 372#define CSR_MIDELEG 0x303 373#define CSR_MIE 0x304 374#define CSR_MTVEC 0x305 375#define CSR_MENVCFG 0x30a 376#define CSR_MENVCFGH 0x31a 377#define CSR_MSCRATCH 0x340 378#define CSR_MEPC 0x341 379#define CSR_MCAUSE 0x342 380#define CSR_MTVAL 0x343 381#define CSR_MIP 0x344 382#define CSR_PMPCFG0 0x3a0 383#define CSR_PMPADDR0 0x3b0 384#define CSR_MVENDORID 0xf11 385#define CSR_MARCHID 0xf12 386#define CSR_MIMPID 0xf13 387#define CSR_MHARTID 0xf14 388 389/* Machine-Level Window to Indirectly Accessed Registers (AIA) */ 390#define CSR_MISELECT 0x350 391#define CSR_MIREG 0x351 392 393/* Machine-Level Interrupts (AIA) */ 394#define CSR_MTOPEI 0x35c 395#define CSR_MTOPI 0xfb0 396 397/* Virtual Interrupts for Supervisor Level (AIA) */ 398#define CSR_MVIEN 0x308 399#define CSR_MVIP 0x309 400 401/* Machine-Level High-Half CSRs (AIA) */ 402#define CSR_MIDELEGH 0x313 403#define CSR_MIEH 0x314 404#define CSR_MVIENH 0x318 405#define CSR_MVIPH 0x319 406#define CSR_MIPH 0x354 407 408#define CSR_VSTART 0x8 409#define CSR_VCSR 0xf 410#define CSR_VL 0xc20 411#define CSR_VTYPE 0xc21 412#define CSR_VLENB 0xc22 413 414/* Scalar Crypto Extension - Entropy */ 415#define CSR_SEED 0x015 416#define SEED_OPST_MASK _AC(0xC0000000, UL) 417#define SEED_OPST_BIST _AC(0x00000000, UL) 418#define SEED_OPST_WAIT _AC(0x40000000, UL) 419#define SEED_OPST_ES16 _AC(0x80000000, UL) 420#define SEED_OPST_DEAD _AC(0xC0000000, UL) 421#define SEED_ENTROPY_MASK _AC(0xFFFF, UL) 422 423#ifdef CONFIG_RISCV_M_MODE 424# define CSR_STATUS CSR_MSTATUS 425# define CSR_IE CSR_MIE 426# define CSR_TVEC CSR_MTVEC 427# define CSR_ENVCFG CSR_MENVCFG 428# define CSR_SCRATCH CSR_MSCRATCH 429# define CSR_EPC CSR_MEPC 430# define CSR_CAUSE CSR_MCAUSE 431# define CSR_TVAL CSR_MTVAL 432# define CSR_IP CSR_MIP 433 434# define CSR_IEH CSR_MIEH 435# define CSR_ISELECT CSR_MISELECT 436# define CSR_IREG CSR_MIREG 437# define CSR_IPH CSR_MIPH 438# define CSR_TOPEI CSR_MTOPEI 439# define CSR_TOPI CSR_MTOPI 440 441# define SR_IE SR_MIE 442# define SR_PIE SR_MPIE 443# define SR_PP SR_MPP 444 445# define RV_IRQ_SOFT IRQ_M_SOFT 446# define RV_IRQ_TIMER IRQ_M_TIMER 447# define RV_IRQ_EXT IRQ_M_EXT 448#else /* CONFIG_RISCV_M_MODE */ 449# define CSR_STATUS CSR_SSTATUS 450# define CSR_IE CSR_SIE 451# define CSR_TVEC CSR_STVEC 452# define CSR_ENVCFG CSR_SENVCFG 453# define CSR_SCRATCH CSR_SSCRATCH 454# define CSR_EPC CSR_SEPC 455# define CSR_CAUSE CSR_SCAUSE 456# define CSR_TVAL CSR_STVAL 457# define CSR_IP CSR_SIP 458 459# define CSR_IEH CSR_SIEH 460# define CSR_ISELECT CSR_SISELECT 461# define CSR_IREG CSR_SIREG 462# define CSR_IPH CSR_SIPH 463# define CSR_TOPEI CSR_STOPEI 464# define CSR_TOPI CSR_STOPI 465 466# define SR_IE SR_SIE 467# define SR_PIE SR_SPIE 468# define SR_PP SR_SPP 469 470# define RV_IRQ_SOFT IRQ_S_SOFT 471# define RV_IRQ_TIMER IRQ_S_TIMER 472# define RV_IRQ_EXT IRQ_S_EXT 473# define RV_IRQ_PMU IRQ_PMU_OVF 474# define SIP_LCOFIP (_AC(0x1, UL) << IRQ_PMU_OVF) 475 476#endif /* !CONFIG_RISCV_M_MODE */ 477 478/* IE/IP (Supervisor/Machine Interrupt Enable/Pending) flags */ 479#define IE_SIE (_AC(0x1, UL) << RV_IRQ_SOFT) 480#define IE_TIE (_AC(0x1, UL) << RV_IRQ_TIMER) 481#define IE_EIE (_AC(0x1, UL) << RV_IRQ_EXT) 482 483#ifndef __ASSEMBLY__ 484 485#define csr_swap(csr, val) \ 486({ \ 487 unsigned long __v = (unsigned long)(val); \ 488 __asm__ __volatile__ ("csrrw %0, " __ASM_STR(csr) ", %1"\ 489 : "=r" (__v) : "rK" (__v) \ 490 : "memory"); \ 491 __v; \ 492}) 493 494#define csr_read(csr) \ 495({ \ 496 register unsigned long __v; \ 497 __asm__ __volatile__ ("csrr %0, " __ASM_STR(csr) \ 498 : "=r" (__v) : \ 499 : "memory"); \ 500 __v; \ 501}) 502 503#define csr_write(csr, val) \ 504({ \ 505 unsigned long __v = (unsigned long)(val); \ 506 __asm__ __volatile__ ("csrw " __ASM_STR(csr) ", %0" \ 507 : : "rK" (__v) \ 508 : "memory"); \ 509}) 510 511#define csr_read_set(csr, val) \ 512({ \ 513 unsigned long __v = (unsigned long)(val); \ 514 __asm__ __volatile__ ("csrrs %0, " __ASM_STR(csr) ", %1"\ 515 : "=r" (__v) : "rK" (__v) \ 516 : "memory"); \ 517 __v; \ 518}) 519 520#define csr_set(csr, val) \ 521({ \ 522 unsigned long __v = (unsigned long)(val); \ 523 __asm__ __volatile__ ("csrs " __ASM_STR(csr) ", %0" \ 524 : : "rK" (__v) \ 525 : "memory"); \ 526}) 527 528#define csr_read_clear(csr, val) \ 529({ \ 530 unsigned long __v = (unsigned long)(val); \ 531 __asm__ __volatile__ ("csrrc %0, " __ASM_STR(csr) ", %1"\ 532 : "=r" (__v) : "rK" (__v) \ 533 : "memory"); \ 534 __v; \ 535}) 536 537#define csr_clear(csr, val) \ 538({ \ 539 unsigned long __v = (unsigned long)(val); \ 540 __asm__ __volatile__ ("csrc " __ASM_STR(csr) ", %0" \ 541 : : "rK" (__v) \ 542 : "memory"); \ 543}) 544 545#endif /* __ASSEMBLY__ */ 546 547#endif /* _ASM_RISCV_CSR_H */ 548