/freebsd-13-stable/contrib/llvm-project/llvm/lib/CodeGen/ |
H A D | SwiftErrorValueTracking.cpp | 83 TII = MF->getSubtarget().getInstrInfo(); 137 TII->get(TargetOpcode::IMPLICIT_DEF), VReg); 224 const auto *TII = MF->getSubtarget().getInstrInfo(); local 232 BuildMI(*MBB, MBB->getFirstNonPHI(), DLoc, TII->get(TargetOpcode::COPY), 246 TII->get(TargetOpcode::PHI), PHIVReg);
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H A D | MachineSink.cpp | 88 const TargetInstrInfo *TII; member in class:__anon3524::MachineSinking 321 TII = MF.getSubtarget().getInstrInfo(); 454 if (!MI.isCopy() && !TII->isAsCheapAsAMove(MI)) 685 if (!TII->isSafeToMoveRegClassDefs(MRI->getRegClass(Reg))) 754 const TargetInstrInfo *TII, 775 if (!TII->getMemOperandWithOffset(MI, BaseOp, Offset, OffsetIsScalable, TRI)) 785 if (TII->analyzeBranchPredicate(*PredMBB, MBP, false)) 800 const TargetInstrInfo &TII = *SinkInst.getMF()->getSubtarget().getInstrInfo(); local 808 auto CopyOperands = TII.isCopyInstr(SinkInst); 884 if (!TII 753 SinkingPreventsImplicitNullCheck(MachineInstr &MI, const TargetInstrInfo *TII, const TargetRegisterInfo *TRI) argument 1279 tryToSinkCopy(MachineBasicBlock &CurBB, MachineFunction &MF, const TargetRegisterInfo *TRI, const TargetInstrInfo *TII) argument 1400 const TargetInstrInfo *TII = MF.getSubtarget().getInstrInfo(); local [all...] |
H A D | TwoAddressInstructionPass.cpp | 93 const TargetInstrInfo *TII; member in class:__anon3597::TwoAddressInstructionPass 269 static bool isCopyToReg(MachineInstr &MI, const TargetInstrInfo *TII, argument 333 const TargetInstrInfo *TII, 356 if (!isCopyToReg(*DefMI, TII, SrcReg, DstReg, IsSrcPhys, IsDstPhys)) 383 const TargetInstrInfo *TII, 394 if (isCopyToReg(UseMI, TII, SrcReg, DstReg, IsSrcPhys, IsDstPhys)) { 549 MachineInstr *NewMI = TII->commuteInstruction(*MI, false, RegBIdx, RegCIdx); 597 MachineInstr *NewMI = TII->convertToThreeAddress(MFI, *mi, LV); 630 while (MachineInstr *UseMI = findOnlyInterestingUse(Reg, MBB, MRI, TII,IsCopy, 686 if (!isCopyToReg(*MI, TII, SrcRe 331 isKilled(MachineInstr &MI, unsigned Reg, const MachineRegisterInfo *MRI, const TargetInstrInfo *TII, LiveIntervals *LIS, bool allowFalsePositives) argument 381 findOnlyInterestingUse(unsigned Reg, MachineBasicBlock *MBB, MachineRegisterInfo *MRI, const TargetInstrInfo *TII, bool &IsCopy, unsigned &DstReg, bool &IsDstPhys) argument [all...] |
H A D | LiveRangeEdit.cpp | 76 if (!TII.isTriviallyReMaterializable(*DefMI, aa)) 155 if (cheapAsAMove && !TII.isAsCheapAsAMove(*RM.OrigMI)) 172 TII.reMaterialize(MBB, MI, DestReg, 0, *RM.OrigMI, tri); 230 MachineInstr *FoldMI = TII.foldMemoryOperand(*UseMI, Ops, *DefMI, &LIS); 350 MI->setDesc(TII.get(TargetOpcode::KILL)); 365 if (isOrigDef && DeadRemats && TII.isTriviallyReMaterializable(*MI, AA)) {
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H A D | CFIInstrInserter.cpp | 295 const TargetInstrInfo *TII = MF.getSubtarget().getInstrInfo(); local 319 BuildMI(*MBBInfo.MBB, MBBI, DL, TII->get(TargetOpcode::CFI_INSTRUCTION)) 328 BuildMI(*MBBInfo.MBB, MBBI, DL, TII->get(TargetOpcode::CFI_INSTRUCTION)) 336 BuildMI(*MBBInfo.MBB, MBBI, DL, TII->get(TargetOpcode::CFI_INSTRUCTION)) 354 BuildMI(*MBBInfo.MBB, MBBI, DL, TII->get(TargetOpcode::CFI_INSTRUCTION)) 375 BuildMI(*MBBInfo.MBB, MBBI, DL, TII->get(TargetOpcode::CFI_INSTRUCTION))
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H A D | MachineOutliner.cpp | 242 /// \param TII \p TargetInstrInfo for the function. 244 const TargetInstrInfo &TII) { 248 if (!TII.isMBBSafeToOutlineFrom(MBB, Flags)) 275 switch (TII.getOutliningType(It, Flags)) { 577 // Arbitrarily choose a TII from the first candidate. 579 const TargetInstrInfo *TII = local 583 TII->getOutliningCandidateInfo(CandidatesForRepeatedSeq); 649 const TargetInstrInfo &TII = *STI.getInstrInfo(); local 699 TII.buildOutlinedFrame(MBB, MF, OF); 773 const TargetInstrInfo &TII local 880 const TargetInstrInfo *TII = MF->getSubtarget().getInstrInfo(); local [all...] |
H A D | MachineDebugify.cpp | 41 const TargetInstrInfo &TII = *MF.getSubtarget().getInstrInfo(); local 92 const MCInstrDesc &DbgValDesc = TII.get(TargetOpcode::DBG_VALUE);
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H A D | ModuloSchedule.cpp | 111 LoopInfo = TII->analyzeLoopForPipelining(BB); 240 unsigned numBranches = TII->removeBranch(*Preheader); 243 TII->insertBranch(*Preheader, PrologBBs[0], nullptr, Cond, DebugLoc()); 259 bool checkBranch = TII->analyzeBranch(*KernelBB, TBB, FBB, Cond); 323 TII->removeBranch(*KernelBB); 324 TII->insertBranch(*KernelBB, KernelBB, EpilogStart, Cond, DebugLoc()); 329 TII->insertBranch(*LastEpilogBB, LoopExitBB, nullptr, Cond1, DebugLoc()); 554 TII->get(TargetOpcode::PHI), NewReg); 670 TII->get(TargetOpcode::PHI), NewReg); 815 TII 1257 const TargetInstrInfo *TII; member in class:__anon3534::KernelRewriter [all...] |
H A D | OptimizePHIs.cpp | 39 const TargetInstrInfo *TII; member in class:__anon3537::OptimizePHIs 79 TII = Fn.getSubtarget().getInstrInfo();
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H A D | DeadMachineInstructionElim.cpp | 35 const TargetInstrInfo *TII; member in class:__anon3452::DeadMachineInstructionElim 114 TII = MF.getSubtarget().getInstrInfo();
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/freebsd-13-stable/contrib/llvm-project/llvm/lib/Target/BPF/ |
H A D | BPFMISimplifyPatchable.cpp | 47 const BPFInstrInfo *TII; member in struct:__anon4082::BPFMISimplifyPatchable 87 TII = MF->getSubtarget<BPFSubtarget>().getInstrInfo(); 138 BuildMI(*DefInst->getParent(), *DefInst, DefInst->getDebugLoc(), TII->get(COREOp)) 153 BuildMI(MBB, *Inst, Inst->getDebugLoc(), TII->get(BPF::CORE_SHIFT)) 185 BuildMI(MBB, MI, MI.getDebugLoc(), TII->get(BPF::COPY), DstReg)
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/freebsd-13-stable/contrib/llvm-project/llvm/lib/Target/PowerPC/ |
H A D | PPCPreEmitPeephole.cpp | 190 const PPCInstrInfo *TII = MF.getSubtarget<PPCSubtarget>().getInstrInfo(); variable 203 const MCInstrDesc &MCID = TII->get(Opc); 223 if (TII->convertToImmediateForm(MI, &DefMIToErase)) { 232 if (TII->foldFrameOffset(MI)) { 286 TII->insertBranch(MBB, Br->getOperand(1).getMBB(), nullptr,
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/freebsd-13-stable/contrib/llvm-project/llvm/lib/CodeGen/SelectionDAG/ |
H A D | FastISel.cpp | 461 TII.get(TargetOpcode::IMPLICIT_DEF), Reg); 857 unsigned AdjStackDown = TII.getCallFrameSetupOpcode(); 859 BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DbgLoc, TII.get(AdjStackDown)); 866 TII.get(TargetOpcode::STACKMAP)); 871 unsigned AdjStackUp = TII.getCallFrameDestroyOpcode(); 872 BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DbgLoc, TII.get(AdjStackUp)) 1042 TII.get(TargetOpcode::PATCHPOINT)); 1071 TII.get(TargetOpcode::PATCHABLE_EVENT_CALL)); 1092 TII.get(TargetOpcode::PATCHABLE_TYPED_EVENT_CALL)); 1338 TII [all...] |
/freebsd-13-stable/contrib/llvm-project/llvm/lib/Target/Mips/ |
H A D | MipsSEISelLowering.cpp | 3037 const TargetInstrInfo *TII = Subtarget.getInstrInfo(); local 3062 BuildMI(BB, DL, TII->get(Mips::BPOSGE32)).addMBB(TBB); 3064 BuildMI(BB, DL, TII->get(Mips::BPOSGE32C_MMR3)).addMBB(TBB); 3068 BuildMI(*FBB, FBB->end(), DL, TII->get(Mips::ADDiu), VR2) 3070 BuildMI(*FBB, FBB->end(), DL, TII->get(Mips::B)).addMBB(Sink); 3074 BuildMI(*TBB, TBB->end(), DL, TII->get(Mips::ADDiu), VR1) 3078 BuildMI(*Sink, Sink->begin(), DL, TII->get(Mips::PHI), 3106 const TargetInstrInfo *TII = Subtarget.getInstrInfo(); local 3131 BuildMI(BB, DL, TII->get(BranchOp)) 3137 BuildMI(*FBB, FBB->end(), DL, TII 3171 const TargetInstrInfo *TII = Subtarget.getInstrInfo(); local 3217 const TargetInstrInfo *TII = Subtarget.getInstrInfo(); local 3246 const TargetInstrInfo *TII = Subtarget.getInstrInfo(); local 3282 const TargetInstrInfo *TII = Subtarget.getInstrInfo(); local 3328 const TargetInstrInfo *TII = Subtarget.getInstrInfo(); local 3442 const TargetInstrInfo *TII = Subtarget.getInstrInfo(); local 3477 const TargetInstrInfo *TII = Subtarget.getInstrInfo(); local 3511 const TargetInstrInfo *TII = Subtarget.getInstrInfo(); local 3566 const TargetInstrInfo *TII = Subtarget.getInstrInfo(); local 3661 const TargetInstrInfo *TII = Subtarget.getInstrInfo(); local 3766 const TargetInstrInfo *TII = Subtarget.getInstrInfo(); local 3819 const TargetInstrInfo *TII = Subtarget.getInstrInfo(); local 3848 const TargetInstrInfo *TII = Subtarget.getInstrInfo(); local [all...] |
H A D | MipsISelLowering.cpp | 1267 const TargetInstrInfo &TII, 1277 TII.get(IsMicroMips ? Mips::TEQ_MM : Mips::TEQ)) 1474 const TargetInstrInfo *TII = Subtarget.getInstrInfo(); local 1603 BuildMI(*BB, II, DL, TII->get(Mips::COPY), IncrCopy).addReg(Incr); 1604 BuildMI(*BB, II, DL, TII->get(Mips::COPY), PtrCopy).addReg(Ptr); 1607 BuildMI(*BB, II, DL, TII->get(AtomicOp)) 1628 const TargetInstrInfo *TII = Subtarget.getInstrInfo(); local 1632 BuildMI(BB, DL, TII->get(Mips::SEB), DstReg).addReg(SrcReg); 1637 BuildMI(BB, DL, TII->get(Mips::SEH), DstReg).addReg(SrcReg); 1649 BuildMI(BB, DL, TII 1265 insertDivByZeroTrap(MachineInstr &MI, MachineBasicBlock &MBB, const TargetInstrInfo &TII, bool Is64Bit, bool IsMicroMips) argument 1666 const TargetInstrInfo *TII = Subtarget.getInstrInfo(); local 1859 const TargetInstrInfo *TII = Subtarget.getInstrInfo(); local 1914 const TargetInstrInfo *TII = Subtarget.getInstrInfo(); local 4577 const TargetInstrInfo *TII = local 4654 const TargetInstrInfo *TII = Subtarget.getInstrInfo(); local 4750 const TargetInstrInfo *TII = Subtarget.getInstrInfo(); local 4796 const TargetInstrInfo *TII = Subtarget.getInstrInfo(); local 4880 const TargetInstrInfo *TII = Subtarget.getInstrInfo(); local 4930 const TargetInstrInfo *TII = Subtarget.getInstrInfo(); local [all...] |
H A D | MipsDelaySlotFiller.cpp | 564 const MipsInstrInfo *TII = STI.getInstrInfo(); local 566 unsigned NewOpcode = TII->getEquivalentCompactForm(Branch); 567 Branch = TII->genInstrWithNewOpc(NewOpcode, Branch); 606 const MipsInstrInfo *TII = STI.getInstrInfo(); local 619 !TII->getEquivalentCompactForm(I)) { 641 if (InMicroMipsMode && TII->getInstSizeInBytes(*std::next(DSI)) == 2 && 651 DSI->setDesc(TII->get(getEquivalentCallShort(DSI->getOpcode()))); 670 TII->getEquivalentCompactForm(I)) { 679 BuildMI(MBB, std::next(I), I->getDebugLoc(), TII->get(Mips::NOP)); 743 const MipsInstrInfo *TII local 887 const MipsInstrInfo *TII = local [all...] |
/freebsd-13-stable/contrib/llvm-project/llvm/lib/Target/ARM/ |
H A D | ARMBaseRegisterInfo.cpp | 476 const TargetInstrInfo &TII = *MF.getSubtarget().getInstrInfo(); local 482 BuildMI(MBB, MBBI, dl, TII.get(ARM::LDRcp)) 652 const TargetInstrInfo &TII = *MF.getSubtarget().getInstrInfo(); local 653 const MCInstrDesc &MCID = TII.get(ADDriOpc); 654 MRI.constrainRegClass(BaseReg, TII.getRegClass(MCID, 0, this, MF)); 667 const ARMBaseInstrInfo &TII = local 682 Done = rewriteARMFrameIndex(MI, i, BaseReg, Off, TII); 685 Done = rewriteT2FrameIndex(MI, i, BaseReg, Off, TII, this); 764 const ARMBaseInstrInfo &TII = local 795 Done = rewriteARMFrameIndex(MI, FIOperandNum, FrameReg, Offset, TII); [all...] |
H A D | ARMConstantIslandPass.cpp | 211 const ARMBaseInstrInfo *TII; member in class:__anon4012::ARMConstantIslands 351 TII = STI->getInstrInfo(); 519 BuildMI(*BB, InsAt, DebugLoc(), TII->get(ARM::CONSTPOOL_ENTRY)) 587 DebugLoc(), TII->get(JTOpcode)) 620 bool TooDifficult = TII->analyzeBranch(*MBB, TBB, FBB, Cond); 899 BuildMI(OrigBB, DebugLoc(), TII->get(Opc)).addMBB(NewBB); 901 BuildMI(OrigBB, DebugLoc(), TII->get(Opc)) 1285 BuildMI(UserMBB, DebugLoc(), TII->get(UncondBr)).addMBB(NewMBB); 1287 BuildMI(UserMBB, DebugLoc(), TII->get(UncondBr)) 1341 UserOffset + TII [all...] |
/freebsd-13-stable/contrib/llvm-project/llvm/lib/Target/Hexagon/ |
H A D | HexagonStoreWidening.cpp | 65 const HexagonInstrInfo *TII; member in struct:__anon4149::HexagonStoreWidening 430 const MCInstrDesc &StD = TII->get(WOpc); 442 const MCInstrDesc &TfrD = TII->get(Hexagon::A2_tfrsi); 443 const TargetRegisterClass *RC = TII->getRegClass(TfrD, 0, TRI, *MF); 453 const MCInstrDesc &StD = TII->get(WOpc); 592 TII = ST.getInstrInfo();
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H A D | HexagonCFGOptimizer.cpp | 82 const TargetInstrInfo *TII = local 102 MI.setDesc(TII->get(NewOpcode));
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H A D | HexagonFixupHwLoops.cpp | 170 const TargetInstrInfo *TII = MF.getSubtarget().getInstrInfo(); local 191 MIB = BuildMI(*MBB, MII, DL, TII->get(newOp));
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/freebsd-13-stable/contrib/llvm-project/llvm/lib/Target/WebAssembly/ |
H A D | WebAssemblyExplicitLocals.cpp | 207 const auto *TII = MF.getSubtarget<WebAssemblySubtarget>().getInstrInfo(); local 266 BuildMI(MBB, &MI, MI.getDebugLoc(), TII->get(Opc), NewReg) 276 BuildMI(MBB, &MI, MI.getDebugLoc(), TII->get(Opc), 298 BuildMI(MBB, InsertPt, MI.getDebugLoc(), TII->get(Opc)) 310 BuildMI(MBB, InsertPt, MI.getDebugLoc(), TII->get(Opc)) 368 BuildMI(MBB, InsertPt, MI.getDebugLoc(), TII->get(Opc), NewReg)
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H A D | WebAssemblyFastISel.cpp | 387 BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DbgLoc, TII.get(Opc), Reg) 463 TII.get(WebAssembly::CONST_I32), Imm) 468 TII.get(WebAssembly::AND_I32), Result) 493 TII.get(WebAssembly::CONST_I32), Imm) 498 TII.get(WebAssembly::SHL_I32), Left) 504 TII.get(WebAssembly::SHR_S_I32), Right) 522 TII.get(WebAssembly::I64_EXTEND_U_I32), Result) 544 TII.get(WebAssembly::I64_EXTEND_S_I32), Result) 583 TII.get(WebAssembly::EQZ_I32), NotReg) 590 BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DbgLoc, TII [all...] |
/freebsd-13-stable/contrib/llvm-project/llvm/include/llvm/CodeGen/GlobalISel/ |
H A D | InstructionSelector.h | 471 const int64_t *MatchTable, const TargetInstrInfo &TII, 503 const TargetInstrInfo &TII,
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/freebsd-13-stable/contrib/llvm-project/llvm/include/llvm/CodeGen/ |
H A D | LiveRangeEdit.h | 75 const TargetInstrInfo &TII; member in class:llvm::LiveRangeEdit 143 VRM(vrm), TII(*MF.getSubtarget().getInstrInfo()), TheDelegate(delegate),
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