Searched refs:TII (Results 126 - 150 of 403) sorted by relevance

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/freebsd-13-stable/contrib/llvm-project/llvm/lib/Target/X86/
H A DX86MacroFusion.cpp34 static bool shouldScheduleAdjacent(const TargetInstrInfo &TII, argument
H A DX86FixupBWInsts.cpp138 const X86InstrInfo *TII = nullptr; member in class:__anon4428::FixupBWInstPass
164 TII = MF.getSubtarget<X86Subtarget>().getInstrInfo();
170 LiveRegs.init(TII->getRegisterInfo());
190 auto *TRI = &TII->getRegisterInfo();
299 BuildMI(*MF, MI->getDebugLoc(), TII->get(New32BitOpcode), NewDestReg);
323 auto *TRI = &TII->getRegisterInfo();
334 BuildMI(*MF, MI->getDebugLoc(), TII->get(X86::MOV32rr), NewDestReg)
362 BuildMI(*MF, MI->getDebugLoc(), TII->get(New32BitOpcode), NewDestReg);
/freebsd-13-stable/contrib/llvm-project/llvm/include/llvm/CodeGen/
H A DTargetSchedule.h37 const TargetInstrInfo *TII = nullptr; member in class:llvm::TargetSchedModel
66 const TargetInstrInfo *getInstrInfo() const { return TII; }
186 /// present this method falls back to TII->getInstrLatency with an empty
/freebsd-13-stable/contrib/llvm-project/llvm/lib/CodeGen/
H A DMachineBasicBlock.cpp201 const TargetInstrInfo *TII = getParent()->getSubtarget().getInstrInfo();
205 TII->isBasicBlockPrologue(*I)))
216 const TargetInstrInfo *TII = getParent()->getSubtarget().getInstrInfo();
220 TII->isBasicBlockPrologue(*I)))
378 const TargetInstrInfo &TII = *getParent()->getSubtarget().getInstrInfo();
462 /*AddNewLine=*/false, &TII);
541 const TargetInstrInfo &TII = *getParent()->getSubtarget().getInstrInfo();
555 BuildMI(*this, I, DebugLoc(), TII.get(TargetOpcode::COPY), VirtReg)
575 const TargetInstrInfo *TII = getParent()->getSubtarget().getInstrInfo();
583 bool B = TII
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H A DMacroFusion.cpp94 dbgs() << DAG.TII->getName(FirstSU.getInstr()->getOpcode()) << " - "
95 << DAG.TII->getName(SecondSU.getInstr()->getOpcode()) << '\n';);
170 const TargetInstrInfo &TII = *DAG.TII; local
174 if (!shouldScheduleAdjacent(TII, ST, nullptr, AnchorMI))
190 !shouldScheduleAdjacent(TII, ST, DepMI, AnchorMI))
H A DIfConversion.cpp195 const TargetInstrInfo *TII; member in class:__anon3479::IfConverter
289 return Cycle > 0 && TII->isProfitableToIfCvt(BB, Cycle, Extra,
315 CommonBytes += TII->getInstSizeInBytes(I);
319 CommonBytes += TII->getInstSizeInBytes(I);
329 BranchBytes += TII->predictBranchSizeForIfCvt(I);
332 CommonBytes += TII->getInstSizeInBytes(I);
338 BranchBytes += TII->predictBranchSizeForIfCvt(I);
341 CommonBytes += TII->getInstSizeInBytes(I);
347 BranchBytes += TII->predictBranchSizeForIfCvt(I);
377 unsigned ExtraPredicateBytes = TII
1472 InsertUncondBranch(MachineBasicBlock &MBB, MachineBasicBlock &ToMBB, const TargetInstrInfo *TII) argument
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/freebsd-13-stable/contrib/llvm-project/llvm/lib/Target/ARM/
H A DARMBasicBlockInfo.h114 const ARMBaseInstrInfo *TII = nullptr; member in class:llvm::ARMBasicBlockUtils
119 TII =
/freebsd-13-stable/contrib/llvm-project/llvm/lib/Target/PowerPC/
H A DPPCFrameLowering.cpp320 static void HandleVRSaveUpdate(MachineInstr &MI, const TargetInstrInfo &TII) { argument
367 BuildMI(*MI.getParent(), MI, dl, TII.get(PPC::ORI), DstReg)
371 BuildMI(*MI.getParent(), MI, dl, TII.get(PPC::ORI), DstReg)
376 BuildMI(*MI.getParent(), MI, dl, TII.get(PPC::ORIS), DstReg)
380 BuildMI(*MI.getParent(), MI, dl, TII.get(PPC::ORIS), DstReg)
385 BuildMI(*MI.getParent(), MI, dl, TII.get(PPC::ORIS), DstReg)
389 BuildMI(*MI.getParent(), MI, dl, TII.get(PPC::ORIS), DstReg)
393 BuildMI(*MI.getParent(), MI, dl, TII.get(PPC::ORI), DstReg)
760 const PPCInstrInfo &TII = *Subtarget.getInstrInfo(); local
785 HandleVRSaveUpdate(*MBBI, TII);
1372 const PPCInstrInfo &TII = *Subtarget.getInstrInfo(); local
1543 const PPCInstrInfo &TII = *Subtarget.getInstrInfo(); local
1893 const PPCInstrInfo &TII = *Subtarget.getInstrInfo(); local
2359 const PPCInstrInfo &TII = *Subtarget.getInstrInfo(); local
2446 const PPCInstrInfo &TII = *MF->getSubtarget<PPCSubtarget>().getInstrInfo(); local
2472 const TargetInstrInfo &TII = *Subtarget.getInstrInfo(); local
2516 const PPCInstrInfo &TII = *Subtarget.getInstrInfo(); local
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H A DPPCFastISel.cpp92 const TargetInstrInfo &TII; member in class:__anon4264::final
103 TII(*Subtarget->getInstrInfo()), TLI(*Subtarget->getTargetLowering()),
160 TII.get(TargetOpcode::COPY), TmpReg).addReg(SrcReg, Flag, SubReg);
437 BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DbgLoc, TII.get(PPC::ADDI8),
542 BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DbgLoc, TII.get(Opc), ResultReg)
550 BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DbgLoc, TII.get(Opc), ResultReg)
577 auto MIB = BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DbgLoc, TII.get(Opc),
688 BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DbgLoc, TII.get(Opc))
700 BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DbgLoc, TII.get(Opc))
723 auto MIB = BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DbgLoc, TII
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/freebsd-13-stable/contrib/llvm-project/llvm/lib/Target/AArch64/
H A DAArch64AdvSIMDScalarPass.cpp67 const TargetInstrInfo *TII; member in class:__anon3835::AArch64AdvSIMDScalar
274 static MachineInstr *insertCopy(const TargetInstrInfo *TII, MachineInstr &MI, argument
277 TII->get(AArch64::COPY), Dst)
344 insertCopy(TII, MI, Src0, OrigSrc0, KillSrc0);
350 insertCopy(TII, MI, Src1, OrigSrc1, KillSrc1);
362 BuildMI(*MBB, MI, MI.getDebugLoc(), TII->get(NewOpc), Dst)
369 insertCopy(TII, MI, MI.getOperand(0).getReg(), Dst, true);
399 TII = mf.getSubtarget().getInstrInfo();
H A DAArch64BranchTargets.cpp109 const AArch64InstrInfo *TII = static_cast<const AArch64InstrInfo *>( local
133 TII->get(AArch64::HINT))
H A DAArch64SLSHardening.cpp45 const TargetInstrInfo *TII; member in class:__anon3871::AArch64SLSHardening
85 const TargetInstrInfo *TII = ST->getInstrInfo(); local
92 BuildMI(MBB, MBBI, DL, TII->get(BarrierOpc));
97 TII = MF.getSubtarget().getInstrInfo();
215 const TargetInstrInfo *TII = local
227 BuildMI(Entry, DebugLoc(), TII->get(AArch64::ORRXrs), AArch64::X16)
231 BuildMI(Entry, DebugLoc(), TII->get(AArch64::BR)).addReg(AArch64::X16);
333 MachineInstr *BL = BuildMI(MBB, MBBI, DL, TII->get(BLOpcode)).addSym(Sym);
H A DAArch64FrameLowering.cpp337 const AArch64InstrInfo *TII = local
341 bool IsDestroy = Opc == TII->getCallFrameDestroyOpcode();
366 TII);
373 {-(int64_t)CalleePopAmount, MVT::i8}, TII);
499 const TargetInstrInfo *TII = STI.getInstrInfo();
529 BuildMI(MBB, MBBI, DL, TII->get(TargetOpcode::CFI_INSTRUCTION))
678 const TargetInstrInfo &TII,
699 MIB = BuildMI(MF, DL, TII.get(AArch64::SEH_SaveFRegP_X))
713 MIB = BuildMI(MF, DL, TII.get(AArch64::SEH_SaveFPLR_X))
717 MIB = BuildMI(MF, DL, TII
677 InsertSEH(MachineBasicBlock::iterator MBBI, const TargetInstrInfo &TII, MachineInstr::MIFlag Flag) argument
819 convertCalleeSaveRestoreToSPPrePostIncDec( MachineBasicBlock &MBB, MachineBasicBlock::iterator MBBI, const DebugLoc &DL, const TargetInstrInfo *TII, int CSStackSizeInc, bool NeedsWinCFI, bool *HasWinCFI, bool InProlog = true) argument
1056 const TargetInstrInfo *TII = Subtarget.getInstrInfo(); local
1520 const TargetInstrInfo *TII = Subtarget.getInstrInfo(); local
1560 const TargetInstrInfo *TII = Subtarget.getInstrInfo(); local
2244 const TargetInstrInfo &TII = *MF.getSubtarget().getInstrInfo(); local
2386 const TargetInstrInfo &TII = *MF.getSubtarget().getInstrInfo(); local
2799 const TargetInstrInfo &TII = *MF.getSubtarget().getInstrInfo(); local
2887 const AArch64InstrInfo *TII = local
2929 const AArch64InstrInfo *TII = local
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H A DAArch64SpeculationHardening.cpp127 const TargetInstrInfo *TII; member in class:__anon3874::AArch64SpeculationHardening
190 if (TII->analyzeBranch(MBB, TBB, FBB, analyzeBranchCondCode, false))
198 // nullptr (see API docs for TII->analyzeBranch). For the rest of the
221 BuildMI(MBB, MBBI, DL, TII->get(AArch64::DSB)).addImm(0xf);
222 BuildMI(MBB, MBBI, DL, TII->get(AArch64::ISB)).addImm(0xf);
231 BuildMI(SplitEdgeBB, SplitEdgeBB.begin(), DL, TII->get(AArch64::CSELXr))
369 BuildMI(MBB, MBBI, DebugLoc(), TII->get(AArch64::SUBSXri))
375 BuildMI(MBB, MBBI, DebugLoc(), TII->get(AArch64::CSINVXr))
392 BuildMI(MBB, MBBI, DebugLoc(), TII->get(AArch64::ADDXri))
398 BuildMI(MBB, MBBI, DebugLoc(), TII
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H A DAArch64InstrInfo.cpp1094 const TargetInstrInfo *TII = MF->getSubtarget().getInstrInfo();
1102 Instr.getRegClassConstraint(OpIdx, TII, TRI);
1520 const TargetInstrInfo *TII = local
1530 BuildMI(MBB, FirstEpilogSEH, DL, TII->get(AArch64::ADRP))
1533 BuildMI(MBB, FirstEpilogSEH, DL, TII->get(AArch64::ADDXri))
3339 const TargetInstrInfo *TII,
3395 auto MBI = BuildMI(MBB, MBBI, DL, TII->get(Opc), TmpReg)
3411 BuildMI(MBB, MBBI, DL, TII->get(AArch64::SEH_SetFP)).setMIFlag(Flag);
3413 BuildMI(MBB, MBBI, DL, TII->get(AArch64::SEH_AddFP))
3422 BuildMI(MBB, MBBI, DL, TII
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H A DAArch64ConditionalCompares.cpp140 const TargetInstrInfo *TII; member in class:__anon3843::SSACCmpConv
195 TII = MF.getSubtarget().getInstrInfo();
502 if (TII->analyzeBranch(*Head, TBB, FBB, HeadCond)) {
531 if (TII->analyzeBranch(*CmpBB, TBB, FBB, CmpBBCond)) {
613 TII->removeBranch(*Head);
632 const MCInstrDesc &MCID = TII->get(Opc);
635 MRI->createVirtualRegister(TII->getRegClass(MCID, 0, TRI, *MF));
644 TII->getRegClass(MCID, 1, TRI, *MF));
689 const MCInstrDesc &MCID = TII->get(Opc);
691 TII
763 const TargetInstrInfo *TII; member in class:__anon3844::AArch64ConditionalCompares
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H A DAArch64RegisterInfo.cpp535 const AArch64InstrInfo *TII =
537 const MCInstrDesc &MCID = TII->get(AArch64::ADDXri);
539 MRI.constrainRegClass(BaseReg, TII->getRegClass(MCID, 0, this, MF));
560 const AArch64InstrInfo *TII =
562 bool Done = rewriteAArch64FrameIndex(MI, i, BaseReg, Off, TII);
572 const AArch64InstrInfo *TII) {
577 MI.setDesc(TII->get(AArch64::STGloop_wback));
580 MI.setDesc(TII->get(AArch64::STZGloop_wback));
597 const AArch64InstrInfo *TII =
647 TII);
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/freebsd-13-stable/contrib/llvm-project/llvm/lib/Target/WebAssembly/
H A DWebAssemblyPrepareForLiveIntervals.cpp81 const auto &TII = *MF.getSubtarget<WebAssemblySubtarget>().getInstrInfo(); local
109 TII.get(WebAssembly::IMPLICIT_DEF), Reg);
H A DWebAssemblyRegStackify.cpp101 const TargetInstrInfo *TII,
108 MI->setDesc(TII->get(WebAssembly::CONST_I32));
111 MI->setDesc(TII->get(WebAssembly::CONST_I64));
114 MI->setDesc(TII->get(WebAssembly::CONST_F32));
119 MI->setDesc(TII->get(WebAssembly::CONST_F64));
126 MI->setDesc(TII->get(WebAssembly::SPLAT_v4i32));
129 TII->get(WebAssembly::CONST_I32), TempReg)
264 const WebAssemblyInstrInfo *TII) {
265 return Def.isAsCheapAsAMove() && TII->isTriviallyReMaterializable(Def, &AA);
568 const WebAssemblyInstrInfo *TII, cons
99 convertImplicitDefToConstZero(MachineInstr *MI, MachineRegisterInfo &MRI, const TargetInstrInfo *TII, MachineFunction &MF, LiveIntervals &LIS) argument
263 shouldRematerialize(const MachineInstr &Def, AliasAnalysis &AA, const WebAssemblyInstrInfo *TII) argument
564 rematerializeCheapDef( unsigned Reg, MachineOperand &Op, MachineInstr &Def, MachineBasicBlock &MBB, MachineBasicBlock::instr_iterator Insert, LiveIntervals &LIS, WebAssemblyFunctionInfo &MFI, MachineRegisterInfo &MRI, const WebAssemblyInstrInfo *TII, const WebAssemblyRegisterInfo *TRI) argument
632 moveAndTeeForMultiUse( unsigned Reg, MachineOperand &Op, MachineInstr *Def, MachineBasicBlock &MBB, MachineInstr *Insert, LiveIntervals &LIS, WebAssemblyFunctionInfo &MFI, MachineRegisterInfo &MRI, const WebAssemblyInstrInfo *TII) argument
773 maybeCommute(MachineInstr *Insert, TreeWalkerState &TreeWalker, const WebAssemblyInstrInfo *TII) argument
812 const auto *TII = MF.getSubtarget<WebAssemblySubtarget>().getInstrInfo(); local
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/freebsd-13-stable/contrib/llvm-project/llvm/lib/Target/AMDGPU/
H A DSIRegisterInfo.cpp458 const SIInstrInfo *TII = ST.getInstrInfo(); local
461 BuildMI(*MBB, Ins, DL, TII->get(AMDGPU::V_MOV_B32_e32), BaseReg)
471 BuildMI(*MBB, Ins, DL, TII->get(AMDGPU::S_MOV_B32), OffsetReg)
473 BuildMI(*MBB, Ins, DL, TII->get(AMDGPU::V_MOV_B32_e32), FIReg)
476 TII->getAddNoCarry(*MBB, Ins, DL, BaseReg)
484 const SIInstrInfo *TII = ST.getInstrInfo(); local
499 MachineOperand *FIOp = TII->getNamedOperand(MI, AMDGPU::OpName::vaddr);
505 assert(TII->isMUBUF(MI));
506 assert(TII->getNamedOperand(MI, AMDGPU::OpName::soffset)->getReg() ==
510 MachineOperand *OffsetOp = TII
662 const SIInstrInfo *TII = ST.getInstrInfo(); local
689 const SIInstrInfo *TII = ST.getInstrInfo(); local
736 const SIInstrInfo *TII = ST.getInstrInfo(); local
884 const SIInstrInfo *TII = ST.getInstrInfo(); local
998 const SIInstrInfo *TII = ST.getInstrInfo(); local
1111 const SIInstrInfo *TII = ST.getInstrInfo(); local
1217 const SIInstrInfo *TII = ST.getInstrInfo(); local
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H A DSIWholeQuadMode.cpp151 const SIInstrInfo *TII; member in class:__anon3995::SIWholeQuadMode
333 if (TII->isWQM(Opcode)) {
374 } else if (TII->isDisableWQM(MI)) {
436 (MI.isTerminator() || (TII->usesVM_CNT(MI) && MI.mayStore()))) {
533 BuildMI(MBB, Before, DebugLoc(), TII->get(AMDGPU::COPY), SaveReg)
536 BuildMI(MBB, Before, DebugLoc(), TII->get(AMDGPU::COPY), AMDGPU::SCC)
603 MI = BuildMI(MBB, Before, DebugLoc(), TII->get(ST->isWave32() ?
609 MI = BuildMI(MBB, Before, DebugLoc(), TII->get(ST->isWave32() ?
626 MI = BuildMI(MBB, Before, DebugLoc(), TII->get(AMDGPU::COPY), Exec)
629 MI = BuildMI(MBB, Before, DebugLoc(), TII
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H A DSIMachineFunctionInfo.h52 AMDGPUPseudoSourceValue(unsigned Kind, const TargetInstrInfo &TII) argument
53 : PseudoSourceValue(Kind, TII) {}
73 explicit AMDGPUBufferPseudoSourceValue(const TargetInstrInfo &TII) argument
74 : AMDGPUPseudoSourceValue(PSVBuffer, TII) {}
84 explicit AMDGPUImagePseudoSourceValue(const TargetInstrInfo &TII) argument
85 : AMDGPUPseudoSourceValue(PSVImage, TII) {}
94 explicit AMDGPUGWSResourcePseudoSourceValue(const TargetInstrInfo &TII) argument
95 : AMDGPUPseudoSourceValue(GWSResource, TII) {}
887 const AMDGPUBufferPseudoSourceValue *getBufferPSV(const SIInstrInfo &TII, argument
892 std::make_unique<AMDGPUBufferPseudoSourceValue>(TII));
896 getImagePSV(const SIInstrInfo &TII, const Value *ImgRsrc) argument
905 getGWSPSV(const SIInstrInfo &TII) argument
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/freebsd-13-stable/contrib/llvm-project/llvm/lib/Target/Mips/
H A DMips16ISelLowering.cpp512 const TargetInstrInfo *TII = Subtarget.getInstrInfo(); local
543 BuildMI(BB, DL, TII->get(Opc))
560 BuildMI(*BB, BB->begin(), DL, TII->get(Mips::PHI), MI.getOperand(0).getReg())
575 const TargetInstrInfo *TII = Subtarget.getInstrInfo(); local
606 BuildMI(BB, DL, TII->get(Opc2))
609 BuildMI(BB, DL, TII->get(Opc1)).addMBB(sinkMBB);
624 BuildMI(*BB, BB->begin(), DL, TII->get(Mips::PHI), MI.getOperand(0).getReg())
641 const TargetInstrInfo *TII = Subtarget.getInstrInfo(); local
672 BuildMI(BB, DL, TII->get(Opc2))
675 BuildMI(BB, DL, TII
707 const TargetInstrInfo *TII = Subtarget.getInstrInfo(); local
724 const TargetInstrInfo *TII = Subtarget.getInstrInfo(); local
757 const TargetInstrInfo *TII = Subtarget.getInstrInfo(); local
776 const TargetInstrInfo *TII = Subtarget.getInstrInfo(); local
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/freebsd-13-stable/contrib/llvm-project/llvm/lib/Target/Hexagon/
H A DHexagonHardwareLoops.cpp105 const HexagonInstrInfo *TII; member in struct:__anon4129::HexagonHardwareLoops
389 TII = HST.getInstrInfo();
458 bool NotAnalyzed = TII->analyzeBranch(*ExitingBlock, TB, FB, Cond, false);
463 if (!TII->getPredReg(Cond, PredR, PredPos, PredRegFlags))
473 TII->analyzeCompare(*PredI, CmpReg1, CmpReg2, CmpMask, CmpImm);
619 bool NotAnalyzed = TII->analyzeBranch(*ExitingBlock, TB, FB, Cond, false);
631 bool NotAnalyzed = TII->analyzeBranch(*Latch, LTB, LFB, LCond, false);
647 bool Negated = TII->predOpcodeHasNot(Cond) ^ (TB != Header);
649 if (!TII->getPredReg(Cond, PredReg, PredPos, PredRegFlags))
657 TII
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/freebsd-13-stable/contrib/llvm-project/llvm/lib/CodeGen/SelectionDAG/
H A DScheduleDAGRRList.cpp311 const TargetInstrInfo *TII,
341 const MCInstrDesc Desc = TII->get(Opcode);
342 const TargetRegisterClass *RC = TII->getRegClass(Desc, Idx, TRI, MF);
442 const TargetInstrInfo *TII) {
452 if (IsChainDependent(Op.getNode(), Inner, NestLevel, TII))
458 if (N->getMachineOpcode() == TII->getCallFrameDestroyOpcode()) {
460 } else if (N->getMachineOpcode() == TII->getCallFrameSetupOpcode()) {
490 const TargetInstrInfo *TII) {
502 MyNestLevel, MyMaxNest, TII))
514 if (N->getMachineOpcode() == TII
309 GetCostForDef(const ScheduleDAGSDNodes::RegDefIter &RegDefPos, const TargetLowering *TLI, const TargetInstrInfo *TII, const TargetRegisterInfo *TRI, unsigned &RegClass, unsigned &Cost, const MachineFunction &MF) argument
440 IsChainDependent(SDNode *Outer, SDNode *Inner, unsigned NestLevel, const TargetInstrInfo *TII) argument
489 FindCallSeqStart(SDNode *N, unsigned &NestLevel, unsigned &MaxNest, const TargetInstrInfo *TII) argument
1276 getPhysicalRegisterVT(SDNode *N, unsigned Reg, const TargetInstrInfo *TII) argument
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