Lines Matching refs:TII
311 const TargetInstrInfo *TII,
341 const MCInstrDesc Desc = TII->get(Opcode);
342 const TargetRegisterClass *RC = TII->getRegClass(Desc, Idx, TRI, MF);
442 const TargetInstrInfo *TII) {
452 if (IsChainDependent(Op.getNode(), Inner, NestLevel, TII))
458 if (N->getMachineOpcode() == TII->getCallFrameDestroyOpcode()) {
460 } else if (N->getMachineOpcode() == TII->getCallFrameSetupOpcode()) {
490 const TargetInstrInfo *TII) {
502 MyNestLevel, MyMaxNest, TII))
514 if (N->getMachineOpcode() == TII->getCallFrameDestroyOpcode()) {
517 } else if (N->getMachineOpcode() == TII->getCallFrameSetupOpcode()) {
581 Node->getMachineOpcode() == TII->getCallFrameDestroyOpcode()) {
584 SDNode *N = FindCallSeqStart(Node, NestLevel, MaxNest, TII);
787 SUNode->getMachineOpcode() == TII->getCallFrameSetupOpcode()) {
858 SUNode->getMachineOpcode() == TII->getCallFrameSetupOpcode()) {
875 SUNode->getMachineOpcode() == TII->getCallFrameDestroyOpcode()) {
984 if (!TII->unfoldMemoryOperand(*DAG, N, NewNodes))
1034 const MCInstrDesc &MCID = TII->get(N->getMachineOpcode());
1143 !TII->canCopyGluedNodeDuringSchedule(N)) {
1163 if (VT == MVT::Glue && !TII->canCopyGluedNodeDuringSchedule(N)) {
1277 const TargetInstrInfo *TII) {
1283 const MCInstrDesc &MCID = TII->get(N->getMachineOpcode());
1395 if (Node->getMachineOpcode() == TII->getCallFrameDestroyOpcode()) {
1402 if (!IsChainDependent(Gen, Node, 0, TII) &&
1412 const MCInstrDesc &MCID = TII->get(Node->getMachineOpcode());
1556 MVT VT = getPhysicalRegisterVT(LRDef->getNode(), Reg, TII);
1736 const TargetInstrInfo *TII;
1760 SrcOrder(srcorder), MF(mf), TII(tii), TRI(tri), TLI(tli) {
2099 GetCostForDef(RegDefPos, TLI, TII, TRI, RCId, Cost, MF);
2114 unsigned NumDefs = TII->get(N->getMachineOpcode()).getNumDefs();
2160 unsigned NumDefs = TII->get(N->getMachineOpcode()).getNumDefs();
2211 GetCostForDef(RegDefPos, TLI, TII, TRI, RCId, Cost, MF);
2226 GetCostForDef(RegDefPos, TLI, TII, TRI, RCId, Cost, MF);
2289 unsigned NumDefs = TII->get(PN->getMachineOpcode()).getNumDefs();
2306 unsigned NumDefs = TII->get(N->getMachineOpcode()).getNumDefs();
2819 const MCInstrDesc &MCID = TII->get(Opc);
2839 const TargetInstrInfo *TII,
2842 = TII->get(SU->getNode()->getMachineOpcode()).getImplicitDefs();
2874 const TargetInstrInfo *TII,
2877 unsigned NumDefs = TII->get(N->getMachineOpcode()).getNumDefs();
2878 const MCPhysReg *ImpDefs = TII->get(N->getMachineOpcode()).getImplicitDefs();
2885 TII->get(SUNode->getMachineOpcode()).getImplicitDefs();
2973 (PredND->getMachineOpcode() == TII->getCallFrameSetupOpcode())) {
3016 if (canClobberPhysRegDefs(PredSuccSU, &SU, TII, TRI))
3064 const MCInstrDesc &MCID = TII->get(Opc);
3102 if (canClobberPhysRegDefs(SuccSU, &SU, TII, TRI))
3112 if (!canClobberReachingPhysRegUse(SuccSU, &SU, scheduleDAG, TII, TRI) &&
3135 const TargetInstrInfo *TII = STI.getInstrInfo();
3139 new BURegReductionPriorityQueue(*IS->MF, false, false, TII, TRI, nullptr);
3149 const TargetInstrInfo *TII = STI.getInstrInfo();
3153 new SrcRegReductionPriorityQueue(*IS->MF, false, true, TII, TRI, nullptr);
3163 const TargetInstrInfo *TII = STI.getInstrInfo();
3168 new HybridBURRPriorityQueue(*IS->MF, true, false, TII, TRI, TLI);
3179 const TargetInstrInfo *TII = STI.getInstrInfo();
3184 new ILPBURRPriorityQueue(*IS->MF, true, false, TII, TRI, TLI);