Lines Matching refs:TII
151 const SIInstrInfo *TII;
333 if (TII->isWQM(Opcode)) {
374 } else if (TII->isDisableWQM(MI)) {
436 (MI.isTerminator() || (TII->usesVM_CNT(MI) && MI.mayStore()))) {
533 BuildMI(MBB, Before, DebugLoc(), TII->get(AMDGPU::COPY), SaveReg)
536 BuildMI(MBB, Before, DebugLoc(), TII->get(AMDGPU::COPY), AMDGPU::SCC)
603 MI = BuildMI(MBB, Before, DebugLoc(), TII->get(ST->isWave32() ?
609 MI = BuildMI(MBB, Before, DebugLoc(), TII->get(ST->isWave32() ?
626 MI = BuildMI(MBB, Before, DebugLoc(), TII->get(AMDGPU::COPY), Exec)
629 MI = BuildMI(MBB, Before, DebugLoc(), TII->get(ST->isWave32() ?
644 MI = BuildMI(MBB, Before, DebugLoc(), TII->get(AMDGPU::ENTER_WWM), SaveOrig)
655 MI = BuildMI(MBB, Before, DebugLoc(), TII->get(AMDGPU::EXIT_WWM),
713 if (MI.isTerminator() || TII->mayReadEXEC(*MRI, MI)) {
823 BuildMI(*MI->getParent(), MI, DL, TII->get(AMDGPU::COPY), Dest)
842 const unsigned MovOp = TII->getMovOpcode(regClass);
843 MI->setDesc(TII->get(MovOp));
848 MI->setDesc(TII->get(AMDGPU::COPY));
865 MI->setDesc(TII->get(AMDGPU::COPY));
879 TII = ST->getInstrInfo();
880 TRI = &TII->getRegisterInfo();
899 TII->get(AMDGPU::COPY), LiveMaskReg)
909 TII->get(ST->isWave32() ? AMDGPU::S_WQM_B32