Searched refs:RegInfo (Results 26 - 50 of 90) sorted by relevance

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/freebsd-13-stable/contrib/llvm-project/llvm/lib/Target/AArch64/
H A DAArch64FrameLowering.cpp296 const TargetRegisterInfo *RegInfo = MF.getSubtarget().getRegisterInfo(); local
307 RegInfo->needsStackRealignment(MF))
580 const AArch64RegisterInfo *RegInfo = Subtarget.getRegisterInfo();
583 if (!RegInfo->needsStackRealignment(*MF))
612 const AArch64RegisterInfo *RegInfo = Subtarget.getRegisterInfo();
625 if (RegInfo->needsStackRealignment(MF))
688 const AArch64RegisterInfo *RegInfo = Subtarget.getRegisterInfo(); local
697 unsigned Reg0 = RegInfo->getSEHRegNum(MBBI->getOperand(1).getReg());
698 unsigned Reg1 = RegInfo->getSEHRegNum(MBBI->getOperand(2).getReg());
718 .addImm(RegInfo
1055 const AArch64RegisterInfo *RegInfo = Subtarget.getRegisterInfo(); local
1857 const auto *RegInfo = static_cast<const AArch64RegisterInfo *>( local
1880 const auto *RegInfo = static_cast<const AArch64RegisterInfo *>( local
2510 const AArch64RegisterInfo *RegInfo = static_cast<const AArch64RegisterInfo *>( local
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/freebsd-13-stable/contrib/llvm-project/llvm/lib/Target/Mips/
H A DMipsSEISelLowering.cpp3036 MachineRegisterInfo &RegInfo = BB->getParent()->getRegInfo(); local
3067 Register VR2 = RegInfo.createVirtualRegister(RC);
3073 Register VR1 = RegInfo.createVirtualRegister(RC);
3105 MachineRegisterInfo &RegInfo = BB->getParent()->getRegInfo(); local
3136 Register RD1 = RegInfo.createVirtualRegister(RC);
3142 Register RD2 = RegInfo.createVirtualRegister(RC);
3172 MachineRegisterInfo &RegInfo = BB->getParent()->getRegInfo(); local
3183 Wt = RegInfo.createVirtualRegister(&Mips::MSA128WEvensRegClass);
3190 Register Wt = RegInfo.createVirtualRegister(
3218 MachineRegisterInfo &RegInfo local
3247 MachineRegisterInfo &RegInfo = BB->getParent()->getRegInfo(); local
3283 MachineRegisterInfo &RegInfo = BB->getParent()->getRegInfo(); local
3329 MachineRegisterInfo &RegInfo = BB->getParent()->getRegInfo(); local
3443 MachineRegisterInfo &RegInfo = BB->getParent()->getRegInfo(); local
3478 MachineRegisterInfo &RegInfo = BB->getParent()->getRegInfo(); local
3512 MachineRegisterInfo &RegInfo = BB->getParent()->getRegInfo(); local
3567 MachineRegisterInfo &RegInfo = BB->getParent()->getRegInfo(); local
3666 MachineRegisterInfo &RegInfo = BB->getParent()->getRegInfo(); local
3771 MachineRegisterInfo &RegInfo = BB->getParent()->getRegInfo(); local
3820 MachineRegisterInfo &RegInfo = BB->getParent()->getRegInfo(); local
3849 MachineRegisterInfo &RegInfo = BB->getParent()->getRegInfo(); local
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H A DMipsISelLowering.cpp1473 MachineRegisterInfo &RegInfo = MF->getRegInfo(); local
1561 Register Scratch = RegInfo.createVirtualRegister(RegInfo.getRegClass(OldVal));
1600 Register PtrCopy = RegInfo.createVirtualRegister(RegInfo.getRegClass(Ptr));
1601 Register IncrCopy = RegInfo.createVirtualRegister(RegInfo.getRegClass(Incr));
1615 RegInfo.createVirtualRegister(RegInfo.getRegClass(OldVal));
1642 MachineRegisterInfo &RegInfo local
1661 MachineRegisterInfo &RegInfo = MF->getRegInfo(); local
1909 MachineRegisterInfo &RegInfo = MF->getRegInfo(); local
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/freebsd-13-stable/contrib/llvm-project/llvm/include/llvm/DebugInfo/DWARF/
H A DDWARFDebugLoc.h106 void dump(raw_ostream &OS, const MCRegisterInfo *RegInfo,
H A DDWARFContext.h89 std::unique_ptr<MCRegisterInfo> RegInfo; member in class:llvm::DWARFContext
371 const MCRegisterInfo *getRegisterInfo() const { return RegInfo.get(); }
/freebsd-13-stable/contrib/llvm-project/llvm/include/llvm/CodeGen/
H A DRDFRegisters.h135 struct RegInfo { struct in struct:llvm::rdf::PhysicalRegisterInfo
148 std::vector<RegInfo> RegInfos;
H A DTargetInstrInfo.h1852 using RegInfo = DenseMapInfo<unsigned>;
1855 return TargetInstrInfo::RegSubRegPair(RegInfo::getEmptyKey(),
1856 RegInfo::getEmptyKey());
1860 return TargetInstrInfo::RegSubRegPair(RegInfo::getTombstoneKey(),
1861 RegInfo::getTombstoneKey());
1873 return RegInfo::isEqual(LHS.Reg, RHS.Reg) &&
1874 RegInfo::isEqual(LHS.SubReg, RHS.SubReg);
H A DFunctionLoweringInfo.h58 MachineRegisterInfo *RegInfo; member in class:llvm::FunctionLoweringInfo
H A DMachineInstr.h1482 const TargetRegisterInfo &RegInfo);
1489 const TargetRegisterInfo *RegInfo,
1492 /// Clear all kill flags affecting Reg. If RegInfo is provided, this includes
1494 void clearRegisterKills(Register Reg, const TargetRegisterInfo *RegInfo);
1500 bool addRegisterDead(Register Reg, const TargetRegisterInfo *RegInfo,
1514 const TargetRegisterInfo *RegInfo = nullptr);
/freebsd-13-stable/contrib/llvm-project/llvm/lib/CodeGen/
H A DMachineFrameInfo.cpp139 const TargetRegisterInfo *RegInfo = MF.getSubtarget().getRegisterInfo(); local
176 (RegInfo->needsStackRealignment(MF) && getObjectIndexEnd() != 0))
H A DGCRootLowering.cpp316 const TargetRegisterInfo *RegInfo = MF.getSubtarget().getRegisterInfo(); local
318 RegInfo->needsStackRealignment(MF);
H A DPrologEpilogInserter.cpp392 const TargetRegisterInfo *RegInfo = F.getSubtarget().getRegisterInfo(); local
404 if (!TFI->assignCalleeSavedSpillSlots(F, RegInfo, CSI)) {
423 const TargetRegisterClass *RC = RegInfo->getMinimalPhysRegClass(Reg);
426 if (RegInfo->hasReservedSpillSlot(F, Reg, FrameIdx)) {
438 unsigned Size = RegInfo->getSpillSize(*RC);
441 Align Alignment(RegInfo->getSpillAlignment(*RC));
883 const TargetRegisterInfo *RegInfo = MF.getSubtarget().getRegisterInfo(); local
886 RegInfo->useFPForScavengingIndex(MF) &&
887 !RegInfo->needsStackRealignment(MF));
1072 (RegInfo
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H A DMachineInstr.cpp1177 const TargetRegisterInfo &RegInfo) {
1180 ToReg = RegInfo.getSubReg(ToReg, SubIdx);
1184 MO.substPhysReg(ToReg, RegInfo);
1190 MO.substVirtReg(ToReg, SubIdx, RegInfo);
1821 const TargetRegisterInfo *RegInfo,
1825 MCRegAliasIterator(IncomingReg, RegInfo, false).isValid();
1856 if (RegInfo->isSuperRegister(IncomingReg, Reg))
1858 if (RegInfo->isSubRegister(IncomingReg, Reg))
1887 const TargetRegisterInfo *RegInfo) {
1889 RegInfo
1175 substituteRegister(Register FromReg, Register ToReg, unsigned SubIdx, const TargetRegisterInfo &RegInfo) argument
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H A DMachineFunction.cpp160 RegInfo = new (Allocator) MachineRegisterInfo(this);
162 RegInfo = nullptr;
229 if (RegInfo) {
230 RegInfo->~MachineRegisterInfo();
231 Allocator.Deallocate(RegInfo);
571 if (RegInfo && !RegInfo->livein_empty()) {
574 I = RegInfo->livein_begin(), E = RegInfo->livein_end(); I != E; ++I) {
/freebsd-13-stable/contrib/llvm-project/llvm/lib/Target/BPF/
H A DBPFISelLowering.cpp253 MachineRegisterInfo &RegInfo = MF.getRegInfo(); local
273 Register VReg = RegInfo.createVirtualRegister(
275 RegInfo.addLiveIn(VA.getLocReg(), VReg);
606 MachineRegisterInfo &RegInfo = F->getRegInfo(); local
609 Register PromotedReg0 = RegInfo.createVirtualRegister(RC);
613 Register PromotedReg0 = RegInfo.createVirtualRegister(RC);
614 Register PromotedReg1 = RegInfo.createVirtualRegister(RC);
615 Register PromotedReg2 = RegInfo.createVirtualRegister(RC);
/freebsd-13-stable/contrib/llvm-project/llvm/lib/Target/Hexagon/
H A DHexagonSubtarget.h99 HexagonRegisterInfo RegInfo; member in class:llvm::HexagonSubtarget
121 return &RegInfo;
/freebsd-13-stable/contrib/llvm-project/llvm/lib/Target/NVPTX/
H A DNVPTXPrologEpilogPass.cpp131 const TargetRegisterInfo *RegInfo = Fn.getSubtarget().getRegisterInfo(); local
231 (RegInfo->needsStackRealignment(Fn) && MFI.getObjectIndexEnd() != 0))
/freebsd-13-stable/contrib/llvm-project/llvm/lib/Target/PowerPC/
H A DPPCFrameLowering.cpp467 const PPCRegisterInfo *RegInfo = Subtarget.getRegisterInfo(); local
469 unsigned LR = RegInfo->getRARegister();
475 !RegInfo->hasBasePointer(MF); // No special alignment.
544 const PPCRegisterInfo *RegInfo = Subtarget.getRegisterInfo(); local
545 bool HasBP = RegInfo->hasBasePointer(MF);
546 unsigned BPReg = HasBP ? (unsigned) RegInfo->getBaseRegister(MF) : FPReg;
640 const PPCRegisterInfo *RegInfo = Subtarget.getRegisterInfo(); local
641 const MCPhysReg *CSRegs = RegInfo->getCalleeSavedRegs(MBB->getParent());
686 const PPCRegisterInfo *RegInfo = Subtarget.getRegisterInfo(); local
688 bool HasBP = RegInfo
713 const PPCRegisterInfo *RegInfo = Subtarget.getRegisterInfo(); local
761 const PPCRegisterInfo *RegInfo = Subtarget.getRegisterInfo(); local
1395 const PPCRegisterInfo *RegInfo = Subtarget.getRegisterInfo(); local
1544 const PPCRegisterInfo *RegInfo = Subtarget.getRegisterInfo(); local
1949 const PPCRegisterInfo *RegInfo = Subtarget.getRegisterInfo(); local
2157 const PPCRegisterInfo *RegInfo = Subtarget.getRegisterInfo(); local
2317 const PPCRegisterInfo *RegInfo = Subtarget.getRegisterInfo(); local
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/freebsd-13-stable/contrib/llvm-project/llvm/lib/Target/ARC/
H A DARCFrameLowering.cpp435 const TargetRegisterInfo *RegInfo = MF.getSubtarget().getRegisterInfo(); local
442 int RegScavFI = MFI.CreateStackObject(RegInfo->getSpillSize(*RC),
443 RegInfo->getSpillAlign(*RC), false);
492 const TargetRegisterInfo *RegInfo = MF.getSubtarget().getRegisterInfo(); local
496 RegInfo->needsStackRealignment(MF);
H A DARCISelLowering.cpp452 MachineRegisterInfo &RegInfo = MF.getRegInfo(); local
493 unsigned VReg = RegInfo.createVirtualRegister(&ARC::GPR32RegClass);
494 RegInfo.addLiveIn(VA.getLocReg(), VReg);
538 unsigned VReg = RegInfo.createVirtualRegister(&ARC::GPR32RegClass);
539 RegInfo.addLiveIn(ArgRegs[i], VReg);
/freebsd-13-stable/contrib/llvm-project/llvm/lib/DebugInfo/DWARF/
H A DDWARFExpression.cpp256 const MCRegisterInfo *RegInfo,
272 if (prettyPrintRegisterOp(U, OS, Opcode, Operands, RegInfo, isEH))
314 void DWARFExpression::print(raw_ostream &OS, const MCRegisterInfo *RegInfo, argument
318 if (!Op.print(OS, this, RegInfo, U, IsEH)) {
254 print(raw_ostream &OS, const DWARFExpression *Expr, const MCRegisterInfo *RegInfo, DWARFUnit *U, bool isEH) argument
/freebsd-13-stable/contrib/llvm-project/llvm/lib/Target/ARM/
H A DMVEVPTOptimisationsPass.cpp139 MachineRegisterInfo &RegInfo = Instr.getMF()->getRegInfo();
140 const TargetRegisterClass *RegClass = RegInfo.getRegClassOrNull(DstReg);
/freebsd-13-stable/contrib/llvm-project/llvm/lib/Target/WebAssembly/
H A DWebAssemblyFrameLowering.cpp47 const auto *RegInfo = local
49 return RegInfo->needsStackRealignment(MF);
/freebsd-13-stable/contrib/llvm-project/llvm/lib/CodeGen/MIRParser/
H A DMIParser.cpp127 auto RegInfo = Names2Regs.find(RegName); local
128 if (RegInfo == Names2Regs.end())
130 Reg = RegInfo->getValue();
447 bool parseRegisterClassOrBank(VRegInfo &RegInfo);
1311 bool MIParser::parseRegisterClassOrBank(VRegInfo &RegInfo) { argument
1322 switch (RegInfo.Kind) {
1325 RegInfo.Kind = VRegInfo::NORMAL;
1326 if (RegInfo.Explicit && RegInfo.D.RC != RC) {
1329 Twine(TRI.getRegClassName(RegInfo
1487 VRegInfo *RegInfo; local
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H A DMIRParser.cpp519 MachineRegisterInfo &RegInfo = MF.getRegInfo(); local
520 assert(RegInfo.tracksLiveness());
522 RegInfo.invalidateLiveness();
578 RegInfo.addLiveIn(Reg, VReg);
591 RegInfo.setCalleeSavedRegs(CalleeSavedRegisters);

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