Searched refs:MCInst (Results 151 - 175 of 296) sorted by relevance

1234567891011>>

/freebsd-13-stable/contrib/llvm-project/llvm/lib/Target/Sparc/
H A DSparc.h25 class MCInst;
32 MCInst &OutMI,
/freebsd-13-stable/contrib/llvm-project/llvm/lib/Target/VE/
H A DVEAsmPrinter.cpp29 #include "llvm/MC/MCInst.h"
82 MCInst SICInst;
90 MCInst BSICInst;
102 MCInst LEAInst;
114 MCInst LEASLInst;
126 MCInst LEAInst;
139 MCInst LEASLInst;
151 MCInst Inst;
346 MCInst TmpInst;
/freebsd-13-stable/contrib/llvm-project/llvm/lib/Target/X86/MCTargetDesc/
H A DX86MCTargetDesc.h24 class MCInst;
64 bool hasLockPrefix(const MCInst &MI);
H A DX86ATTInstPrinter.cpp9 // This file includes code for rendering MCInst instances as AT&T-style
18 #include "llvm/MC/MCInst.h"
41 void X86ATTInstPrinter::printInst(const MCInst *MI, uint64_t Address,
78 bool X86ATTInstPrinter::printVecCompareInstr(const MCInst *MI,
352 void X86ATTInstPrinter::printOperand(const MCInst *MI, unsigned OpNo,
385 void X86ATTInstPrinter::printMemReference(const MCInst *MI, unsigned Op,
425 void X86ATTInstPrinter::printSrcIdx(const MCInst *MI, unsigned Op,
439 void X86ATTInstPrinter::printDstIdx(const MCInst *MI, unsigned Op,
450 void X86ATTInstPrinter::printMemOffset(const MCInst *MI, unsigned Op,
469 void X86ATTInstPrinter::printU8Imm(const MCInst *M
[all...]
H A DX86IntelInstPrinter.cpp9 // This file includes code for rendering MCInst instances as Intel-style
18 #include "llvm/MC/MCInst.h"
39 void X86IntelInstPrinter::printInst(const MCInst *MI, uint64_t Address,
59 bool X86IntelInstPrinter::printVecCompareInstr(const MCInst *MI, raw_ostream &OS) {
329 void X86IntelInstPrinter::printOperand(const MCInst *MI, unsigned OpNo,
343 void X86IntelInstPrinter::printMemReference(const MCInst *MI, unsigned Op,
391 void X86IntelInstPrinter::printSrcIdx(const MCInst *MI, unsigned Op,
400 void X86IntelInstPrinter::printDstIdx(const MCInst *MI, unsigned Op,
408 void X86IntelInstPrinter::printMemOffset(const MCInst *MI, unsigned Op,
427 void X86IntelInstPrinter::printU8Imm(const MCInst *M
[all...]
H A DX86MCCodeEmitter.cpp21 #include "llvm/MC/MCInst.h"
50 void emitPrefix(const MCInst &MI, raw_ostream &OS,
53 void encodeInstruction(const MCInst &MI, raw_ostream &OS,
60 unsigned getX86RegEncoding(const MCInst &MI, unsigned OpNum) const;
66 bool isREXExtendedReg(const MCInst &MI, unsigned OpNum) const;
78 void emitMemModRMByte(const MCInst &MI, unsigned Op, unsigned RegOpcodeField,
84 bool emitPrefixImpl(unsigned &CurOp, const MCInst &MI,
87 void emitVEXOpcodePrefix(int MemOperand, const MCInst &MI,
90 void emitSegmentOverridePrefix(unsigned SegOperand, const MCInst &MI,
93 bool emitOpcodePrefix(int MemOperand, const MCInst
[all...]
/freebsd-13-stable/contrib/llvm-project/llvm/lib/Target/ARM/
H A DThumb2InstrInfo.h29 void getNoop(MCInst &NopInst) const override;
/freebsd-13-stable/contrib/llvm-project/llvm/lib/Target/AVR/MCTargetDesc/
H A DAVRAsmBackend.h50 bool mayNeedRelaxation(const MCInst &Inst,
/freebsd-13-stable/contrib/llvm-project/llvm/lib/Target/BPF/
H A DBPFMCInstLower.cpp1 //=-- BPFMCInstLower.cpp - Convert BPF MachineInstr to an MCInst ------------=//
10 // MCInst records.
21 #include "llvm/MC/MCInst.h"
47 void BPFMCInstLower::Lower(const MachineInstr *MI, MCInst &OutMI) const {
/freebsd-13-stable/contrib/llvm-project/llvm/lib/Target/Hexagon/
H A DHexagonAsmPrinter.cpp39 #include "llvm/MC/MCInst.h"
59 MCInst &MCB, HexagonAsmPrinter &AP);
246 static MCInst ScaleVectorOffset(MCInst &Inst, unsigned OpNo,
248 MCInst T;
265 void HexagonAsmPrinter::HexagonProcessInstruction(MCInst &Inst,
267 MCInst &MappedInst = static_cast <MCInst &>(Inst);
334 MCInst TmpInst;
350 MCInst TmpIns
[all...]
H A DHexagonMCInstLower.cpp1 //===- HexagonMCInstLower.cpp - Convert Hexagon MachineInstr to an MCInst -===//
10 // MCInst records.
27 #include "llvm/MC/MCInst.h"
37 MCInst &MCB, HexagonAsmPrinter &AP);
96 // Create an MCInst from a MachineInstr
98 MCInst &MCB, HexagonAsmPrinter &AP) {
107 MCInst *MCI = new (AP.OutContext) MCInst;
/freebsd-13-stable/contrib/llvm-project/llvm/lib/Target/Mips/MCTargetDesc/
H A DMipsAsmBackend.h60 bool mayNeedRelaxation(const MCInst &Inst,
H A DMipsELFStreamer.h44 void emitInstruction(const MCInst &Inst, const MCSubtargetInfo &STI) override;
/freebsd-13-stable/contrib/llvm-project/llvm/include/llvm/MC/
H A DMCObjectStreamer.h53 virtual void emitInstToData(const MCInst &Inst, const MCSubtargetInfo&) = 0;
57 void emitInstructionImpl(const MCInst &Inst, const MCSubtargetInfo &STI);
127 void emitInstruction(const MCInst &Inst, const MCSubtargetInfo &STI) override;
131 virtual void emitInstToFragment(const MCInst &Inst, const MCSubtargetInfo &);
H A DMCSubtargetInfo.h29 class MCInst;
212 /// Resolve a variant scheduling class for the given MCInst and CPU.
214 resolveVariantSchedClass(unsigned SchedClass, const MCInst *MI,
/freebsd-13-stable/contrib/llvm-project/llvm/lib/Target/AMDGPU/AsmParser/
H A DAMDGPUAsmParser.cpp1 //===- AMDGPUAsmParser.cpp - Parse SI asm to MCInst instructions ----------===//
32 #include "llvm/MC/MCInst.h"
741 void addImmOperands(MCInst &Inst, unsigned N, bool ApplyModifiers = true) const;
743 void addLiteralImmOperand(MCInst &Inst, int64_t Val, bool ApplyModifiers) const;
746 void addKImmFPOperands(MCInst &Inst, unsigned N) const;
748 void addKImmFP16Operands(MCInst &Inst, unsigned N) const {
752 void addKImmFP32Operands(MCInst &Inst, unsigned N) const {
756 void addRegOperands(MCInst &Inst, unsigned N) const;
758 void addBoolRegOperands(MCInst &Inst, unsigned N) const {
762 void addRegOrImmOperands(MCInst
[all...]
/freebsd-13-stable/contrib/llvm-project/llvm/lib/Target/WebAssembly/MCTargetDesc/
H A DWebAssemblyInstPrinter.cpp10 /// Print MCInst instructions to wasm format.
23 #include "llvm/MC/MCInst.h"
47 void WebAssemblyInstPrinter::printInst(const MCInst *MI, uint64_t Address,
220 void WebAssemblyInstPrinter::printOperand(const MCInst *MI, unsigned OpNo,
265 void WebAssemblyInstPrinter::printBrList(const MCInst *MI, unsigned OpNo,
276 void WebAssemblyInstPrinter::printWebAssemblyP2AlignOperand(const MCInst *MI,
285 void WebAssemblyInstPrinter::printWebAssemblySignatureOperand(const MCInst *MI,
/freebsd-13-stable/contrib/llvm-project/llvm/lib/Target/ARM/AsmParser/
H A DARMAsmParser.cpp1 //===- ARMAsmParser.cpp - Parse ARM assembly to MCInst instructions -------===//
32 #include "llvm/MC/MCInst.h"
294 SmallVector<MCInst, 4> PendingConditionalInsts;
303 MCInst ITInst;
311 for (const MCInst &Inst : PendingConditionalInsts) {
448 bool validatetLDMRegList(const MCInst &Inst, const OperandVector &Operands,
450 bool validatetSTMRegList(const MCInst &Inst, const OperandVector &Operands,
643 void cvtThumbMultiply(MCInst &Inst, const OperandVector &);
644 void cvtThumbBranches(MCInst &Inst, const OperandVector &);
645 void cvtMVEVMOVQtoDReg(MCInst
[all...]
/freebsd-13-stable/contrib/llvm-project/llvm/lib/Target/Hexagon/MCTargetDesc/
H A DHexagonShuffler.cpp23 #include "llvm/MC/MCInst.h"
111 MCInst const *id)
180 void HexagonShuffler::append(MCInst const &ID, MCInst const *Extender,
197 MCInst const &Inst = ISJ.getDesc();
229 MCInst const &Inst = ISJ.getDesc();
364 MCInst const &ID = ISJ->getDesc();
446 MCInst const &ID = ISJ->getDesc();
538 MCInst const &Inst0 = *ID.getOperand(0).getInst();
539 MCInst cons
[all...]
/freebsd-13-stable/contrib/llvm-project/llvm/lib/Target/Lanai/AsmParser/
H A DLanaiAsmParser.cpp1 //===-- LanaiAsmParser.cpp - Parse Lanai assembly to MCInst instructions --===//
19 #include "llvm/MC/MCInst.h"
391 void addExpr(MCInst &Inst, const MCExpr *Expr) const {
402 void addRegOperands(MCInst &Inst, unsigned N) const {
407 void addImmOperands(MCInst &Inst, unsigned N) const {
412 void addBrTargetOperands(MCInst &Inst, unsigned N) const {
417 void addCallTargetOperands(MCInst &Inst, unsigned N) const {
422 void addCondCodeOperands(MCInst &Inst, unsigned N) const {
427 void addMemImmOperands(MCInst &Inst, unsigned N) const {
433 void addMemRegImmOperands(MCInst
[all...]
/freebsd-13-stable/contrib/llvm-project/llvm/lib/Target/AMDGPU/
H A DAMDGPUMCInstLower.cpp1 //===- AMDGPUMCInstLower.cpp - Lower AMDGPU MachineInstr to an MCInst -----===//
10 /// Code to lower AMDGPU MachineInstrs to their corresponding MCInst.
30 #include "llvm/MC/MCInst.h"
55 /// Lower a MachineInstr to an MCInst
56 void lower(const MachineInstr *MI, MCInst &OutMI) const;
65 /// Lower a MachineInstr to an MCInst
66 void lower(const MachineInstr *MI, MCInst &OutMI) const;
176 void AMDGPUMCInstLower::lower(const MachineInstr *MI, MCInst &OutMI) const {
315 MCInst TmpInst;
375 void R600MCInstLower::lower(const MachineInstr *MI, MCInst
[all...]
/freebsd-13-stable/contrib/llvm-project/llvm/lib/Target/Mips/AsmParser/
H A DMipsAsmParser.cpp1 //===-- MipsAsmParser.cpp - Parse Mips assembly to MCInst instructions ----===//
26 #include "llvm/MC/MCInst.h"
165 void ConvertXWPOperands(MCInst &Inst, const OperandVector &Operands);
171 checkEarlyTargetMatchPredicate(MCInst &Inst,
173 unsigned checkTargetMatchPredicate(MCInst &Inst) override;
222 MacroExpanderResultTy tryExpandInstruction(MCInst &Inst, SMLoc IDLoc,
226 bool expandJalWithRegs(MCInst &Inst, SMLoc IDLoc, MCStreamer &Out,
239 bool expandLoadImm(MCInst &Inst, bool Is32BitImm, SMLoc IDLoc,
242 bool expandLoadSingleImmToGPR(MCInst &Inst, SMLoc IDLoc, MCStreamer &Out,
244 bool expandLoadSingleImmToFPR(MCInst
[all...]
/freebsd-13-stable/contrib/llvm-project/llvm/lib/Target/AArch64/
H A DAArch64AsmPrinter.cpp47 #include "llvm/MC/MCInst.h"
974 MCInst MOVI;
980 MCInst FMov;
1036 MCInst Inst;
1058 MCInst MovZ;
1065 MCInst MovK;
1079 MCInst TmpInst;
1117 MCInst TmpInst;
1126 MCInst TmpInst;
1134 MCInst TmpInstDS
[all...]
/freebsd-13-stable/contrib/llvm-project/llvm/lib/MC/
H A DMCSchedule.cpp14 #include "llvm/MC/MCInst.h"
69 const MCInst &Inst) const {
112 const MCInst &Inst) const {
/freebsd-13-stable/contrib/llvm-project/llvm/lib/Target/VE/MCTargetDesc/
H A DVEAsmBackend.cpp143 bool mayNeedRelaxation(const MCInst &Inst,
161 void relaxInstruction(MCInst &Inst,

Completed in 238 milliseconds

1234567891011>>