1//===-- X86MCTargetDesc.h - X86 Target Descriptions -------------*- C++ -*-===// 2// 3// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions. 4// See https://llvm.org/LICENSE.txt for license information. 5// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception 6// 7//===----------------------------------------------------------------------===// 8// 9// This file provides X86 specific target descriptions. 10// 11//===----------------------------------------------------------------------===// 12 13#ifndef LLVM_LIB_TARGET_X86_MCTARGETDESC_X86MCTARGETDESC_H 14#define LLVM_LIB_TARGET_X86_MCTARGETDESC_X86MCTARGETDESC_H 15 16#include <memory> 17#include <string> 18 19namespace llvm { 20class formatted_raw_ostream; 21class MCAsmBackend; 22class MCCodeEmitter; 23class MCContext; 24class MCInst; 25class MCInstPrinter; 26class MCInstrInfo; 27class MCObjectTargetWriter; 28class MCObjectWriter; 29class MCRegister; 30class MCRegisterInfo; 31class MCStreamer; 32class MCSubtargetInfo; 33class MCTargetOptions; 34class MCTargetStreamer; 35class Target; 36class Triple; 37class StringRef; 38 39/// Flavour of dwarf regnumbers 40/// 41namespace DWARFFlavour { 42 enum { 43 X86_64 = 0, X86_32_DarwinEH = 1, X86_32_Generic = 2 44 }; 45} 46 47/// Native X86 register numbers 48/// 49namespace N86 { 50 enum { 51 EAX = 0, ECX = 1, EDX = 2, EBX = 3, ESP = 4, EBP = 5, ESI = 6, EDI = 7 52 }; 53} 54 55namespace X86_MC { 56std::string ParseX86Triple(const Triple &TT); 57 58unsigned getDwarfRegFlavour(const Triple &TT, bool isEH); 59 60void initLLVMToSEHAndCVRegMapping(MCRegisterInfo *MRI); 61 62 63/// Returns true if this instruction has a LOCK prefix. 64bool hasLockPrefix(const MCInst &MI); 65 66/// Create a X86 MCSubtargetInfo instance. This is exposed so Asm parser, etc. 67/// do not need to go through TargetRegistry. 68MCSubtargetInfo *createX86MCSubtargetInfo(const Triple &TT, StringRef CPU, 69 StringRef FS); 70} 71 72MCCodeEmitter *createX86MCCodeEmitter(const MCInstrInfo &MCII, 73 const MCRegisterInfo &MRI, 74 MCContext &Ctx); 75 76MCAsmBackend *createX86_32AsmBackend(const Target &T, 77 const MCSubtargetInfo &STI, 78 const MCRegisterInfo &MRI, 79 const MCTargetOptions &Options); 80MCAsmBackend *createX86_64AsmBackend(const Target &T, 81 const MCSubtargetInfo &STI, 82 const MCRegisterInfo &MRI, 83 const MCTargetOptions &Options); 84 85/// Implements X86-only directives for assembly emission. 86MCTargetStreamer *createX86AsmTargetStreamer(MCStreamer &S, 87 formatted_raw_ostream &OS, 88 MCInstPrinter *InstPrint, 89 bool isVerboseAsm); 90 91/// Implements X86-only directives for object files. 92MCTargetStreamer *createX86ObjectTargetStreamer(MCStreamer &OS, 93 const MCSubtargetInfo &STI); 94 95/// Construct an X86 Windows COFF machine code streamer which will generate 96/// PE/COFF format object files. 97/// 98/// Takes ownership of \p AB and \p CE. 99MCStreamer *createX86WinCOFFStreamer(MCContext &C, 100 std::unique_ptr<MCAsmBackend> &&AB, 101 std::unique_ptr<MCObjectWriter> &&OW, 102 std::unique_ptr<MCCodeEmitter> &&CE, 103 bool RelaxAll, 104 bool IncrementalLinkerCompatible); 105 106/// Construct an X86 Mach-O object writer. 107std::unique_ptr<MCObjectTargetWriter> 108createX86MachObjectWriter(bool Is64Bit, uint32_t CPUType, uint32_t CPUSubtype); 109 110/// Construct an X86 ELF object writer. 111std::unique_ptr<MCObjectTargetWriter> 112createX86ELFObjectWriter(bool IsELF64, uint8_t OSABI, uint16_t EMachine); 113/// Construct an X86 Win COFF object writer. 114std::unique_ptr<MCObjectTargetWriter> 115createX86WinCOFFObjectWriter(bool Is64Bit); 116 117/// Returns the sub or super register of a specific X86 register. 118/// e.g. getX86SubSuperRegister(X86::EAX, 16) returns X86::AX. 119/// Aborts on error. 120MCRegister getX86SubSuperRegister(MCRegister, unsigned, bool High=false); 121 122/// Returns the sub or super register of a specific X86 register. 123/// Like getX86SubSuperRegister() but returns 0 on error. 124MCRegister getX86SubSuperRegisterOrZero(MCRegister, unsigned, 125 bool High = false); 126 127} // End llvm namespace 128 129 130// Defines symbolic names for X86 registers. This defines a mapping from 131// register name to register number. 132// 133#define GET_REGINFO_ENUM 134#include "X86GenRegisterInfo.inc" 135 136// Defines symbolic names for the X86 instructions. 137// 138#define GET_INSTRINFO_ENUM 139#define GET_INSTRINFO_MC_HELPER_DECLS 140#include "X86GenInstrInfo.inc" 141 142#define GET_SUBTARGETINFO_ENUM 143#include "X86GenSubtargetInfo.inc" 144 145#endif 146