Searched refs:Hexagon (Results 26 - 50 of 65) sorted by relevance

123

/freebsd-13-stable/contrib/llvm-project/llvm/lib/Target/Hexagon/AsmParser/
H A DHexagonAsmParser.cpp1 //===-- HexagonAsmParser.cpp - Parse Hexagon asm to MCInst instructions----===//
165 MCB.setOpcode(Hexagon::BUNDLE);
193 /// HexagonOperand - Instances of this class represent a parsed Hexagon machine
521 if (getSTI().getFeatureBits()[Hexagon::FeatureMemNoShuf])
659 /// ParseDirective parses the Hexagon specific directives
733 // Hexagon's .lcomm:
817 if (HexagonMCRegisterClasses[Hexagon::V62RegsRegClassID].contains(MatchNum))
818 if (!getSTI().getFeatureBits()[Hexagon::ArchV62])
880 case Hexagon::P0:
881 case Hexagon
[all...]
/freebsd-13-stable/contrib/llvm-project/llvm/lib/Target/Hexagon/
H A DHexagonFrameLowering.cpp68 // Hexagon stack frame layout as defined by the ABI:
153 cl::Hidden, cl::desc("Disable Dealloc Return for Hexagon target"));
236 "Hexagon call frame information", false, false)
247 if (Reg < Hexagon::D0 || Reg > Hexagon::D15)
266 static_assert(Hexagon::R1 > 0,
290 case Hexagon::PS_alloca:
291 case Hexagon::PS_aligna:
341 return RetOpc == Hexagon::PS_tailcall_i || RetOpc == Hexagon
[all...]
H A DHexagonConstPropagation.cpp1837 // Hexagon-specific code.
1905 return "Hexagon Constant Propagation";
1923 "Hexagon Constant Propagation", false, false)
1961 unsigned SubLo = HRI.getHexagonSubRegIndex(DefRC, Hexagon::ps_sub_lo);
1962 unsigned SubHi = HRI.getHexagonSubRegIndex(DefRC, Hexagon::ps_sub_hi);
1987 case Hexagon::A2_tfrsi:
1988 case Hexagon::A2_tfrpi:
1989 case Hexagon::CONST32:
1990 case Hexagon::CONST64:
2011 case Hexagon
[all...]
H A DHexagonBitSimplify.cpp190 return "Hexagon bit simplification";
236 unsigned NewSub = Hexagon::NoSubRegister);
259 "Hexagon bit simplification", false, false)
262 "Hexagon bit simplification", false, false)
417 case Hexagon::DoubleRegsRegClassID:
418 case Hexagon::HvxWRRegClassID:
420 if (RR.Sub == Hexagon::isub_hi || RR.Sub == Hexagon::vsub_hi)
440 unsigned SubLo = HRI.getHexagonSubRegIndex(DstRC, Hexagon::ps_sub_lo);
441 unsigned SubHi = HRI.getHexagonSubRegIndex(DstRC, Hexagon
[all...]
H A DHexagonSplitDouble.cpp70 return "Hexagon Split Double Registers";
130 &Hexagon::DoubleRegsRegClass;
133 "Hexagon Split Double Registers", false, false)
177 case Hexagon::L2_loadrd_io:
182 case Hexagon::S2_storerd_io:
187 case Hexagon::L2_loadrd_pi:
188 case Hexagon::S2_storerd_pi:
190 case Hexagon::A2_tfrpi:
191 case Hexagon::A2_combineii:
192 case Hexagon
[all...]
H A DHexagonHardwareLoops.cpp9 // This pass identifies loops where we can generate the Hexagon hardware
118 StringRef getPassName() const override { return "Hexagon Hardware Loops"; }
368 "Hexagon Hardware Loops", false, false)
372 "Hexagon Hardware Loops", false, false)
379 LLVM_DEBUG(dbgs() << "********* Hexagon Hardware Loops *********\n");
514 case Hexagon::C2_cmpeq:
515 case Hexagon::C2_cmpeqi:
516 case Hexagon::C2_cmpeqp:
519 case Hexagon::C4_cmpneq:
520 case Hexagon
[all...]
H A DHexagonVLIWPacketizer.cpp20 #include "Hexagon.h"
60 cl::desc("Disable Hexagon packetizer pass"));
106 StringRef getPassName() const override { return "Hexagon Packetizer"; }
125 "Hexagon Packetizer", false, false)
131 "Hexagon Packetizer", false, false)
296 auto *ExtMI = MF.CreateMachineInstr(HII->get(Hexagon::A4_ext), DebugLoc());
334 return MI.getOpcode() == Hexagon::J2_jump;
339 case Hexagon::Y2_barrier:
365 if (NewRC == &Hexagon::PredRegsRegClass) {
464 if (RC == &Hexagon
[all...]
H A DHexagonEarlyIfConv.cpp9 // This implements a Hexagon-specific if-conversion pass that runs on the
61 #include "Hexagon.h"
104 cl::desc("Size limit in Hexagon early if-conversion"));
160 return "Hexagon early if conversion";
228 "Hexagon early if conversion", false, false)
251 if (Opc != Hexagon::J2_jumpt && Opc != Hexagon::J2_jumpf)
262 assert(T2I == B->end() || T2I->getOpcode() == Hexagon::J2_jump);
273 if (Opc == Hexagon::J2_jumpt)
376 bool IsJMP = (Opc == Hexagon
[all...]
H A DHexagonISelLowering.cpp1 //===-- HexagonISelLowering.cpp - Hexagon DAG Lowering Implementation -----===//
9 // This file implements the interfaces that Hexagon uses to lower LLVM code
15 #include "Hexagon.h"
70 cl::desc("Control jump table emission on Hexagon target"));
74 cl::desc("Enable Hexagon SDNode scheduling"));
135 // Implement calling convention for Hexagon.
141 Hexagon::R0, Hexagon::R1, Hexagon::R2,
142 Hexagon
[all...]
H A DHexagonISelDAGToDAG.cpp1 //===-- HexagonISelDAGToDAG.cpp - A dag to dag inst selector for Hexagon --===//
9 // This file defines an instruction selector for the Hexagon target.
14 #include "Hexagon.h"
58 /// Hexagon-specific DAG, ready for instruction scheduling.
85 Opcode = IsValidInc ? Hexagon::L2_loadrub_pi : Hexagon::L2_loadrub_io;
87 Opcode = IsValidInc ? Hexagon::L2_loadrb_pi : Hexagon::L2_loadrb_io;
91 Opcode = IsValidInc ? Hexagon::L2_loadruh_pi : Hexagon
[all...]
H A DHexagonArch.h19 namespace Hexagon { namespace in namespace:llvm
35 } // namespace Hexagon
H A DHexagonStoreWidening.cpp80 StringRef getPassName() const override { return "Hexagon Store Widening"; }
119 "Hexagon Store Widening", false, false)
133 case Hexagon::S4_storeirb_io:
134 case Hexagon::S4_storeirh_io:
135 case Hexagon::S4_storeiri_io: {
158 case Hexagon::S4_storeirb_io:
159 case Hexagon::S4_storeirh_io:
160 case Hexagon::S4_storeiri_io:
425 unsigned WOpc = (TotalSize == 2) ? Hexagon::S4_storeirh_io :
426 (TotalSize == 4) ? Hexagon
[all...]
H A DHexagonGenMux.cpp73 return "Hexagon generate mux instructions";
124 return Hexagon::DoubleRegsRegClass.contains(Reg);
144 "Hexagon generate mux instructions", false, false)
199 case Hexagon::A2_tfrt:
200 case Hexagon::A2_tfrf:
201 case Hexagon::C2_cmoveit:
202 case Hexagon::C2_cmoveif:
212 return IsReg2 ? Hexagon::C2_mux : Hexagon::C2_muxir;
214 return Hexagon
[all...]
H A DHexagonISelDAGToDAGHVX.cpp9 #include "Hexagon.h"
49 // [1] Hexagon's vdelta/vrdelta allow an element to be routed to both
1014 unsigned Sub = (Part == OpRef::LoHalf) ? Hexagon::vsub_lo
1015 : Hexagon::vsub_hi;
1044 DAG.getTargetConstant(Hexagon::HvxWRRegClassID, dl, MVT::i32),
1045 Lo, DAG.getTargetConstant(Hexagon::vsub_lo, dl, MVT::i32),
1046 Hi, DAG.getTargetConstant(Hexagon::vsub_hi, dl, MVT::i32),
1104 unsigned Opc = IsRight ? Hexagon::V6_valignbi
1105 : Hexagon::V6_vlalignbi;
1109 Results.push(Hexagon
[all...]
H A DHexagonRegisterInfo.h1 //==- HexagonRegisterInfo.h - Hexagon Register Information Impl --*- C++ -*-==//
9 // This file contains the Hexagon implementation of the TargetRegisterInfo
24 namespace Hexagon { namespace in namespace:llvm
H A DHexagonISelLoweringHVX.cpp26 addRegisterClass(MVT::v64i8, &Hexagon::HvxVRRegClass);
27 addRegisterClass(MVT::v32i16, &Hexagon::HvxVRRegClass);
28 addRegisterClass(MVT::v16i32, &Hexagon::HvxVRRegClass);
29 addRegisterClass(MVT::v128i8, &Hexagon::HvxWRRegClass);
30 addRegisterClass(MVT::v64i16, &Hexagon::HvxWRRegClass);
31 addRegisterClass(MVT::v32i32, &Hexagon::HvxWRRegClass);
40 addRegisterClass(MVT::v16i1, &Hexagon::HvxQRRegClass);
41 addRegisterClass(MVT::v32i1, &Hexagon::HvxQRRegClass);
42 addRegisterClass(MVT::v64i1, &Hexagon::HvxQRRegClass);
44 addRegisterClass(MVT::v128i8, &Hexagon
[all...]
H A DHexagonBitTracker.cpp10 #include "Hexagon.h"
96 bool IsSubLo = (Sub == HRI.getHexagonSubRegIndex(RC, Hexagon::ps_sub_lo));
98 case Hexagon::DoubleRegsRegClassID:
99 case Hexagon::HvxWRRegClassID:
100 case Hexagon::HvxVQRRegClassID:
116 using namespace Hexagon;
139 bool IsSubLo = (Idx == HRI.getHexagonSubRegIndex(RC, Hexagon::ps_sub_lo));
140 bool IsSubHi = (Idx == HRI.getHexagonSubRegIndex(RC, Hexagon::ps_sub_hi));
145 case Hexagon::DoubleRegsRegClassID:
146 return Hexagon
[all...]
H A DHexagonExpandCondsets.cpp151 StringRef getPassName() const override { return "Hexagon Expand Condsets"; }
253 "Hexagon Expand Condsets", false, false)
258 "Hexagon Expand Condsets", false, false)
262 case Hexagon::isub_lo:
263 case Hexagon::vsub_lo:
265 case Hexagon::isub_hi:
266 case Hexagon::vsub_hi:
268 case Hexagon::NoSubRegister:
277 case Hexagon::C2_mux:
278 case Hexagon
[all...]
H A DHexagonSubtarget.cpp1 //===- HexagonSubtarget.cpp - Hexagon Subtarget Information ---------------===//
9 // This file implements the Hexagon specific subclass of TargetSubtarget.
13 #include "Hexagon.h"
54 cl::desc("Disable Hexagon MI Scheduling"));
58 cl::desc("Enable subregister liveness tracking for Hexagon"));
93 Optional<Hexagon::ArchEnum> ArchVer =
94 Hexagon::GetCpu(Hexagon::CpuTable, CPUString);
98 llvm_unreachable("Unrecognized Hexagon processor version");
121 setFeatureBits(Features.reset(Hexagon
[all...]
/freebsd-13-stable/contrib/llvm-project/llvm/lib/Target/Hexagon/MCTargetDesc/
H A DHexagonMCTargetDesc.cpp1 //===-- HexagonMCTargetDesc.cpp - Hexagon Target Descriptions -------------===//
9 // This file provides Hexagon specific target descriptions.
58 cl::desc("Disable looking for compound instructions for Hexagon"));
62 cl::desc("Disable looking for duplex instructions for Hexagon"));
65 cl::opt<bool> MV5("mv5", cl::Hidden, cl::desc("Build for Hexagon V5"),
67 cl::opt<bool> MV55("mv55", cl::Hidden, cl::desc("Build for Hexagon V55"),
69 cl::opt<bool> MV60("mv60", cl::Hidden, cl::desc("Build for Hexagon V60"),
71 cl::opt<bool> MV62("mv62", cl::Hidden, cl::desc("Build for Hexagon V62"),
73 cl::opt<bool> MV65("mv65", cl::Hidden, cl::desc("Build for Hexagon V65"),
75 cl::opt<bool> MV66("mv66", cl::Hidden, cl::desc("Build for Hexagon V6
[all...]
H A DHexagonMCCodeEmitter.cpp1 //===- HexagonMCCodeEmitter.cpp - Hexagon Target Descriptions -------------===//
41 using namespace Hexagon;
48 #define P(x) Hexagon::fixup_Hexagon##x
426 if (Opc >= Hexagon::DuplexIClass0 && Opc <= Hexagon::DuplexIClassF) {
429 unsigned DupIClass = MI.getOpcode() - Hexagon::DuplexIClass0;
462 Hexagon::Fixups HexagonMCCodeEmitter::getFixupNoBits(
467 using namespace Hexagon;
501 return Hexagon::Fixups(F->second);
533 case Hexagon
[all...]
H A DHexagonFixupKinds.h1 //===-- HexagonFixupKinds.h - Hexagon Specific Fixup Entries --------------===//
15 namespace Hexagon { namespace in namespace:llvm
139 } // namespace Hexagon
H A DHexagonMCCodeEmitter.h1 //===- HexagonMCCodeEmitter.h - Hexagon Target Descriptions -----*- C++ -*-===//
10 /// Definition for classes that emit Hexagon machine code from MCInsts
78 Hexagon::Fixups getFixupNoBits(MCInstrInfo const &MCII, const MCInst &MI,
/freebsd-13-stable/contrib/llvm-project/lld/ELF/Arch/
H A DHexagon.cpp1 //===-- Hexagon.cpp -------------------------------------------------------===//
26 class Hexagon final : public TargetInfo {
28 Hexagon();
41 Hexagon::Hexagon() { function in class:Hexagon
54 // Hexagon Linux uses 64K pages by default.
62 uint32_t Hexagon::calcEFlags() const {
91 RelExpr Hexagon::getRelExpr(RelType type, const Symbol &s,
242 void Hexagon::relocate(uint8_t *loc, const Relocation &rel,
348 void Hexagon
[all...]
/freebsd-13-stable/contrib/llvm-project/clang/lib/Sema/
H A DSemaChecking.cpp2621 { Hexagon::BI__builtin_circ_ldd, {{ 3, true, 4, 3 }} },
2622 { Hexagon::BI__builtin_circ_ldw, {{ 3, true, 4, 2 }} },
2623 { Hexagon::BI__builtin_circ_ldh, {{ 3, true, 4, 1 }} },
2624 { Hexagon::BI__builtin_circ_lduh, {{ 3, true, 4, 1 }} },
2625 { Hexagon::BI__builtin_circ_ldb, {{ 3, true, 4, 0 }} },
2626 { Hexagon::BI__builtin_circ_ldub, {{ 3, true, 4, 0 }} },
2627 { Hexagon::BI__builtin_circ_std, {{ 3, true, 4, 3 }} },
2628 { Hexagon::BI__builtin_circ_stw, {{ 3, true, 4, 2 }} },
2629 { Hexagon::BI__builtin_circ_sth, {{ 3, true, 4, 1 }} },
2630 { Hexagon
[all...]

Completed in 324 milliseconds

123