Lines Matching refs:Hexagon
1 //===-- HexagonISelLowering.cpp - Hexagon DAG Lowering Implementation -----===//
9 // This file implements the interfaces that Hexagon uses to lower LLVM code
15 #include "Hexagon.h"
70 cl::desc("Control jump table emission on Hexagon target"));
74 cl::desc("Enable Hexagon SDNode scheduling"));
135 // Implement calling convention for Hexagon.
141 Hexagon::R0, Hexagon::R1, Hexagon::R2,
142 Hexagon::R3, Hexagon::R4, Hexagon::R5
248 .Case("r0", Hexagon::R0)
249 .Case("r1", Hexagon::R1)
250 .Case("r2", Hexagon::R2)
251 .Case("r3", Hexagon::R3)
252 .Case("r4", Hexagon::R4)
253 .Case("r5", Hexagon::R5)
254 .Case("r6", Hexagon::R6)
255 .Case("r7", Hexagon::R7)
256 .Case("r8", Hexagon::R8)
257 .Case("r9", Hexagon::R9)
258 .Case("r10", Hexagon::R10)
259 .Case("r11", Hexagon::R11)
260 .Case("r12", Hexagon::R12)
261 .Case("r13", Hexagon::R13)
262 .Case("r14", Hexagon::R14)
263 .Case("r15", Hexagon::R15)
264 .Case("r16", Hexagon::R16)
265 .Case("r17", Hexagon::R17)
266 .Case("r18", Hexagon::R18)
267 .Case("r19", Hexagon::R19)
268 .Case("r20", Hexagon::R20)
269 .Case("r21", Hexagon::R21)
270 .Case("r22", Hexagon::R22)
271 .Case("r23", Hexagon::R23)
272 .Case("r24", Hexagon::R24)
273 .Case("r25", Hexagon::R25)
274 .Case("r26", Hexagon::R26)
275 .Case("r27", Hexagon::R27)
276 .Case("r28", Hexagon::R28)
277 .Case("r29", Hexagon::R29)
278 .Case("r30", Hexagon::R30)
279 .Case("r31", Hexagon::R31)
280 .Case("r1:0", Hexagon::D0)
281 .Case("r3:2", Hexagon::D1)
282 .Case("r5:4", Hexagon::D2)
283 .Case("r7:6", Hexagon::D3)
284 .Case("r9:8", Hexagon::D4)
285 .Case("r11:10", Hexagon::D5)
286 .Case("r13:12", Hexagon::D6)
287 .Case("r15:14", Hexagon::D7)
288 .Case("r17:16", Hexagon::D8)
289 .Case("r19:18", Hexagon::D9)
290 .Case("r21:20", Hexagon::D10)
291 .Case("r23:22", Hexagon::D11)
292 .Case("r25:24", Hexagon::D12)
293 .Case("r27:26", Hexagon::D13)
294 .Case("r29:28", Hexagon::D14)
295 .Case("r31:30", Hexagon::D15)
296 .Case("sp", Hexagon::R29)
297 .Case("fp", Hexagon::R30)
298 .Case("lr", Hexagon::R31)
299 .Case("p0", Hexagon::P0)
300 .Case("p1", Hexagon::P1)
301 .Case("p2", Hexagon::P2)
302 .Case("p3", Hexagon::P3)
303 .Case("sa0", Hexagon::SA0)
304 .Case("lc0", Hexagon::LC0)
305 .Case("sa1", Hexagon::SA1)
306 .Case("lc1", Hexagon::LC1)
307 .Case("m0", Hexagon::M0)
308 .Case("m1", Hexagon::M1)
309 .Case("usr", Hexagon::USR)
310 .Case("ugp", Hexagon::UGP)
352 Register PredR = MRI.createVirtualRegister(&Hexagon::PredRegsRegClass);
501 Align VecAlign(HRI.getSpillAlignment(Hexagon::HvxVRRegClass));
697 // is marked as having side-effects, while the register read on Hexagon does
779 // stack where the return value will be stored. For Hexagon, the location on
785 case Hexagon::IntRegsRegClassID:
786 return Reg - Hexagon::R0 + 1;
787 case Hexagon::DoubleRegsRegClassID:
788 return (Reg - Hexagon::D0 + 1) * 2;
789 case Hexagon::HvxVRRegClassID:
790 return Reg - Hexagon::V0 + 1;
791 case Hexagon::HvxWRRegClassID:
792 return (Reg - Hexagon::W0 + 1) * 2;
874 MRI.addLiveIn(Hexagon::R0+i);
1277 SDValue Ops[] = { Chain, TGA, DAG.getRegister(Hexagon::R0, PtrVT),
1299 SDValue TP = DAG.getCopyFromReg(DAG.getEntryNode(), dl, Hexagon::UGP, PtrVT);
1341 SDValue TP = DAG.getCopyFromReg(DAG.getEntryNode(), dl, Hexagon::UGP, PtrVT);
1375 Chain = DAG.getCopyToReg(DAG.getEntryNode(), dl, Hexagon::R0, Chain, InFlag);
1384 Hexagon::R0, Flags);
1446 addRegisterClass(MVT::i1, &Hexagon::PredRegsRegClass);
1447 addRegisterClass(MVT::v2i1, &Hexagon::PredRegsRegClass); // bbbbaaaa
1448 addRegisterClass(MVT::v4i1, &Hexagon::PredRegsRegClass); // ddccbbaa
1449 addRegisterClass(MVT::v8i1, &Hexagon::PredRegsRegClass); // hgfedcba
1450 addRegisterClass(MVT::i32, &Hexagon::IntRegsRegClass);
1451 addRegisterClass(MVT::v2i16, &Hexagon::IntRegsRegClass);
1452 addRegisterClass(MVT::v4i8, &Hexagon::IntRegsRegClass);
1453 addRegisterClass(MVT::i64, &Hexagon::DoubleRegsRegClass);
1454 addRegisterClass(MVT::v8i8, &Hexagon::DoubleRegsRegClass);
1455 addRegisterClass(MVT::v4i16, &Hexagon::DoubleRegsRegClass);
1456 addRegisterClass(MVT::v2i32, &Hexagon::DoubleRegsRegClass);
1458 addRegisterClass(MVT::f32, &Hexagon::IntRegsRegClass);
1459 addRegisterClass(MVT::f64, &Hexagon::DoubleRegsRegClass);
1495 // Hexagon needs to optimize cases with negative constants.
1523 // Hexagon has A4_addp_c and A4_subp_c that take and generate a carry bit,
2181 return getInstr(Hexagon::S2_vtrunehb, dl, VecTy, {Concat10}, DAG);
2183 return getInstr(Hexagon::S2_vtrunohb, dl, VecTy, {Concat10}, DAG);
2188 return getInstr(Hexagon::S2_vtrunehb, dl, VecTy, {Concat01}, DAG);
2190 return getInstr(Hexagon::S2_vtrunohb, dl, VecTy, {Concat01}, DAG);
2206 return getInstr(Hexagon::S2_shuffeh, dl, VecTy, {Op1, Op0}, DAG);
2208 return getInstr(Hexagon::S2_shuffoh, dl, VecTy, {Op1, Op0}, DAG);
2210 return getInstr(Hexagon::S2_vtrunewh, dl, VecTy, {Op1, Op0}, DAG);
2212 return getInstr(Hexagon::S2_vtrunowh, dl, VecTy, {Op1, Op0}, DAG);
2215 return getInstr(Hexagon::S2_packhl, dl, VecTy, {P.second, P.first}, DAG);
2220 return getInstr(Hexagon::S2_shuffeb, dl, VecTy, {Op1, Op0}, DAG);
2222 return getInstr(Hexagon::S2_shuffob, dl, VecTy, {Op1, Op0}, DAG);
2228 // Create a Hexagon-specific node for shifting a vector by an integer.
2280 return getInstr(Hexagon::C2_tfrrp, dl, ResTy, Ext, DAG);
2345 SDValue N = getInstr(Hexagon::A2_combine_ll, dl, MVT::i32,
2391 SDValue R = getInstr(Hexagon::A2_combine_ll, dl, MVT::i32, {B1, B0}, DAG);
2475 // Special case for v{8,4,2}i1 (the only boolean vectors legal in Hexagon
2491 SDValue A0 = getInstr(Hexagon::C2_tfrpr, dl, MVT::i32, {VecV}, DAG);
2514 T1 = DAG.getTargetExtractSubreg(Hexagon::isub_lo, dl, MVT::i32, T1);
2535 unsigned SubIdx = Off == 0 ? Hexagon::isub_lo : Hexagon::isub_hi;
2581 ValR = DAG.getTargetExtractSubreg(Hexagon::isub_lo, dl, MVT::i32, ValR);
2633 return getInstr(Hexagon::S2_vsxtbh, dl, MVT::i64, {Vec32}, DAG);
2642 return getInstr(Hexagon::S2_vtrunehb, dl, MVT::i32, {Vec64}, DAG);
2711 return getInstr(Hexagon::C2_tfrrp, dl, VecTy, {Rs[0]}, DAG);
2751 W = DAG.getTargetExtractSubreg(Hexagon::isub_lo, dl, MVT::i32, W);
3004 unsigned OffsetReg = Hexagon::R28;
3007 DAG.getNode(ISD::ADD, dl, PtrVT, DAG.getRegister(Hexagon::R30, PtrVT),
3121 SDValue P = getInstr(Hexagon::C2_tfrpr, dl, MVT::i32,
3218 return {0u, &Hexagon::IntRegsRegClass};
3221 return {0u, &Hexagon::DoubleRegsRegClass};
3227 return {0u, &Hexagon::ModRegsRegClass};
3234 return {0u, &Hexagon::HvxQRRegClass};
3242 return {0u, &Hexagon::HvxVRRegClass};
3245 return {0u, &Hexagon::HvxVRRegClass};
3246 return {0u, &Hexagon::HvxWRRegClass};
3248 return {0u, &Hexagon::HvxWRRegClass};
3425 return std::make_pair(&Hexagon::HvxQRRegClass, 1);
3427 return std::make_pair(&Hexagon::HvxVRRegClass, 1);
3429 return std::make_pair(&Hexagon::HvxWRRegClass, 1);