Lines Matching refs:Hexagon
9 // This pass identifies loops where we can generate the Hexagon hardware
118 StringRef getPassName() const override { return "Hexagon Hardware Loops"; }
368 "Hexagon Hardware Loops", false, false)
372 "Hexagon Hardware Loops", false, false)
379 LLVM_DEBUG(dbgs() << "********* Hexagon Hardware Loops *********\n");
514 case Hexagon::C2_cmpeq:
515 case Hexagon::C2_cmpeqi:
516 case Hexagon::C2_cmpeqp:
519 case Hexagon::C4_cmpneq:
520 case Hexagon::C4_cmpneqi:
523 case Hexagon::C2_cmplt:
526 case Hexagon::C2_cmpltu:
529 case Hexagon::C4_cmplte:
530 case Hexagon::C4_cmpltei:
533 case Hexagon::C4_cmplteu:
534 case Hexagon::C4_cmplteui:
537 case Hexagon::C2_cmpgt:
538 case Hexagon::C2_cmpgti:
539 case Hexagon::C2_cmpgtp:
542 case Hexagon::C2_cmpgtu:
543 case Hexagon::C2_cmpgtui:
544 case Hexagon::C2_cmpgtup:
547 case Hexagon::C2_cmpgei:
550 case Hexagon::C2_cmpgeui:
739 if (StartValInstr && (StartValInstr->getOpcode() == Hexagon::A2_tfrsi ||
740 StartValInstr->getOpcode() == Hexagon::A2_tfrpi))
745 if (EndValInstr && (EndValInstr->getOpcode() == Hexagon::A2_tfrsi ||
746 EndValInstr->getOpcode() == Hexagon::A2_tfrpi))
837 // will be "reg - imm". Hexagon's "subtract immediate" instruction
898 if (!SR && RC == &Hexagon::DoubleRegsRegClass)
900 const TargetRegisterClass *IntRC = &Hexagon::IntRegsRegClass;
910 const MCInstrDesc &SubD = RegToReg ? TII->get(Hexagon::A2_sub) :
911 (RegToImm ? TII->get(Hexagon::A2_subri) :
912 TII->get(Hexagon::A2_addi));
930 if (EndValInstr->getOpcode() == Hexagon::A2_addi &&
955 MCInstrDesc const &AddD = TII->get(Hexagon::A2_addi);
976 const MCInstrDesc &LsrD = TII->get(Hexagon::S2_lsr_i_r);
997 using namespace Hexagon;
1155 LOOP_i = Hexagon::J2_loop1i;
1156 LOOP_r = Hexagon::J2_loop1r;
1157 ENDLOOP = Hexagon::ENDLOOP1;
1160 LOOP_i = Hexagon::J2_loop0i;
1161 LOOP_r = Hexagon::J2_loop0r;
1162 ENDLOOP = Hexagon::ENDLOOP0;
1248 Register CountReg = MRI->createVirtualRegister(&Hexagon::IntRegsRegClass);
1261 Register CountReg = MRI->createVirtualRegister(&Hexagon::IntRegsRegClass);
1262 BuildMI(*Preheader, InsertPos, DL, TII->get(Hexagon::A2_tfrsi), CountReg)
1286 if (LastI->getOpcode() == Hexagon::J2_jumpt ||
1287 LastI->getOpcode() == Hexagon::J2_jumpf) {
1519 case Hexagon::A2_tfrsi:
1520 case Hexagon::A2_tfrpi:
1521 case Hexagon::CONST32:
1522 case Hexagon::CONST64:
1529 case Hexagon::A2_combineii:
1530 case Hexagon::A4_combineir:
1531 case Hexagon::A4_combineii:
1532 case Hexagon::A4_combineri:
1533 case Hexagon::A2_combinew: {
1550 if (Sub2 == Hexagon::isub_lo && Sub4 == Hexagon::isub_hi)
1552 else if (Sub2 == Hexagon::isub_hi && Sub4 == Hexagon::isub_lo)
1566 case Hexagon::isub_lo:
1569 case Hexagon::isub_hi:
1599 if (CmpOpc == Hexagon::A4_cmpbeqi)
1601 if (CmpOpc == Hexagon::A4_cmpbgti)
1789 nonIndI->getOpcode() == Hexagon::A2_addi &&