Lines Matching refs:Hexagon
68 // Hexagon stack frame layout as defined by the ABI:
153 cl::Hidden, cl::desc("Disable Dealloc Return for Hexagon target"));
236 "Hexagon call frame information", false, false)
247 if (Reg < Hexagon::D0 || Reg > Hexagon::D15)
266 static_assert(Hexagon::R1 > 0,
290 case Hexagon::PS_alloca:
291 case Hexagon::PS_aligna:
341 return RetOpc == Hexagon::PS_tailcall_i || RetOpc == Hexagon::PS_tailcall_r;
363 case Hexagon::RESTORE_DEALLOC_RET_JMP_V4:
364 case Hexagon::RESTORE_DEALLOC_RET_JMP_V4_PIC:
365 case Hexagon::RESTORE_DEALLOC_RET_JMP_V4_EXT:
366 case Hexagon::RESTORE_DEALLOC_RET_JMP_V4_EXT_PIC:
367 case Hexagon::RESTORE_DEALLOC_BEFORE_TAILCALL_V4_EXT:
368 case Hexagon::RESTORE_DEALLOC_BEFORE_TAILCALL_V4_EXT_PIC:
369 case Hexagon::RESTORE_DEALLOC_BEFORE_TAILCALL_V4:
370 case Hexagon::RESTORE_DEALLOC_BEFORE_TAILCALL_V4_PIC:
438 BitVector CSR(Hexagon::NUM_TARGET_REGS);
617 if (MI.getOpcode() == Hexagon::PS_alloca)
621 assert((MI->getOpcode() == Hexagon::PS_alloca) && "Expected alloca");
638 BuildMI(MBB, InsertPt, dl, HII.get(Hexagon::A2_addi), SP)
669 LDOpc = Hexagon::L2_loadrb_io;
670 STOpc = Hexagon::S2_storerb_io;
673 LDOpc = Hexagon::L2_loadrh_io;
674 STOpc = Hexagon::S2_storerh_io;
677 LDOpc = Hexagon::L2_loadri_io;
678 STOpc = Hexagon::S2_storeri_io;
682 LDOpc = Hexagon::L2_loadrd_io;
683 STOpc = Hexagon::S2_storerd_io;
687 unsigned RegUsed = LDOpc == Hexagon::L2_loadrd_io ? Hexagon::D3
688 : Hexagon::R6;
731 BuildMI(MBB, InsertPt, dl, HII.get(Hexagon::S2_storeri_io))
734 .addReg(Hexagon::R0 + j)
743 BuildMI(MBB, InsertPt, dl, HII.get(Hexagon::A2_andir), SP)
751 BuildMI(MBB, InsertPt, dl, HII.get(Hexagon::PS_call_stk))
755 BuildMI(MBB, InsertPt, dl, HII.get(Hexagon::A2_addi), SP)
776 // On Hexagon Linux, deallocate the stack for the register saved area.
783 BuildMI(MBB, InsertPt, dl, HII.get(Hexagon::A2_addi), SP)
794 if (RetOpc == Hexagon::EH_RETURN_JMPR) {
795 BuildMI(MBB, InsertPt, dl, HII.get(Hexagon::L2_deallocframe))
796 .addDef(Hexagon::D15)
797 .addReg(Hexagon::R30);
798 BuildMI(MBB, InsertPt, dl, HII.get(Hexagon::A2_add), SP)
800 .addReg(Hexagon::R28);
806 if (RetOpc == Hexagon::RESTORE_DEALLOC_RET_JMP_V4 ||
807 RetOpc == Hexagon::RESTORE_DEALLOC_RET_JMP_V4_PIC ||
808 RetOpc == Hexagon::RESTORE_DEALLOC_RET_JMP_V4_EXT ||
809 RetOpc == Hexagon::RESTORE_DEALLOC_RET_JMP_V4_EXT_PIC) {
829 if (COpc == Hexagon::RESTORE_DEALLOC_BEFORE_TAILCALL_V4 ||
830 COpc == Hexagon::RESTORE_DEALLOC_BEFORE_TAILCALL_V4_PIC ||
831 COpc == Hexagon::RESTORE_DEALLOC_BEFORE_TAILCALL_V4_EXT ||
832 COpc == Hexagon::RESTORE_DEALLOC_BEFORE_TAILCALL_V4_EXT_PIC ||
833 COpc == Hexagon::PS_call_nr || COpc == Hexagon::PS_callr_nr)
844 if (RetOpc != Hexagon::PS_jmpret || DisableDeallocRet) {
845 BuildMI(MBB, InsertPt, dl, HII.get(Hexagon::L2_deallocframe))
846 .addDef(Hexagon::D15)
847 .addReg(Hexagon::R30);
850 unsigned NewOpc = Hexagon::L4_return;
852 .addDef(Hexagon::D15)
853 .addReg(Hexagon::R30);
868 (I->getOpcode() != Hexagon::RESTORE_DEALLOC_BEFORE_TAILCALL_V4_EXT &&
869 I->getOpcode() != Hexagon::RESTORE_DEALLOC_BEFORE_TAILCALL_V4_EXT_PIC &&
870 I->getOpcode() != Hexagon::RESTORE_DEALLOC_BEFORE_TAILCALL_V4 &&
871 I->getOpcode() != Hexagon::RESTORE_DEALLOC_BEFORE_TAILCALL_V4_PIC))
872 BuildMI(MBB, InsertPt, dl, HII.get(Hexagon::L2_deallocframe))
873 .addDef(Hexagon::D15)
874 .addReg(Hexagon::R30);
876 BuildMI(MBB, InsertPt, dl, HII.get(Hexagon::A2_addi), SP)
903 BuildMI(MBB, InsertPt, dl, HII.get(Hexagon::S2_allocframe))
911 BuildMI(MBB, InsertPt, dl, HII.get(Hexagon::A2_addi), SP)
915 BuildMI(MBB, InsertPt, dl, HII.get(Hexagon::S2_allocframe))
1001 if (I.getOpcode() == Hexagon::S2_allocframe)
1009 if (T->getOpcode() == Hexagon::S2_allocframe)
1075 Hexagon::R1, Hexagon::R0, Hexagon::R3, Hexagon::R2,
1076 Hexagon::R17, Hexagon::R16, Hexagon::R19, Hexagon::R18,
1077 Hexagon::R21, Hexagon::R20, Hexagon::R23, Hexagon::R22,
1078 Hexagon::R25, Hexagon::R24, Hexagon::R27, Hexagon::R26,
1079 Hexagon::D0, Hexagon::D1, Hexagon::D8, Hexagon::D9,
1080 Hexagon::D10, Hexagon::D11, Hexagon::D12, Hexagon::D13,
1081 Hexagon::NoRegister
1086 for (unsigned i = 0; RegsToMove[i] != Hexagon::NoRegister; ++i) {
1112 if (Reg < Hexagon::D0 || Reg > Hexagon::D15) {
1125 Register HiReg = HRI.getSubReg(Reg, Hexagon::isub_hi);
1126 Register LoReg = HRI.getSubReg(Reg, Hexagon::isub_lo);
1241 case Hexagon::R17:
1243 case Hexagon::R19:
1245 case Hexagon::R21:
1247 case Hexagon::R23:
1249 case Hexagon::R25:
1251 case Hexagon::R27:
1387 SpillOpc = IsPIC ? Hexagon::SAVE_REGISTERS_CALL_V4STK_EXT_PIC
1388 : Hexagon::SAVE_REGISTERS_CALL_V4STK_EXT;
1390 SpillOpc = IsPIC ? Hexagon::SAVE_REGISTERS_CALL_V4STK_PIC
1391 : Hexagon::SAVE_REGISTERS_CALL_V4STK;
1394 SpillOpc = IsPIC ? Hexagon::SAVE_REGISTERS_CALL_V4_EXT_PIC
1395 : Hexagon::SAVE_REGISTERS_CALL_V4_EXT;
1397 SpillOpc = IsPIC ? Hexagon::SAVE_REGISTERS_CALL_V4_PIC
1398 : Hexagon::SAVE_REGISTERS_CALL_V4;
1455 RetOpc = IsPIC ? Hexagon::RESTORE_DEALLOC_BEFORE_TAILCALL_V4_EXT_PIC
1456 : Hexagon::RESTORE_DEALLOC_BEFORE_TAILCALL_V4_EXT;
1458 RetOpc = IsPIC ? Hexagon::RESTORE_DEALLOC_BEFORE_TAILCALL_V4_PIC
1459 : Hexagon::RESTORE_DEALLOC_BEFORE_TAILCALL_V4;
1468 RetOpc = IsPIC ? Hexagon::RESTORE_DEALLOC_RET_JMP_V4_EXT_PIC
1469 : Hexagon::RESTORE_DEALLOC_RET_JMP_V4_EXT;
1471 RetOpc = IsPIC ? Hexagon::RESTORE_DEALLOC_RET_JMP_V4_PIC
1472 : Hexagon::RESTORE_DEALLOC_RET_JMP_V4;
1498 assert((Opc == Hexagon::ADJCALLSTACKDOWN || Opc == Hexagon::ADJCALLSTACKUP) &&
1614 BitVector SRegs(Hexagon::NUM_TARGET_REGS);
1650 BitVector TmpSup(Hexagon::NUM_TARGET_REGS);
1757 if (!Hexagon::ModRegsRegClass.contains(DstR) ||
1758 !Hexagon::ModRegsRegClass.contains(SrcR))
1761 Register TmpR = MRI.createVirtualRegister(&Hexagon::IntRegsRegClass);
1786 Register TmpR = MRI.createVirtualRegister(&Hexagon::IntRegsRegClass);
1787 unsigned TfrOpc = (Opc == Hexagon::STriw_pred) ? Hexagon::C2_tfrpr
1788 : Hexagon::A2_tfrcrr;
1793 BuildMI(B, It, DL, HII.get(Hexagon::S2_storeri_io))
1817 Register TmpR = MRI.createVirtualRegister(&Hexagon::IntRegsRegClass);
1818 BuildMI(B, It, DL, HII.get(Hexagon::L2_loadri_io), TmpR)
1825 unsigned TfrOpc = (Opc == Hexagon::LDriw_pred) ? Hexagon::C2_tfrrp
1826 : Hexagon::A2_tfrrcr;
1846 auto *RC = &Hexagon::HvxVRRegClass;
1852 Register TmpR0 = MRI.createVirtualRegister(&Hexagon::IntRegsRegClass);
1855 BuildMI(B, It, DL, HII.get(Hexagon::A2_tfrsi), TmpR0)
1858 BuildMI(B, It, DL, HII.get(Hexagon::V6_vandqrt), TmpR1)
1882 auto *RC = &Hexagon::HvxVRRegClass;
1887 Register TmpR0 = MRI.createVirtualRegister(&Hexagon::IntRegsRegClass);
1890 BuildMI(B, It, DL, HII.get(Hexagon::A2_tfrsi), TmpR0)
1897 BuildMI(B, It, DL, HII.get(Hexagon::V6_vandvrt), DstR)
1931 Register SrcLo = HRI.getSubReg(SrcR, Hexagon::vsub_lo);
1932 Register SrcHi = HRI.getSubReg(SrcR, Hexagon::vsub_hi);
1937 unsigned Size = HRI.getSpillSize(Hexagon::HvxVRRegClass);
1938 Align NeedAlign = HRI.getSpillAlign(Hexagon::HvxVRRegClass);
1948 StoreOpc = UseAligned(NeedAlign, HasAlign) ? Hexagon::V6_vS32b_ai
1949 : Hexagon::V6_vS32Ub_ai;
1959 StoreOpc = UseAligned(NeedAlign, HasAlign) ? Hexagon::V6_vS32b_ai
1960 : Hexagon::V6_vS32Ub_ai;
1984 Register DstHi = HRI.getSubReg(DstR, Hexagon::vsub_hi);
1985 Register DstLo = HRI.getSubReg(DstR, Hexagon::vsub_lo);
1989 unsigned Size = HRI.getSpillSize(Hexagon::HvxVRRegClass);
1990 Align NeedAlign = HRI.getSpillAlign(Hexagon::HvxVRRegClass);
1999 LoadOpc = UseAligned(NeedAlign, HasAlign) ? Hexagon::V6_vL32b_ai
2000 : Hexagon::V6_vL32Ub_ai;
2007 LoadOpc = UseAligned(NeedAlign, HasAlign) ? Hexagon::V6_vL32b_ai
2008 : Hexagon::V6_vL32Ub_ai;
2034 Align NeedAlign = HRI.getSpillAlign(Hexagon::HvxVRRegClass);
2037 unsigned StoreOpc = UseAligned ? Hexagon::V6_vS32b_ai
2038 : Hexagon::V6_vS32Ub_ai;
2064 Align NeedAlign = HRI.getSpillAlign(Hexagon::HvxVRRegClass);
2067 unsigned LoadOpc = UseAligned ? Hexagon::V6_vL32b_ai
2068 : Hexagon::V6_vL32Ub_ai;
2096 case Hexagon::STriw_pred:
2097 case Hexagon::STriw_ctr:
2100 case Hexagon::LDriw_pred:
2101 case Hexagon::LDriw_ctr:
2104 case Hexagon::PS_vstorerq_ai:
2107 case Hexagon::PS_vloadrq_ai:
2110 case Hexagon::PS_vloadrw_ai:
2113 case Hexagon::PS_vstorerw_ai:
2150 SpillRCs.insert(&Hexagon::IntRegsRegClass);
2160 case Hexagon::IntRegsRegClassID:
2163 case Hexagon::HvxQRRegClassID:
2514 CopyOpc = (MemSize == 1) ? Hexagon::A2_sxtb : Hexagon::A2_sxth;
2516 CopyOpc = (MemSize == 1) ? Hexagon::A2_zxtb : Hexagon::A2_zxth;
2559 BuildMI(MB, AI, DL, HII.get(Hexagon::A2_sub), Rd)
2564 BuildMI(MB, AI, DL, HII.get(Hexagon::A2_sub), SP)
2570 BuildMI(MB, AI, DL, HII.get(Hexagon::A2_andir), Rd)
2574 BuildMI(MB, AI, DL, HII.get(Hexagon::A2_andir), SP)
2585 BuildMI(MB, AI, DL, HII.get(Hexagon::A2_addi), Rd)
2605 if (I.getOpcode() == Hexagon::PS_aligna)
2637 BitVector Regs(Hexagon::NUM_TARGET_REGS);
2640 if (!Hexagon::DoubleRegsRegClass.contains(R))
2645 if (F != Hexagon::D8)
2710 case Hexagon::S4_storeirit_io:
2711 case Hexagon::S4_storeirif_io:
2712 case Hexagon::S4_storeiri_io:
2715 case Hexagon::S4_storeirht_io:
2716 case Hexagon::S4_storeirhf_io:
2717 case Hexagon::S4_storeirh_io:
2720 case Hexagon::S4_storeirbt_io:
2721 case Hexagon::S4_storeirbf_io:
2722 case Hexagon::S4_storeirb_io: