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  • only in /freebsd-13-stable/contrib/llvm-project/llvm/lib/Target/Hexagon/

Lines Matching refs:Hexagon

26     addRegisterClass(MVT::v64i8,  &Hexagon::HvxVRRegClass);
27 addRegisterClass(MVT::v32i16, &Hexagon::HvxVRRegClass);
28 addRegisterClass(MVT::v16i32, &Hexagon::HvxVRRegClass);
29 addRegisterClass(MVT::v128i8, &Hexagon::HvxWRRegClass);
30 addRegisterClass(MVT::v64i16, &Hexagon::HvxWRRegClass);
31 addRegisterClass(MVT::v32i32, &Hexagon::HvxWRRegClass);
40 addRegisterClass(MVT::v16i1, &Hexagon::HvxQRRegClass);
41 addRegisterClass(MVT::v32i1, &Hexagon::HvxQRRegClass);
42 addRegisterClass(MVT::v64i1, &Hexagon::HvxQRRegClass);
44 addRegisterClass(MVT::v128i8, &Hexagon::HvxVRRegClass);
45 addRegisterClass(MVT::v64i16, &Hexagon::HvxVRRegClass);
46 addRegisterClass(MVT::v32i32, &Hexagon::HvxVRRegClass);
47 addRegisterClass(MVT::v256i8, &Hexagon::HvxWRRegClass);
48 addRegisterClass(MVT::v128i16, &Hexagon::HvxWRRegClass);
49 addRegisterClass(MVT::v64i32, &Hexagon::HvxWRRegClass);
50 addRegisterClass(MVT::v32i1, &Hexagon::HvxQRRegClass);
51 addRegisterClass(MVT::v64i1, &Hexagon::HvxQRRegClass);
52 addRegisterClass(MVT::v128i1, &Hexagon::HvxQRRegClass);
519 return DAG.getTargetExtractSubreg(Hexagon::vsub_lo, dl, VecTy, S);
525 SDValue HalfV0 = getInstr(Hexagon::V6_vd0, dl, VecTy, {}, DAG);
526 SDValue HalfV1 = getInstr(Hexagon::V6_vd0, dl, VecTy, {}, DAG);
575 SDValue Q = getInstr(Hexagon::V6_pred_scalar2, dl, BoolTy,
589 return DAG.getTargetExtractSubreg(Hexagon::isub_lo, dl, MVT::i32, P);
592 return DAG.getTargetExtractSubreg(Hexagon::isub_hi, dl, MVT::i32, P);
745 return getInstr(Hexagon::C2_cmpgtui, dl, MVT::i1, {ExtB, Zero}, DAG);
824 SubIdx = Hexagon::vsub_hi;
827 SubIdx = Hexagon::vsub_lo;
914 return getInstr(Hexagon::A4_vcmpbgtui, dl, ResTy,
935 V0 = DAG.getTargetExtractSubreg(Hexagon::vsub_lo, dl, SingleTy, VecV);
936 V1 = DAG.getTargetExtractSubreg(Hexagon::vsub_hi, dl, SingleTy, VecV);
945 unsigned SubIdx = (Idx == 0) ? Hexagon::vsub_lo : Hexagon::vsub_hi;
982 SDValue R0 = DAG.getTargetExtractSubreg(Hexagon::isub_lo, dl, MVT::i32, V);
983 SDValue R1 = DAG.getTargetExtractSubreg(Hexagon::isub_hi, dl, MVT::i32, V);
1038 SDValue Q = getInstr(Hexagon::V6_pred_scalar2, dl, BoolTy,
1040 ByteVec = getInstr(Hexagon::V6_vmux, dl, ByteTy, {Q, ByteSub, ByteVec}, DAG);
1107 SDValue Vrmpy = getInstr(Hexagon::V6_vrmpyub, dl, ByteTy, {Sel, All1}, DAG);
1109 SDValue Rot = getInstr(Hexagon::V6_valignbi, dl, ByteTy,
1390 unsigned MpyOpc = ElemTy == MVT::i8 ? Hexagon::V6_vmpybv
1391 : Hexagon::V6_vmpyhv;
1407 return getInstr(Hexagon::V6_vmpyih, dl, ResTy, {Vs, Vt}, DAG);
1414 SDValue T0 = getInstr(Hexagon::V6_vmpyiowh, dl, ResTy, {Vs, Vt}, DAG);
1415 SDValue T1 = getInstr(Hexagon::V6_vaslw, dl, ResTy, {T0, S16}, DAG);
1416 SDValue T2 = getInstr(Hexagon::V6_vmpyiewuh_acc, dl, ResTy,
1448 ? (IsSigned ? Hexagon::V6_vmpybv : Hexagon::V6_vmpyubv)
1449 : (IsSigned ? Hexagon::V6_vmpyhv : Hexagon::V6_vmpyuhv);
1480 SDValue T0 = getInstr(Hexagon::V6_vmpyewuh, dl, ResTy, {Vt, Vs}, DAG);
1482 SDValue S0 = getInstr(Hexagon::V6_vasrw, dl, ResTy, {Vs, S16}, DAG);
1483 SDValue T1 = getInstr(Hexagon::V6_vmpyiewuh_acc, dl, ResTy,
1486 SDValue S2 = getInstr(Hexagon::V6_vasrw, dl, ResTy, {T1, S16}, DAG);
1488 SDValue T2 = getInstr(Hexagon::V6_vmpyiowh, dl, ResTy, {S0, Vt}, DAG);
1497 return DAG.getTargetExtractSubreg(Hexagon::vsub_lo, dl, ResTy, Pair);
1500 return DAG.getTargetExtractSubreg(Hexagon::vsub_hi, dl, ResTy, Pair);
1504 SDValue P = getInstr(Hexagon::V6_lvsplatw, dl, ResTy,
1509 SDValue T0 = getInstr(Hexagon::V6_vmpyuhv, dl, PairTy, {Vs, Vt}, DAG);
1513 SDValue T1 = getInstr(Hexagon::V6_vlsrw, dl, ResTy, {LoVec(T0), S16}, DAG);
1516 SDValue D0 = getInstr(Hexagon::V6_vdelta, dl, ResTy, {Vt, P}, DAG);
1517 SDValue T2 = getInstr(Hexagon::V6_vmpyuhv, dl, PairTy, {Vs, D0}, DAG);
1522 SDValue T3 = getInstr(Hexagon::V6_vadduhw, dl, PairTy,
1526 SDValue T5 = getInstr(Hexagon::V6_vlsrw, dl, ResTy, {T4, S16}, DAG);