Searched refs:f16 (Results 26 - 50 of 76) sorted by relevance

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/freebsd-12-stable/crypto/openssl/crypto/sha/asm/
H A Dsha512-sparcv9.pl501 ldd [%o1 + 0x00], %f16
565 faligndata %f18, %f20, %f16
607 ldd [%o1 + 0x20], %f16
639 ldd [%o1 + 0x18], %f16
651 faligndata %f14, %f16, %f12
652 faligndata %f16, %f18, %f14
653 faligndata %f18, %f20, %f16
/freebsd-12-stable/contrib/llvm-project/llvm/lib/Target/AArch64/
H A DAArch64ISelLowering.cpp139 addRegisterClass(MVT::f16, &AArch64::FPR16RegClass);
211 setOperationAction(ISD::SETCC, MVT::f16, Custom);
214 setOperationAction(ISD::STRICT_FSETCC, MVT::f16, Custom);
217 setOperationAction(ISD::STRICT_FSETCCS, MVT::f16, Custom);
225 setOperationAction(ISD::BR_CC, MVT::f16, Custom);
230 setOperationAction(ISD::SELECT, MVT::f16, Custom);
235 setOperationAction(ISD::SELECT_CC, MVT::f16, Custom);
395 setOperationAction(ISD::FCOPYSIGN, MVT::f16, Custom);
397 setOperationAction(ISD::FCOPYSIGN, MVT::f16, Promote);
399 setOperationAction(ISD::FREM, MVT::f16, Promot
[all...]
H A DAArch64CallingConvention.cpp93 else if (LocVT.SimpleTy == MVT::f16)
/freebsd-12-stable/contrib/llvm-project/llvm/lib/Target/NVPTX/
H A DNVPTXISelLowering.cpp204 // Vectors with an even number of f16 elements will be passed to
207 if (EltVT == MVT::f16 && NumElts % 2 == 0) {
382 addRegisterClass(MVT::f16, &NVPTX::Float16RegsRegClass);
386 setOperationAction(ISD::SINT_TO_FP, MVT::f16, Legal);
387 setOperationAction(ISD::FP_TO_SINT, MVT::f16, Legal);
393 setFP16OperationAction(ISD::SETCC, MVT::f16, Legal, Promote);
397 for (MVT VT : {MVT::f16, MVT::v2f16, MVT::f32, MVT::f64, MVT::i1, MVT::i8,
450 setLoadExtAction(ISD::EXTLOAD, MVT::f32, MVT::f16, Expand);
451 setLoadExtAction(ISD::EXTLOAD, MVT::f64, MVT::f16, Expand);
461 setTruncStoreAction(MVT::f32, MVT::f16, Expan
[all...]
H A DNVPTXISelDAGToDAG.cpp522 // There's no way to specify FP16 immediates in .f16 ops, so we have to
523 // load them into an .f16 register first.
525 if (N->getValueType(0) != MVT::f16)
528 cast<ConstantFPSDNode>(N)->getValueAPF(), SDLoc(N), MVT::f16);
530 CurDAG->getMachineNode(NVPTX::LOAD_CONST_F16, SDLoc(N), MVT::f16, Val);
644 // Merge (f16 extractelt(V, 0), f16 extractelt(V,1))
645 // into f16,f16 SplitF16x2(V)
647 CurDAG->getMachineNode(Op, SDLoc(N), MVT::f16, MV
[all...]
/freebsd-12-stable/sys/riscv/riscv/
H A Dswtch.S73 fsd f16, (PCB_X + 16 * 16)(\p)
122 fld f16, (PCB_X + 16 * 16)(\p)
185 fcvt.d.l f16, zero
/freebsd-12-stable/contrib/llvm-project/lldb/source/Plugins/Process/Utility/
H A DRegisterInfos_ppc64.h112 DEFINE_FPR_PPC64(f16, NULL, LLDB_INVALID_REGNUM), \
258 uint64_t f16; member in struct:_FPR_PPC64
H A DRegisterContextFreeBSD_powerpc.cpp114 uint64_t f16; member in struct:_FPR
H A DRegisterContext_mips.h303 uint64_t f16; member in struct:FPR_linux_mips
H A DRegisterInfos_ppc64le.h123 DEFINE_FPR(f16, NULL, LLDB_INVALID_REGNUM), \
336 uint64_t f16; member in struct:_FPR
H A DRegisterInfos_powerpc.h102 DEFINE_FPR(f16, LLDB_INVALID_REGNUM), \
H A DRegisterInfos_mips.h179 DEFINE_FPR(f16, nullptr, dwarf_f16_mips, dwarf_f16_mips,
/freebsd-12-stable/contrib/llvm-project/compiler-rt/lib/tsan/rtl/
H A Dtsan_rtl_ppc64.S70 stfd f16,192(r3)
215 stfd f16,192(r3)
/freebsd-12-stable/contrib/llvm-project/llvm/lib/Target/AMDGPU/
H A DSIISelLowering.cpp152 addRegisterClass(MVT::f16, &AMDGPU::SReg_32RegClass);
373 setOperationAction(ISD::FPOW, MVT::f16, Promote);
374 setOperationAction(ISD::FLOG, MVT::f16, Custom);
375 setOperationAction(ISD::FEXP, MVT::f16, Custom);
376 setOperationAction(ISD::FLOG10, MVT::f16, Custom);
492 setOperationAction(ISD::ConstantFP, MVT::f16, Legal);
495 setOperationAction(ISD::LOAD, MVT::f16, Promote);
496 AddPromotedToType(ISD::LOAD, MVT::f16, MVT::i16);
497 setOperationAction(ISD::STORE, MVT::f16, Promote);
498 AddPromotedToType(ISD::STORE, MVT::f16, MV
[all...]
H A DAMDGPUISelLowering.cpp152 setLoadExtAction(ISD::EXTLOAD, MVT::f32, MVT::f16, Expand);
165 setLoadExtAction(ISD::EXTLOAD, MVT::f64, MVT::f16, Expand);
216 setTruncStoreAction(MVT::f32, MVT::f16, Expand);
224 setTruncStoreAction(MVT::f64, MVT::f16, Expand);
626 (ScalarVT == MVT::f16 && Subtarget->has16BitInsts()));
745 (Subtarget->has16BitInsts() && VT == MVT::f16);
751 (Subtarget->has16BitInsts() && VT == MVT::f16) ||
2512 if (DestVT == MVT::f16)
2523 if (Subtarget->has16BitInsts() && DestVT == MVT::f16) {
2529 DAG.getNode(ISD::FP_ROUND, DL, MVT::f16, IntToFp3
[all...]
/freebsd-12-stable/contrib/llvm-project/libunwind/src/
H A DUnwindRegistersSave.S179 sdc1 $f16, (4 * 36 + 8 * 16)($4)
204 sdc1 $f16, (4 * 36 + 8 * 16)($4)
295 sdc1 $f16, (8 * 51)($4)
628 stfd %f16,288(%r3)
1037 fsd f16, (8 * 32 + 8 * 16)(a0)
/freebsd-12-stable/contrib/gcc/config/rs6000/
H A Ddarwin-world.asm95 stfd f16,-128(r1)
249 lfd f16,-128(r11)
/freebsd-12-stable/crypto/openssl/crypto/perlasm/
H A Dsparcv9_modes.pl687 aes_eround01 %f16, %f14, %f2, %f4
691 camellia_f %f16, %f2, %f14, %f2
768 aes_eround01 %f16, %f14, %f2, %f8
770 aes_eround01 %f16, %f14, %f6, %f10
774 camellia_f %f16, %f2, %f14, %f2
775 camellia_f %f16, %f6, %f14, %f6
873 aes_eround01 %f16, %f14, %f2, %f8
875 aes_eround01 %f16, %f14, %f6, %f10
879 camellia_f %f16, %f2, %f14, %f2
880 camellia_f %f16,
[all...]
/freebsd-12-stable/contrib/llvm-project/llvm/lib/CodeGen/
H A DTargetLoweringBase.cpp163 // For f16/f32 conversions, Darwin uses the standard naming scheme, instead
221 if (OpVT == MVT::f16) {
247 if (RetVT == MVT::f16) {
736 setOperationAction(ISD::ConstantFP, MVT::f16, Expand);
1227 // Decide how to handle f16. If the target does not have native f16 support,
1228 // promote it to f32, because there are no f16 library calls (except for
1230 if (!isTypeLegal(MVT::f16)) {
1231 NumRegistersForVT[MVT::f16] = NumRegistersForVT[MVT::f32];
1232 RegisterTypeForVT[MVT::f16]
[all...]
H A DValueTypes.cpp152 case MVT::f16: return Type::getHalfTy(Context);
333 case Type::HalfTyID: return MVT(MVT::f16);
/freebsd-12-stable/sys/sparc64/sparc64/
H A Dswtch.S338 stda %f16, [%o0 + (1 * 64)] %asi
/freebsd-12-stable/contrib/llvm-project/llvm/lib/Target/ARM/
H A DARMCallingConv.cpp213 case MVT::f16:
/freebsd-12-stable/crypto/openssl/crypto/
H A Dia64cpuid.S119 { .mfi; mov f16=f0 }
/freebsd-12-stable/sys/mips/mips/
H A Dfp.S2320 mfc1 t2, $f16
2418 mfc1 ta0, $f16
2516 mfc1 t0, $f16
2628 mfc1 ta3, $f16
2743 mfc1 t3, $f16
2853 mfc1 t0, $f16
2931 mfc1 ta0, $f16
3039 mfc1 t3, $f16
3133 mfc1 ta3, $f16
3250 mtc1 t2, $f16
[all...]
/freebsd-12-stable/crypto/openssl/crypto/poly1305/asm/
H A Dpoly1305-ppcfp.pl240 stfd f16,`$FRAME-8*16`($sp)
522 lfd f16,`$FRAME-8*16`($sp)

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