Lines Matching refs:f16
204 // Vectors with an even number of f16 elements will be passed to
207 if (EltVT == MVT::f16 && NumElts % 2 == 0) {
382 addRegisterClass(MVT::f16, &NVPTX::Float16RegsRegClass);
386 setOperationAction(ISD::SINT_TO_FP, MVT::f16, Legal);
387 setOperationAction(ISD::FP_TO_SINT, MVT::f16, Legal);
393 setFP16OperationAction(ISD::SETCC, MVT::f16, Legal, Promote);
397 for (MVT VT : {MVT::f16, MVT::v2f16, MVT::f32, MVT::f64, MVT::i1, MVT::i8,
450 setLoadExtAction(ISD::EXTLOAD, MVT::f32, MVT::f16, Expand);
451 setLoadExtAction(ISD::EXTLOAD, MVT::f64, MVT::f16, Expand);
461 setTruncStoreAction(MVT::f32, MVT::f16, Expand);
462 setTruncStoreAction(MVT::f64, MVT::f16, Expand);
478 setOperationAction(ISD::ConstantFP, MVT::f16, Legal);
538 setFP16OperationAction(Op, MVT::f16, Legal, Promote);
542 // There's no neg.f16 instruction. Expand to (0-x).
543 setOperationAction(ISD::FNEG, MVT::f16, Expand);
551 setOperationAction(Op, MVT::f16, Legal);
557 setOperationAction(ISD::FROUND, MVT::f16, Promote);
564 setOperationAction(ISD::FCOPYSIGN, MVT::f16, Expand);
569 // These map to corresponding instructions for f32/f64. f16 must be
570 // promoted to f32. v2f16 is expanded to f16, which is then promoted
574 setOperationAction(Op, MVT::f16, Promote);
579 setOperationAction(ISD::FMINNUM, MVT::f16, Promote);
580 setOperationAction(ISD::FMAXNUM, MVT::f16, Promote);
581 setOperationAction(ISD::FMINIMUM, MVT::f16, Promote);
582 setOperationAction(ISD::FMAXIMUM, MVT::f16, Promote);
2357 // v8f16 is a special case. PTX doesn't have st.v8.f16
2360 assert(EltVT == MVT::f16 && "Wrong type for the vector.");
2372 // Combine f16,f16 -> v2f16
2375 SDValue E0 = DAG.getNode(ISD::EXTRACT_VECTOR_ELT, DL, MVT::f16, Val,
2377 SDValue E1 = DAG.getNode(ISD::EXTRACT_VECTOR_ELT, DL, MVT::f16, Val,
4856 // v8f16 is a special case. PTX doesn't have ld.v8.f16
4859 assert(EltVT == MVT::f16 && "Unsupported v8 vector type.");