Lines Matching refs:f16
139 addRegisterClass(MVT::f16, &AArch64::FPR16RegClass);
211 setOperationAction(ISD::SETCC, MVT::f16, Custom);
214 setOperationAction(ISD::STRICT_FSETCC, MVT::f16, Custom);
217 setOperationAction(ISD::STRICT_FSETCCS, MVT::f16, Custom);
225 setOperationAction(ISD::BR_CC, MVT::f16, Custom);
230 setOperationAction(ISD::SELECT, MVT::f16, Custom);
235 setOperationAction(ISD::SELECT_CC, MVT::f16, Custom);
395 setOperationAction(ISD::FCOPYSIGN, MVT::f16, Custom);
397 setOperationAction(ISD::FCOPYSIGN, MVT::f16, Promote);
399 setOperationAction(ISD::FREM, MVT::f16, Promote);
402 setOperationAction(ISD::FPOW, MVT::f16, Promote);
405 setOperationAction(ISD::FPOWI, MVT::f16, Promote);
408 setOperationAction(ISD::FCOS, MVT::f16, Promote);
411 setOperationAction(ISD::FSIN, MVT::f16, Promote);
414 setOperationAction(ISD::FSINCOS, MVT::f16, Promote);
417 setOperationAction(ISD::FEXP, MVT::f16, Promote);
420 setOperationAction(ISD::FEXP2, MVT::f16, Promote);
423 setOperationAction(ISD::FLOG, MVT::f16, Promote);
426 setOperationAction(ISD::FLOG2, MVT::f16, Promote);
429 setOperationAction(ISD::FLOG10, MVT::f16, Promote);
434 setOperationAction(ISD::SELECT, MVT::f16, Promote);
435 setOperationAction(ISD::SELECT_CC, MVT::f16, Promote);
436 setOperationAction(ISD::SETCC, MVT::f16, Promote);
437 setOperationAction(ISD::BR_CC, MVT::f16, Promote);
438 setOperationAction(ISD::FADD, MVT::f16, Promote);
439 setOperationAction(ISD::FSUB, MVT::f16, Promote);
440 setOperationAction(ISD::FMUL, MVT::f16, Promote);
441 setOperationAction(ISD::FDIV, MVT::f16, Promote);
442 setOperationAction(ISD::FMA, MVT::f16, Promote);
443 setOperationAction(ISD::FNEG, MVT::f16, Promote);
444 setOperationAction(ISD::FABS, MVT::f16, Promote);
445 setOperationAction(ISD::FCEIL, MVT::f16, Promote);
446 setOperationAction(ISD::FSQRT, MVT::f16, Promote);
447 setOperationAction(ISD::FFLOOR, MVT::f16, Promote);
448 setOperationAction(ISD::FNEARBYINT, MVT::f16, Promote);
449 setOperationAction(ISD::FRINT, MVT::f16, Promote);
450 setOperationAction(ISD::FROUND, MVT::f16, Promote);
451 setOperationAction(ISD::FTRUNC, MVT::f16, Promote);
452 setOperationAction(ISD::FMINNUM, MVT::f16, Promote);
453 setOperationAction(ISD::FMAXNUM, MVT::f16, Promote);
454 setOperationAction(ISD::FMINIMUM, MVT::f16, Promote);
455 setOperationAction(ISD::FMAXIMUM, MVT::f16, Promote);
524 setOperationAction(ISD::FNEARBYINT, MVT::f16, Legal);
525 setOperationAction(ISD::FFLOOR, MVT::f16, Legal);
526 setOperationAction(ISD::FCEIL, MVT::f16, Legal);
527 setOperationAction(ISD::FRINT, MVT::f16, Legal);
528 setOperationAction(ISD::FTRUNC, MVT::f16, Legal);
529 setOperationAction(ISD::FROUND, MVT::f16, Legal);
530 setOperationAction(ISD::FMINNUM, MVT::f16, Legal);
531 setOperationAction(ISD::FMAXNUM, MVT::f16, Legal);
532 setOperationAction(ISD::FMINIMUM, MVT::f16, Legal);
533 setOperationAction(ISD::FMAXIMUM, MVT::f16, Legal);
581 setLoadExtAction(ISD::EXTLOAD, VT, MVT::f16, Expand);
589 setTruncStoreAction(MVT::f32, MVT::f16, Expand);
591 setTruncStoreAction(MVT::f64, MVT::f16, Expand);
595 setTruncStoreAction(MVT::f128, MVT::f16, Expand);
598 setOperationAction(ISD::BITCAST, MVT::f16, Custom);
609 setIndexedLoadAction(im, MVT::f16, Legal);
616 setIndexedStoreAction(im, MVT::f16, Legal);
751 // Or, direct i32 -> f16 vector conversion. Set it so custom, so the
933 (VT.getVectorElementType() != MVT::f16 || Subtarget->hasFullFP16()))
1700 assert(VT != MVT::f16 && "Lowering of strict fp16 not yet implemented");
1714 if (VT == MVT::f16 && !FullFP16) {
1815 if (LHS.getValueType() == MVT::f16 && !FullFP16) {
2559 // f16 conversions are promoted to f32 when full fp16 is not supported.
2560 if (InVT.getVectorElementType() == MVT::f16 &&
2598 // f16 conversions are promoted to f32 when full fp16 is not supported.
2599 if (SrcVal.getValueType() == MVT::f16 && !Subtarget->hasFullFP16()) {
2658 // f16 conversions are promoted to f32 when full fp16 is not supported.
2659 if (Op.getValueType() == MVT::f16 &&
2664 ISD::FP_ROUND, dl, MVT::f16,
2723 if (Op.getValueType() != MVT::f16)
2732 DAG.getMachineNode(TargetOpcode::EXTRACT_SUBREG, DL, MVT::f16, Op,
3407 else if (RegVT == MVT::f16)
5061 assert(LHS.getValueType() == MVT::f16 || LHS.getValueType() == MVT::f32 ||
5124 } else if (VT == MVT::f16 || VT == MVT::v4f16 || VT == MVT::v8f16) {
5145 if (VT == MVT::f16)
5261 assert(LHS.getValueType() == MVT::f16 || LHS.getValueType() == MVT::f32 ||
5318 // Also handle f16, for which we need to do a f32 comparison.
5319 if (LHS.getValueType() == MVT::f16 && !Subtarget->hasFullFP16()) {
5445 assert(LHS.getValueType() == MVT::f16 || LHS.getValueType() == MVT::f32 ||
6004 else if (VT == MVT::f16 && Subtarget->hasFullFP16())
7079 VT.getVectorElementType() == MVT::f16)
7092 else if (EltTy == MVT::i16 || EltTy == MVT::f16)
7199 if (EltType == MVT::i16 || EltType == MVT::f16)
7429 case MVT::f16:
8044 assert ((EltTy == MVT::f16 || EltTy == MVT::f32 || EltTy == MVT::f64) &&
8492 if (!FullFP16 && LHS.getValueType().getVectorElementType() == MVT::f16) {
8503 assert((!FullFP16 && LHS.getValueType().getVectorElementType() != MVT::f16) ||
12802 if (N->getValueType(0) != MVT::i16 || Op.getValueType() != MVT::f16)