Lines Matching refs:f16
152 addRegisterClass(MVT::f16, &AMDGPU::SReg_32RegClass);
373 setOperationAction(ISD::FPOW, MVT::f16, Promote);
374 setOperationAction(ISD::FLOG, MVT::f16, Custom);
375 setOperationAction(ISD::FEXP, MVT::f16, Custom);
376 setOperationAction(ISD::FLOG10, MVT::f16, Custom);
492 setOperationAction(ISD::ConstantFP, MVT::f16, Legal);
495 setOperationAction(ISD::LOAD, MVT::f16, Promote);
496 AddPromotedToType(ISD::LOAD, MVT::f16, MVT::i16);
497 setOperationAction(ISD::STORE, MVT::f16, Promote);
498 AddPromotedToType(ISD::STORE, MVT::f16, MVT::i16);
501 setOperationAction(ISD::FP_ROUND, MVT::f16, Custom);
502 setOperationAction(ISD::FCOS, MVT::f16, Promote);
503 setOperationAction(ISD::FSIN, MVT::f16, Promote);
508 setOperationAction(ISD::FP_TO_SINT, MVT::f16, Promote);
509 setOperationAction(ISD::FP_TO_UINT, MVT::f16, Promote);
510 setOperationAction(ISD::SINT_TO_FP, MVT::f16, Promote);
511 setOperationAction(ISD::UINT_TO_FP, MVT::f16, Promote);
512 setOperationAction(ISD::FROUND, MVT::f16, Custom);
515 setOperationAction(ISD::BR_CC, MVT::f16, Expand);
516 setOperationAction(ISD::SELECT_CC, MVT::f16, Expand);
518 setOperationAction(ISD::FDIV, MVT::f16, Custom);
521 setOperationAction(ISD::FMA, MVT::f16, Legal);
523 setOperationAction(ISD::FMAD, MVT::f16, Legal);
601 setOperationAction(ISD::FMAXNUM, MVT::f16, Custom);
602 setOperationAction(ISD::FMINNUM, MVT::f16, Custom);
603 setOperationAction(ISD::FMAXNUM_IEEE, MVT::f16, Legal);
604 setOperationAction(ISD::FMINNUM_IEEE, MVT::f16, Legal);
693 setOperationAction(ISD::INTRINSIC_WO_CHAIN, MVT::f16, Custom);
703 setOperationAction(ISD::INTRINSIC_W_CHAIN, MVT::f16, Custom);
712 setOperationAction(ISD::INTRINSIC_VOID, MVT::f16, Custom);
776 // v_mad_mix* support a conversion from f16 to f32.
785 SrcVT.getScalarType() == MVT::f16 &&
3940 case MVT::f16:
3956 if (VT == MVT::f16) {
4255 if (CmpVT == MVT::f16 && !TLI.isTypeLegal(CmpVT)) {
4590 assert(Op.getValueType() == MVT::f16 &&
4591 "Do not know how to custom lower FP_ROUND for non-f16 type");
4602 return DAG.getNode(ISD::BITCAST, DL, MVT::f16, Trunc);
4913 if (ResultVT == MVT::f16) {
5392 if (StoreVT.getScalarType() == MVT::f16) {
5405 if (LoadVT.getScalarType() == MVT::f16) {
5463 if (((VAddrScalarVT == MVT::f16) || (VAddrScalarVT == MVT::i16)) &&
5466 const MVT VectorVT = VAddrScalarVT == MVT::f16 ? MVT::v2f16 : MVT::v2i16;
5480 AddrHi = DAG.getUNDEF(MVT::f16);
5929 S, // Src2 - holds two f16 values selected by high
6294 if (LoadVT.getScalarType() == MVT::f16)
6370 if (LoadVT.getScalarType() == MVT::f16)
6394 if (LoadVT.getScalarType() == MVT::f16)
6418 if (LoadVT.getScalarType() == MVT::f16)
6765 // No change for f16 and legal vector D16 types.
6854 bool IsD16 = (VData.getValueType().getScalarType() == MVT::f16);
6885 bool IsD16 = (VData.getValueType().getScalarType() == MVT::f16);
6910 bool IsD16 = (VData.getValueType().getScalarType() == MVT::f16);
6936 bool IsD16 = (VData.getValueType().getScalarType() == MVT::f16);
7242 if (VDataType == MVT::f16)
7556 if (Unsafe || VT == MVT::f32 || VT == MVT::f16) {
7651 SDValue BestQuot = DAG.getNode(ISD::FP_ROUND, SL, MVT::f16, Quot, FPRoundFlag);
7653 return DAG.getNode(AMDGPUISD::DIV_FIXUP, SL, MVT::f16, BestQuot, Src1, Src0);
7883 if (VT == MVT::f16)
8658 // (i32 zext (i16 (bitcast f16:$src))) -> fp16_zext $src
8662 if (BCSrc.getValueType() == MVT::f16 &&
8804 return Op.getValueType().getScalarType() != MVT::f16;
9119 // med3 for f16 is only available on gfx9+, and not available for v2f16.
9120 if (VT == MVT::f32 || (VT == MVT::f16 && Subtarget->hasMed3_16())) {
9158 ((VT == MVT::f16 || VT == MVT::i16) && Subtarget->hasMin3Max3_16()))) {
9202 (VT == MVT::f16 && Subtarget->has16BitInsts()) ||
9442 (VT == MVT::f16 && !hasFP64FP16Denormals(DAG.getMachineFunction()) &&
9884 VT != MVT::f16))
10096 if (EltVT == MVT::f16)
10681 // We actually support i128, i16 and f16 as inline parameters
10684 VT.SimpleTy == MVT::i16 || VT.SimpleTy == MVT::f16))
10936 case MVT::f16: