Searched refs:SELECT (Results 26 - 50 of 59) sorted by relevance

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/freebsd-11-stable/contrib/llvm-project/llvm/lib/Target/Lanai/
H A DLanaiISelLowering.cpp89 setOperationAction(ISD::SELECT, MVT::i32, Expand);
1353 case ISD::SELECT: {
1438 return DAG.getNode(ISD::SELECT, SDLoc(N), VT, CCOp, TrueVal, FalseVal);
/freebsd-11-stable/contrib/llvm-project/llvm/lib/Target/Hexagon/
H A DHexagonISelLoweringHVX.cpp911 return DAG.getNode(ISD::SELECT, dl, VecTy, PickHi, InHi, InLo);
917 IdxV = DAG.getNode(ISD::SELECT, dl, MVT::i32, PickHi, S, IdxV);
918 SingleV = DAG.getNode(ISD::SELECT, dl, SingleTy, PickHi, V1, V0);
958 return DAG.getNode(ISD::SELECT, dl, VecTy, PickHi, InHi, InLo);
H A DHexagonISelLowering.cpp1510 // Normalize all inputs to SELECT to be vectors of i32.
1513 setOperationAction(ISD::SELECT, VT, Promote);
1514 AddPromotedToType(ISD::SELECT, VT, VT32);
/freebsd-11-stable/contrib/llvm-project/llvm/lib/Target/PowerPC/
H A DPPCISelLowering.cpp371 setOperationAction(ISD::SELECT, MVT::i32, Expand);
372 setOperationAction(ISD::SELECT, MVT::i64, Expand);
373 setOperationAction(ISD::SELECT, MVT::f32, Expand);
374 setOperationAction(ISD::SELECT, MVT::f64, Expand);
643 setOperationAction(ISD::SELECT, VT, Promote);
644 AddPromotedToType (ISD::SELECT, VT, MVT::v4i32);
724 setOperationAction(ISD::SELECT, MVT::v4i32,
953 setOperationAction(ISD::SELECT, MVT::f128, Expand);
1003 setOperationAction(ISD::SELECT, MVT::v4f64, Expand);
1051 setOperationAction(ISD::SELECT, MV
[all...]
/freebsd-11-stable/contrib/llvm-project/llvm/lib/Target/AMDGPU/
H A DSIISelLowering.cpp209 setOperationAction(ISD::SELECT, MVT::i1, Promote);
210 setOperationAction(ISD::SELECT, MVT::i64, Custom);
211 setOperationAction(ISD::SELECT, MVT::f64, Promote);
212 AddPromotedToType(ISD::SELECT, MVT::f64, MVT::i64);
664 setOperationAction(ISD::SELECT, MVT::v4i16, Custom);
665 setOperationAction(ISD::SELECT, MVT::v4f16, Custom);
672 setOperationAction(ISD::SELECT, MVT::v2i16, Promote);
673 AddPromotedToType(ISD::SELECT, MVT::v2i16, MVT::i32);
674 setOperationAction(ISD::SELECT, MVT::v2f16, Promote);
675 AddPromotedToType(ISD::SELECT, MV
[all...]
H A DR600ISelLowering.cpp171 setOperationAction(ISD::SELECT, MVT::i32, Expand);
172 setOperationAction(ISD::SELECT, MVT::f32, Expand);
173 setOperationAction(ISD::SELECT, MVT::v2i32, Expand);
174 setOperationAction(ISD::SELECT, MVT::v4i32, Expand);
/freebsd-11-stable/contrib/llvm-project/llvm/lib/Target/Mips/
H A DMipsSEISelLowering.cpp131 setOperationAction(ISD::SELECT, MVT::f16, Promote);
248 setOperationAction(ISD::SELECT, MVT::i32, Legal);
252 setOperationAction(ISD::SELECT, MVT::f32, Legal);
257 setOperationAction(ISD::SELECT, MVT::f64, Custom);
295 setOperationAction(ISD::SELECT, MVT::i64, Legal);
468 case ISD::SELECT: return lowerSELECT(Op, DAG);
/freebsd-11-stable/contrib/llvm-project/llvm/lib/Target/BPF/
H A DBPFISelLowering.cpp102 setOperationAction(ISD::SELECT, VT, Expand);
648 // To "insert" a SELECT instruction, we actually have to insert the diamond
/freebsd-11-stable/contrib/llvm-project/llvm/lib/CodeGen/SelectionDAG/
H A DSelectionDAGDumper.cpp277 case ISD::SELECT: return "select";
H A DLegalizeFloatTypes.cpp126 case ISD::SELECT: R = SoftenFloatRes_SELECT(N); break;
1118 case ISD::SELECT: SplitRes_SELECT(N, Lo, Hi); break;
2144 case ISD::SELECT: R = PromoteFloatRes_SELECT(N); break;
2346 // Construct a new SELECT node with the promoted true- and false- values.
2351 return DAG.getNode(ISD::SELECT, SDLoc(N), TrueVal->getValueType(0),
H A DDAGCombiner.cpp505 bool SimplifySelectOps(SDNode *SELECT, SDValue LHS, SDValue RHS);
1561 case ISD::SELECT: return visitSELECT(N);
1940 if (Sel.getOpcode() != ISD::SELECT || !Sel.hasOneUse()) {
1945 if (Sel.getOpcode() != ISD::SELECT || !Sel.hasOneUse())
7353 BinOpLHSVal.getOpcode() == ISD::SELECT;
8569 DAG.getNode(ISD::SELECT, DL, N1.getValueType(), Cond1, N1, N2, Flags);
8571 return DAG.getNode(ISD::SELECT, DL, N1.getValueType(), Cond0,
8581 SDValue InnerSelect = DAG.getNode(ISD::SELECT, DL, N1.getValueType(),
8584 return DAG.getNode(ISD::SELECT, DL, N1.getValueType(), Cond0, N1,
8592 if (N1->getOpcode() == ISD::SELECT
[all...]
H A DLegalizeVectorOps.cpp400 case ISD::SELECT:
866 case ISD::SELECT:
H A DLegalizeVectorTypes.cpp61 case ISD::SELECT: R = ScalarizeVecRes_SELECT(N); break;
701 /// <1 x i1>, so just convert to a normal ISD::SELECT
707 return DAG.getNode(ISD::SELECT, SDLoc(N), VT, ScalarCond, N->getOperand(1),
827 case ISD::SELECT: SplitRes_SELECT(N, Lo, Hi); break;
2697 case ISD::SELECT: Res = WidenVecRes_SELECT(N); break;
H A DLegalizeIntegerTypes.cpp75 case ISD::SELECT: Res = PromoteIntRes_SELECT(N); break;
1279 case ISD::SELECT: Res = PromoteIntOp_SELECT(N, OpNo); break;
1536 EVT OpVT = N->getOpcode() == ISD::SELECT ? OpTy.getScalarType() : OpTy;
1804 case ISD::SELECT: SplitRes_SELECT(N, Lo, Hi); break;
3871 // NOTE: on targets without efficient SELECT of bools, we can always use
H A DLegalizeDAG.cpp3518 case ISD::SELECT:
3674 // node using SETCC and SELECT.
3676 assert(!TLI.isOperationExpand(ISD::SELECT, VT) &&
3677 "Cannot expand ISD::SELECT_CC when ISD::SELECT also needs to be "
4378 case ISD::SELECT: {
/freebsd-11-stable/contrib/llvm-project/llvm/lib/Target/Sparc/
H A DSparcISelLowering.cpp1524 setOperationAction(ISD::SELECT, MVT::i32, Expand);
1525 setOperationAction(ISD::SELECT, MVT::f32, Expand);
1526 setOperationAction(ISD::SELECT, MVT::f64, Expand);
1527 setOperationAction(ISD::SELECT, MVT::f128, Expand);
1560 setOperationAction(ISD::SELECT, MVT::i64, Expand);
/freebsd-11-stable/contrib/llvm-project/llvm/lib/Target/AArch64/
H A DAArch64ISelLowering.cpp228 setOperationAction(ISD::SELECT, MVT::i32, Custom);
229 setOperationAction(ISD::SELECT, MVT::i64, Custom);
230 setOperationAction(ISD::SELECT, MVT::f16, Custom);
231 setOperationAction(ISD::SELECT, MVT::f32, Custom);
232 setOperationAction(ISD::SELECT, MVT::f64, Custom);
278 setOperationAction(ISD::SELECT, MVT::f128, Custom);
434 setOperationAction(ISD::SELECT, MVT::f16, Promote);
473 setOperationAction(ISD::SELECT, MVT::v4f16, Expand);
500 setOperationAction(ISD::SELECT, MVT::v8f16, Expand);
655 setTargetDAGCombine(ISD::SELECT);
[all...]
/freebsd-11-stable/contrib/llvm-project/llvm/lib/Target/MSP430/
H A DMSP430ISelLowering.cpp95 setOperationAction(ISD::SELECT, MVT::i8, Expand);
96 setOperationAction(ISD::SELECT, MVT::i16, Expand);
1572 // To "insert" a SELECT instruction, we actually have to insert the diamond
/freebsd-11-stable/contrib/llvm-project/llvm/lib/Target/AVR/
H A DAVRISelLowering.cpp110 setOperationAction(ISD::SELECT, MVT::i8, Expand);
111 setOperationAction(ISD::SELECT, MVT::i16, Expand);
1628 // To "insert" a SELECT instruction, we insert the diamond
/freebsd-11-stable/sys/cam/scsi/
H A Dscsi_ses.h182 GEN_SES_CTRL_COMMON_ACCESSORS(select, SELECT)
/freebsd-11-stable/contrib/llvm-project/llvm/include/llvm/CodeGen/
H A DBasicTTIImpl.h843 if (ISD == ISD::SELECT) {
H A DSelectionDAG.h1019 auto Opcode = Cond.getValueType().isVector() ? ISD::VSELECT : ISD::SELECT;
/freebsd-11-stable/contrib/llvm-project/llvm/lib/Target/X86/
H A DX86ISelLowering.cpp406 setOperationAction(ISD::SELECT, VT, Custom);
414 setOperationAction(ISD::SELECT, VT, Custom);
418 // Custom action for SELECT MMX and expand action for SELECT_CC MMX
419 setOperationAction(ISD::SELECT, MVT::x86mmx, Custom);
849 setOperationAction(ISD::SELECT, MVT::v4f32, Custom);
960 setOperationAction(ISD::SELECT, MVT::v2f64, Custom);
961 setOperationAction(ISD::SELECT, MVT::v2i64, Custom);
962 setOperationAction(ISD::SELECT, MVT::v4i32, Custom);
963 setOperationAction(ISD::SELECT, MVT::v8i16, Custom);
964 setOperationAction(ISD::SELECT, MV
[all...]
/freebsd-11-stable/contrib/llvm-project/llvm/lib/CodeGen/
H A DTargetLoweringBase.cpp1637 case Select: return ISD::SELECT;
/freebsd-11-stable/contrib/llvm-project/llvm/lib/Target/WebAssembly/
H A DWebAssemblyISelLowering.cpp167 for (auto Op : {ISD::VSELECT, ISD::SELECT_CC, ISD::SELECT}) {

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