/freebsd-11-stable/contrib/llvm-project/llvm/lib/CodeGen/ |
H A D | LLVMTargetMachine.cpp | 42 MRI.reset(TheTarget.createMCRegInfo(getTargetTriple().str())); 52 *MRI, getTargetTriple().str(), Options.MCOptions); 126 const MCRegisterInfo &MRI = *getMCRegisterInfo(); local 134 getTargetTriple(), MAI.getAssemblerDialect(), MAI, MII, MRI); 139 MCE.reset(getTarget().createMCCodeEmitter(MII, MRI, Context)); 142 getTarget().createMCAsmBackend(STI, MRI, Options.MCOptions)); 154 MCCodeEmitter *MCE = getTarget().createMCCodeEmitter(MII, MRI, Context); 156 getTarget().createMCAsmBackend(STI, MRI, Options.MCOptions); 245 const MCRegisterInfo &MRI = *getMCRegisterInfo(); local 247 getTarget().createMCCodeEmitter(*getMCInstrInfo(), MRI, *Ct [all...] |
H A D | DetectDeadLanes.cpp | 109 const MachineRegisterInfo *MRI; member in class:__anon1705::DetectDeadLanes 152 static bool isCrossCopy(const MachineRegisterInfo &MRI, argument 158 const TargetRegisterClass *SrcRC = MRI.getRegClass(SrcReg); 164 const TargetRegisterInfo &TRI = *MRI.getTargetRegisterInfo(); 204 UsedLanes &= MRI->getMaxLaneMaskForVReg(MOReg); 254 const TargetRegisterClass *RC = MRI->getRegClass(DefReg); 348 DefinedLanes &= MRI->getMaxLaneMaskForVReg(Def.getReg()); 355 if (!MRI->hasOneDef(Reg)) 358 const MachineOperand &Def = *MRI->def_begin(Reg); 373 const TargetRegisterClass *DefRC = MRI [all...] |
H A D | LivePhysRegs.cpp | 139 bool LivePhysRegs::available(const MachineRegisterInfo &MRI, argument 143 if (MRI.isReserved(Reg)) 174 const MachineRegisterInfo &MRI = MF.getRegInfo(); local 175 for (const MCPhysReg *CSR = MRI.getCalleeSavedRegs(); CSR && *CSR; ++CSR) 245 const MachineRegisterInfo &MRI = MF.getRegInfo(); local 246 const TargetRegisterInfo &TRI = *MRI.getTargetRegisterInfo(); 256 const MachineRegisterInfo &MRI = MF.getRegInfo(); local 257 const TargetRegisterInfo &TRI = *MRI.getTargetRegisterInfo(); 259 if (MRI.isReserved(Reg)) 264 if (LiveRegs.contains(*SReg) && !MRI 277 const MachineRegisterInfo &MRI = MF.getRegInfo(); local [all...] |
H A D | ModuloSchedule.cpp | 85 for (MachineRegisterInfo::use_iterator UI = MRI.use_begin(Reg), 86 EI = MRI.use_end(); 336 MachineRegisterInfo &MRI, 338 for (MachineRegisterInfo::use_iterator I = MRI.use_begin(FromReg), 339 E = MRI.use_end(); 353 MachineRegisterInfo &MRI) { 354 for (MachineRegisterInfo::use_iterator I = MRI.use_begin(Reg), 355 E = MRI.use_end(); 400 int LoopValStage = Schedule.getStage(MRI.getVRegDef(LoopVal)); 451 MachineInstr *InstOp1 = MRI 334 replaceRegUsesAfterLoop(unsigned FromReg, unsigned ToReg, MachineBasicBlock *MBB, MachineRegisterInfo &MRI, LiveIntervals &LIS) argument 352 hasUseAfterLoop(unsigned Reg, MachineBasicBlock *BB, MachineRegisterInfo &MRI) argument 924 MachineRegisterInfo &MRI = MF.getRegInfo(); local 1217 EliminateDeadPhis(MachineBasicBlock *MBB, MachineRegisterInfo &MRI, LiveIntervals *LIS, bool KeepSingleSrcPhi = false) argument 1250 MachineRegisterInfo &MRI; member in class:__anon1776::KernelRewriter 1519 MachineRegisterInfo &MRI; member in class:__anon1777::KernelOperandInfo 1525 KernelOperandInfo(MachineOperand *MO, MachineRegisterInfo &MRI, const SmallPtrSetImpl<MachineInstr *> &IllegalPhis) argument [all...] |
H A D | PeepholeOptimizer.cpp | 157 MachineRegisterInfo *MRI; member in class:__anon1782::PeepholeOptimizer 379 const MachineRegisterInfo &MRI; 419 const MachineRegisterInfo &MRI, 421 : DefSubReg(DefSubReg), Reg(Reg), MRI(MRI), TII(TII) { 423 Def = MRI.getVRegDef(Reg); 424 DefIdx = MRI.def_begin(Reg).getOperandNo(); 468 if (MRI->hasOneNonDBGUse(SrcReg)) 474 const TargetRegisterClass *DstRC = MRI->getRegClass(DstReg); 485 TRI->getSubClassWithSubReg(MRI 756 insertPHI(MachineRegisterInfo &MRI, const TargetInstrInfo &TII, const SmallVectorImpl<RegSubRegPair> &SrcRegs, MachineInstr &OrigPHI) argument 1112 getNewSource(MachineRegisterInfo *MRI, const TargetInstrInfo *TII, RegSubRegPair Def, const PeepholeOptimizer::RewriteMapTy &RewriteMap, bool HandleMultipleSources = true) argument [all...] |
H A D | DeadMachineInstructionElim.cpp | 34 const MachineRegisterInfo *MRI; member in class:__anon1704::DeadMachineInstructionElim 82 if (LivePhysRegs.test(Reg) || MRI->isReserved(Reg)) 89 for (auto &U : MRI->use_nodbg_operands(Reg)) 94 for (const MachineInstr &Use : MRI->use_nodbg_instructions(Reg)) { 112 MRI = &MF.getRegInfo(); 121 LivePhysRegs = MRI->getReservedRegs();
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/freebsd-11-stable/contrib/llvm-project/llvm/lib/CodeGen/GlobalISel/ |
H A D | Localizer.cpp | 39 MRI = &MF.getRegInfo(); 67 auto UI = MRI->use_instr_nodbg_begin(Reg), UE = MRI->use_instr_nodbg_end(); 133 for (auto MOIt = MRI->use_begin(Reg), MOItEnd = MRI->use_end(); 152 if (MRI->hasOneUse(Reg) && !UseMI.isPHI()) 159 Register NewReg = MRI->createGenericVirtualRegister(MRI->getType(Reg)); 160 MRI->setRegClassOrRegBank(NewReg, MRI [all...] |
H A D | GISelKnownBits.cpp | 33 : MF(MF), MRI(MF.getRegInfo()), TL(*MF.getSubtarget().getTargetLowering()), 54 const MachineInstr &MI = *MRI.getVRegDef(R); 71 LLT Ty = MRI.getType(R); 79 LLT Ty = MRI.getType(R); 93 MachineInstr &MI = *MRI.getVRegDef(R); 95 LLT DstTy = MRI.getType(R); 122 TL.computeKnownBitsForTargetInstr(*this, R, Known, DemandedElts, MRI, 136 MRI.getType(Src.getReg()).isValid()) { 143 auto CstVal = getConstantVRegVal(R, MRI); 184 LLT Ty = MRI [all...] |
/freebsd-11-stable/contrib/llvm-project/llvm/lib/Target/ARM/ |
H A D | A15SDOptimizer.cpp | 59 MachineRegisterInfo *MRI; member in struct:__anon2142::A15SDOptimizer 139 return MRI->getRegClass(Reg)->hasSuperClassEq(TRC); 157 MachineInstr *MI = MRI->getVRegDef(SReg); 220 for (MachineInstr &Use : MRI->use_instructions(Reg)) { 251 MachineInstr *DPRMI = MRI->getVRegDef(MI->getOperand(1).getReg()); 252 MachineInstr *SPRMI = MRI->getVRegDef(MI->getOperand(2).getReg()); 271 MRI->getRegClass(MI->getOperand(1).getReg()); 272 if (TRC->hasSuperClassEq(MRI->getRegClass(FullReg))) { 303 MachineInstr *Def = MRI->getVRegDef(OpReg); 346 MachineInstr *Def = MRI [all...] |
H A D | ARMRegisterBankInfo.cpp | 226 const MachineRegisterInfo &MRI = MF.getRegInfo(); local 235 LLT Ty = MRI.getType(MI.getOperand(0).getReg()); 270 LLT LargeTy = MRI.getType(MI.getOperand(1).getReg()); 280 LLT Ty = MRI.getType(MI.getOperand(0).getReg()); 293 LLT Ty = MRI.getType(MI.getOperand(0).getReg()); 300 LLT Ty = MRI.getType(MI.getOperand(0).getReg()); 314 LLT ToTy = MRI.getType(MI.getOperand(0).getReg()); 315 LLT FromTy = MRI.getType(MI.getOperand(1).getReg()); 323 LLT ToTy = MRI.getType(MI.getOperand(0).getReg()); 324 LLT FromTy = MRI [all...] |
H A D | ARMLegalizerInfo.h | 31 bool legalizeCustom(MachineInstr &MI, MachineRegisterInfo &MRI,
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/freebsd-11-stable/contrib/llvm-project/llvm/lib/Target/AMDGPU/ |
H A D | SIInstrInfo.cpp | 482 const MachineRegisterInfo &MRI = local 488 ? MRI.getRegClass(Reg) 762 MachineRegisterInfo &MRI = MBB.getParent()->getRegInfo(); local 763 const TargetRegisterClass *RegClass = MRI.getRegClass(DestReg); 825 MachineRegisterInfo &MRI = MBB.getParent()->getRegInfo(); local 830 assert(MRI.getRegClass(DstReg) == &AMDGPU::VGPR_32RegClass && 834 Register SReg = MRI.createVirtualRegister(BoolXExecRC); 847 Register SReg = MRI.createVirtualRegister(BoolXExecRC); 861 Register SReg = MRI.createVirtualRegister(BoolXExecRC); 877 Register SReg = MRI 951 MachineRegisterInfo &MRI = MBB->getParent()->getRegInfo(); local 964 MachineRegisterInfo &MRI = MBB->getParent()->getRegInfo(); local 1081 MachineRegisterInfo &MRI = MF->getRegInfo(); local 1105 MachineRegisterInfo &MRI = MF->getRegInfo(); local 1207 MachineRegisterInfo &MRI = MF->getRegInfo(); local 1225 MachineRegisterInfo &MRI = MF->getRegInfo(); local 1579 MachineRegisterInfo &MRI = MF->getRegInfo(); local 1787 MachineRegisterInfo &MRI = MF->getRegInfo(); local 2134 const MachineRegisterInfo &MRI = MBB.getParent()->getRegInfo(); local 2148 const MachineRegisterInfo &MRI = MBB.getParent()->getRegInfo(); local 2176 MachineRegisterInfo &MRI = MBB.getParent()->getRegInfo(); local [all...] |
H A D | SIOptimizeExecMaskingPreRA.cpp | 40 MachineRegisterInfo *MRI; member in class:__anon2128::SIOptimizeExecMaskingPreRA 123 const MachineRegisterInfo &MRI, 128 auto SaveExecInst = MRI.getUniqueVRegDef(SavedExec); 138 if (TII->mayReadEXEC(*MRI, *I)) 191 MachineRegisterInfo &MRI, 209 *I, MRI, LIS); 225 auto *Cmp = TRI->findReachingDef(CmpReg, CmpSubReg, *And, MRI, LIS); 239 auto *Sel = TRI->findReachingDef(SelReg, Op1->getSubReg(), *Cmp, MRI, LIS); 271 if ((Register::isVirtualRegister(CmpReg) && MRI.use_nodbg_empty(CmpReg)) || 283 if (Register::isVirtualRegister(SelReg) && MRI 121 getOrExecSource(const MachineInstr &MI, const SIInstrInfo &TII, const MachineRegisterInfo &MRI, const GCNSubtarget& ST) argument 189 optimizeVcndVcmpPair(MachineBasicBlock &MBB, const GCNSubtarget &ST, MachineRegisterInfo &MRI, LiveIntervals *LIS) argument 303 MachineRegisterInfo &MRI = MF.getRegInfo(); local [all...] |
H A D | SIPreAllocateWWMRegs.cpp | 40 MachineRegisterInfo *MRI; member in class:__anon2130::SIPreAllocateWWMRegs 96 if (!TRI->isVGPR(*MRI, Reg)) 107 for (unsigned PhysReg : RegClassInfo.getOrder(MRI->getRegClass(Reg))) { 108 if (!MRI->isPhysRegUsed(PhysReg) && 161 MRI->freezeReservedRegs(MF); 171 MRI = &MF.getRegInfo();
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/freebsd-11-stable/contrib/llvm-project/llvm/lib/Target/BPF/ |
H A D | BPFMIPeephole.cpp | 44 MachineRegisterInfo *MRI; member in struct:__anon2205::BPFMIPeephole 78 MRI = &MF->getRegInfo(); 97 if (MRI->getRegClass(Reg) == &BPF::GPRRegClass) 100 MachineInstr *DefInsn = MRI->getVRegDef(Reg); 115 MachineInstr *PhiDef = MRI->getVRegDef(opnd.getReg()); 154 MachineInstr *DefInsn = MRI->getVRegDef(MovMI->getOperand(1).getReg()); 189 MachineInstr *SllMI = MRI->getVRegDef(ShfReg); 203 MachineInstr *MovMI = MRI->getVRegDef(SllMI->getOperand(1).getReg()); 349 MachineRegisterInfo *MRI; member in struct:__anon2207::BPFMIPeepholeTruncElim 391 MRI [all...] |
/freebsd-11-stable/contrib/llvm-project/llvm/lib/MCA/HardwareUnits/ |
H A D | RegisterFile.cpp | 27 : MRI(mri), 88 const MCRegisterClass &RC = MRI.getRegClass(RCE.RegisterClassID); 96 errs() << "warning: register " << MRI.getName(Reg) 104 for (MCSubRegIterator I(Reg, &MRI); I.isValid(); ++I) { 108 MRI.isSuperRegister(*I, OtherEntry.RenameAs))) { 155 << ", " << MRI.getName(RegID) << "]\n"; 201 for (MCSubRegIterator I(ZeroRegisterID, &MRI); I.isValid(); ++I) 205 for (MCSubRegIterator I(ZeroRegisterID, &MRI); I.isValid(); ++I) 215 for (MCSubRegIterator I(RegID, &MRI); I.isValid(); ++I) { 230 for (MCSuperRegIterator I(RegID, &MRI); [all...] |
/freebsd-11-stable/contrib/llvm-project/llvm/lib/Target/SystemZ/ |
H A D | SystemZRegisterInfo.cpp | 31 const MachineRegisterInfo *MRI) { 32 const TargetRegisterClass *RC = MRI->getRegClass(MO.getReg()); 62 const MachineRegisterInfo *MRI) { 68 RC->contains(Reg) && !MRI->isReserved(Reg)) 72 RC->contains(Reg) && !MRI->isReserved(Reg)) 83 const MachineRegisterInfo *MRI = &MF.getRegInfo(); local 93 for (auto &Use : MRI->reg_nodbg_instructions(VirtReg)) 122 MRI->getRegClass(VirtReg)); 123 if (!MRI->isReserved(PhysReg) && !is_contained(Hints, PhysReg)) 136 if (MRI 29 getRC32(MachineOperand &MO, const VirtRegMap *VRM, const MachineRegisterInfo *MRI) argument 59 addHints(ArrayRef<MCPhysReg> Order, SmallVectorImpl<MCPhysReg> &Hints, const TargetRegisterClass *RC, const MachineRegisterInfo *MRI) argument [all...] |
/freebsd-11-stable/contrib/llvm-project/llvm/lib/Target/WebAssembly/ |
H A D | WebAssemblyExplicitLocals.cpp | 170 MachineRegisterInfo &MRI, 174 MachineInstr *Def = MRI.getVRegDef(Reg); 180 return findStartOfTree(DefMO, MRI, MFI); 197 MachineRegisterInfo &MRI = MF.getRegInfo(); local 223 BitVector UseEmpty(MRI.getNumVirtRegs()); 224 for (unsigned I = 0, E = MRI.getNumVirtRegs(); I < E; ++I) 225 UseEmpty[I] = MRI.use_empty(Register::index2VirtReg(I)); 243 const TargetRegisterClass *RC = MRI.getRegClass(OldReg); 248 Register NewReg = MRI.createVirtualRegister(RC); 278 const TargetRegisterClass *RC = MRI 169 findStartOfTree(MachineOperand &MO, MachineRegisterInfo &MRI, WebAssemblyFunctionInfo &MFI) argument [all...] |
H A D | WebAssemblyFrameLowering.cpp | 164 auto &MRI = MF.getRegInfo(); local 173 MRI.getTargetRegisterInfo()->getPointerRegClass(MF); 176 SPReg = MRI.createVirtualRegister(PtrRC); 186 Register BasePtr = MRI.createVirtualRegister(PtrRC); 193 Register OffsetReg = MRI.createVirtualRegister(PtrRC); 202 Register BitmaskReg = MRI.createVirtualRegister(PtrRC); 231 auto &MRI = MF.getRegInfo(); local 246 MRI.getTargetRegisterInfo()->getPointerRegClass(MF); 247 Register OffsetReg = MRI.createVirtualRegister(PtrRC); 252 SPReg = MRI [all...] |
H A D | WebAssemblyRegStackify.cpp | 99 MachineRegisterInfo &MRI, 105 const auto *RegClass = MRI.getRegClass(MI->getOperand(0).getReg()); 123 Register TempReg = MRI.createVirtualRegister(&WebAssembly::I32RegClass); 270 const MachineRegisterInfo &MRI, 272 // Most registers are in SSA form here so we try a quick MRI query first. 273 if (MachineInstr *Def = MRI.getUniqueVRegDef(Reg)) 276 // MRI doesn't know what the Def is. Try asking LIS. 287 static bool hasOneUse(unsigned Reg, MachineInstr *Def, MachineRegisterInfo &MRI, argument 289 // Most registers are in SSA form here so we try a quick MRI query first. 290 if (MRI 98 convertImplicitDefToConstZero(MachineInstr *MI, MachineRegisterInfo &MRI, const TargetInstrInfo *TII, MachineFunction &MF, LiveIntervals &LIS) argument 269 getVRegDef(unsigned Reg, const MachineInstr *Insert, const MachineRegisterInfo &MRI, const LiveIntervals &LIS) argument 316 isSafeToMove(const MachineInstr *Def, const MachineInstr *Insert, AliasAnalysis &AA, const MachineRegisterInfo &MRI) argument 400 oneUseDominatesOtherUses(unsigned Reg, const MachineOperand &OneUse, const MachineBasicBlock &MBB, const MachineRegisterInfo &MRI, const MachineDominatorTree &MDT, LiveIntervals &LIS, WebAssemblyFunctionInfo &MFI) argument 483 moveForSingleUse(unsigned Reg, MachineOperand &Op, MachineInstr *Def, MachineBasicBlock &MBB, MachineInstr *Insert, LiveIntervals &LIS, WebAssemblyFunctionInfo &MFI, MachineRegisterInfo &MRI) argument 528 rematerializeCheapDef( unsigned Reg, MachineOperand &Op, MachineInstr &Def, MachineBasicBlock &MBB, MachineBasicBlock::instr_iterator Insert, LiveIntervals &LIS, WebAssemblyFunctionInfo &MFI, MachineRegisterInfo &MRI, const WebAssemblyInstrInfo *TII, const WebAssemblyRegisterInfo *TRI) argument 596 moveAndTeeForMultiUse( unsigned Reg, MachineOperand &Op, MachineInstr *Def, MachineBasicBlock &MBB, MachineInstr *Insert, LiveIntervals &LIS, WebAssemblyFunctionInfo &MFI, MachineRegisterInfo &MRI, const WebAssemblyInstrInfo *TII) argument 774 MachineRegisterInfo &MRI = MF.getRegInfo(); local [all...] |
H A D | WebAssemblyAsmPrinter.h | 25 const MachineRegisterInfo *MRI; member in class:llvm::final 33 : AsmPrinter(TM, std::move(Streamer)), Subtarget(nullptr), MRI(nullptr), 51 MRI = &MF.getRegInfo();
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/freebsd-11-stable/contrib/llvm-project/llvm/lib/Target/Hexagon/ |
H A D | HexagonBitSimplify.cpp | 210 MachineRegisterInfo &MRI); 212 unsigned &Begin, unsigned &Width, MachineRegisterInfo &MRI); 214 unsigned NewSR, MachineRegisterInfo &MRI); 216 unsigned NewR, unsigned NewSR, MachineRegisterInfo &MRI); 219 const MachineRegisterInfo &MRI); 227 const BitTracker::RegisterRef &RR, MachineRegisterInfo &MRI); 229 const BitTracker::RegisterRef &RS, MachineRegisterInfo &MRI); 235 static bool hasTiedUse(unsigned Reg, MachineRegisterInfo &MRI, 356 MachineRegisterInfo &MRI) { 359 auto Begin = MRI [all...] |
/freebsd-11-stable/contrib/llvm-project/llvm/lib/Target/AArch64/ |
H A D | AArch64RegisterBankInfo.h | 118 bool hasFPConstraints(const MachineInstr &MI, const MachineRegisterInfo &MRI, 122 bool onlyUsesFP(const MachineInstr &MI, const MachineRegisterInfo &MRI, 126 bool onlyDefinesFP(const MachineInstr &MI, const MachineRegisterInfo &MRI,
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/freebsd-11-stable/contrib/llvm-project/llvm/lib/Target/ARM/MCTargetDesc/ |
H A D | ARMMCTargetDesc.h | 60 const MCRegisterInfo &MRI, 64 const MCRegisterInfo &MRI, 68 const MCRegisterInfo &MRI, 72 const MCRegisterInfo &MRI,
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/freebsd-11-stable/contrib/llvm-project/llvm/lib/Target/AVR/MCTargetDesc/ |
H A D | AVRInstPrinter.cpp | 90 MCRegisterInfo const &MRI) { 93 if (MRI.getNumSubRegIndices() > 0) { 94 unsigned RegLoNum = MRI.getSubReg(RegNum, AVR::sub_lo); 114 O << getPrettyRegisterName(Op.getReg(), MRI); 89 getPrettyRegisterName(unsigned RegNum, MCRegisterInfo const &MRI) argument
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