1//===-- ARMMCTargetDesc.h - ARM Target Descriptions -------------*- C++ -*-===//
2//
3// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
4// See https://llvm.org/LICENSE.txt for license information.
5// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
6//
7//===----------------------------------------------------------------------===//
8//
9// This file provides ARM specific target descriptions.
10//
11//===----------------------------------------------------------------------===//
12
13#ifndef LLVM_LIB_TARGET_ARM_MCTARGETDESC_ARMMCTARGETDESC_H
14#define LLVM_LIB_TARGET_ARM_MCTARGETDESC_ARMMCTARGETDESC_H
15
16#include "llvm/Support/DataTypes.h"
17#include "llvm/MC/MCInstrDesc.h"
18#include <memory>
19#include <string>
20
21namespace llvm {
22class formatted_raw_ostream;
23class MCAsmBackend;
24class MCCodeEmitter;
25class MCContext;
26class MCInstrInfo;
27class MCInstPrinter;
28class MCObjectTargetWriter;
29class MCObjectWriter;
30class MCRegisterInfo;
31class MCSubtargetInfo;
32class MCStreamer;
33class MCTargetOptions;
34class MCRelocationInfo;
35class MCTargetStreamer;
36class StringRef;
37class Target;
38class Triple;
39class raw_ostream;
40class raw_pwrite_stream;
41
42namespace ARM_MC {
43std::string ParseARMTriple(const Triple &TT, StringRef CPU);
44
45/// Create a ARM MCSubtargetInfo instance. This is exposed so Asm parser, etc.
46/// do not need to go through TargetRegistry.
47MCSubtargetInfo *createARMMCSubtargetInfo(const Triple &TT, StringRef CPU,
48                                          StringRef FS);
49}
50
51MCTargetStreamer *createARMNullTargetStreamer(MCStreamer &S);
52MCTargetStreamer *createARMTargetAsmStreamer(MCStreamer &S,
53                                             formatted_raw_ostream &OS,
54                                             MCInstPrinter *InstPrint,
55                                             bool isVerboseAsm);
56MCTargetStreamer *createARMObjectTargetStreamer(MCStreamer &S,
57                                                const MCSubtargetInfo &STI);
58
59MCCodeEmitter *createARMLEMCCodeEmitter(const MCInstrInfo &MCII,
60                                        const MCRegisterInfo &MRI,
61                                        MCContext &Ctx);
62
63MCCodeEmitter *createARMBEMCCodeEmitter(const MCInstrInfo &MCII,
64                                        const MCRegisterInfo &MRI,
65                                        MCContext &Ctx);
66
67MCAsmBackend *createARMLEAsmBackend(const Target &T, const MCSubtargetInfo &STI,
68                                    const MCRegisterInfo &MRI,
69                                    const MCTargetOptions &Options);
70
71MCAsmBackend *createARMBEAsmBackend(const Target &T, const MCSubtargetInfo &STI,
72                                    const MCRegisterInfo &MRI,
73                                    const MCTargetOptions &Options);
74
75// Construct a PE/COFF machine code streamer which will generate a PE/COFF
76// object file.
77MCStreamer *createARMWinCOFFStreamer(MCContext &Context,
78                                     std::unique_ptr<MCAsmBackend> &&MAB,
79                                     std::unique_ptr<MCObjectWriter> &&OW,
80                                     std::unique_ptr<MCCodeEmitter> &&Emitter,
81                                     bool RelaxAll,
82                                     bool IncrementalLinkerCompatible);
83
84/// Construct an ELF Mach-O object writer.
85std::unique_ptr<MCObjectTargetWriter> createARMELFObjectWriter(uint8_t OSABI);
86
87/// Construct an ARM Mach-O object writer.
88std::unique_ptr<MCObjectTargetWriter>
89createARMMachObjectWriter(bool Is64Bit, uint32_t CPUType,
90                          uint32_t CPUSubtype);
91
92/// Construct an ARM PE/COFF object writer.
93std::unique_ptr<MCObjectTargetWriter>
94createARMWinCOFFObjectWriter(bool Is64Bit);
95
96/// Construct ARM Mach-O relocation info.
97MCRelocationInfo *createARMMachORelocationInfo(MCContext &Ctx);
98
99namespace ARM {
100enum OperandType {
101  OPERAND_VPRED_R = MCOI::OPERAND_FIRST_TARGET,
102  OPERAND_VPRED_N,
103};
104inline bool isVpred(OperandType op) {
105  return op == OPERAND_VPRED_R || op == OPERAND_VPRED_N;
106}
107inline bool isVpred(uint8_t op) {
108  return isVpred(static_cast<OperandType>(op));
109}
110} // end namespace ARM
111
112} // End llvm namespace
113
114// Defines symbolic names for ARM registers.  This defines a mapping from
115// register name to register number.
116//
117#define GET_REGINFO_ENUM
118#include "ARMGenRegisterInfo.inc"
119
120// Defines symbolic names for the ARM instructions.
121//
122#define GET_INSTRINFO_ENUM
123#include "ARMGenInstrInfo.inc"
124
125#define GET_SUBTARGETINFO_ENUM
126#include "ARMGenSubtargetInfo.inc"
127
128#endif
129