1224133Sdim//===-- ARMMCTargetDesc.h - ARM Target Descriptions -------------*- C++ -*-===// 2224133Sdim// 3353358Sdim// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions. 4353358Sdim// See https://llvm.org/LICENSE.txt for license information. 5353358Sdim// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception 6224133Sdim// 7224133Sdim//===----------------------------------------------------------------------===// 8224133Sdim// 9224133Sdim// This file provides ARM specific target descriptions. 10224133Sdim// 11224133Sdim//===----------------------------------------------------------------------===// 12224133Sdim 13280031Sdim#ifndef LLVM_LIB_TARGET_ARM_MCTARGETDESC_ARMMCTARGETDESC_H 14280031Sdim#define LLVM_LIB_TARGET_ARM_MCTARGETDESC_ARMMCTARGETDESC_H 15224133Sdim 16226633Sdim#include "llvm/Support/DataTypes.h" 17353358Sdim#include "llvm/MC/MCInstrDesc.h" 18327952Sdim#include <memory> 19224133Sdim#include <string> 20224133Sdim 21224133Sdimnamespace llvm { 22261991Sdimclass formatted_raw_ostream; 23226633Sdimclass MCAsmBackend; 24226633Sdimclass MCCodeEmitter; 25226633Sdimclass MCContext; 26226633Sdimclass MCInstrInfo; 27261991Sdimclass MCInstPrinter; 28341825Sdimclass MCObjectTargetWriter; 29226633Sdimclass MCObjectWriter; 30239462Sdimclass MCRegisterInfo; 31224133Sdimclass MCSubtargetInfo; 32261991Sdimclass MCStreamer; 33314564Sdimclass MCTargetOptions; 34261991Sdimclass MCRelocationInfo; 35288943Sdimclass MCTargetStreamer; 36226633Sdimclass StringRef; 37224133Sdimclass Target; 38288943Sdimclass Triple; 39226633Sdimclass raw_ostream; 40288943Sdimclass raw_pwrite_stream; 41224133Sdim 42224133Sdimnamespace ARM_MC { 43288943Sdimstd::string ParseARMTriple(const Triple &TT, StringRef CPU); 44224133Sdim 45288943Sdim/// Create a ARM MCSubtargetInfo instance. This is exposed so Asm parser, etc. 46288943Sdim/// do not need to go through TargetRegistry. 47288943SdimMCSubtargetInfo *createARMMCSubtargetInfo(const Triple &TT, StringRef CPU, 48288943Sdim StringRef FS); 49224133Sdim} 50224133Sdim 51288943SdimMCTargetStreamer *createARMNullTargetStreamer(MCStreamer &S); 52288943SdimMCTargetStreamer *createARMTargetAsmStreamer(MCStreamer &S, 53288943Sdim formatted_raw_ostream &OS, 54288943Sdim MCInstPrinter *InstPrint, 55288943Sdim bool isVerboseAsm); 56288943SdimMCTargetStreamer *createARMObjectTargetStreamer(MCStreamer &S, 57288943Sdim const MCSubtargetInfo &STI); 58261991Sdim 59276479SdimMCCodeEmitter *createARMLEMCCodeEmitter(const MCInstrInfo &MCII, 60276479Sdim const MCRegisterInfo &MRI, 61276479Sdim MCContext &Ctx); 62276479Sdim 63276479SdimMCCodeEmitter *createARMBEMCCodeEmitter(const MCInstrInfo &MCII, 64276479Sdim const MCRegisterInfo &MRI, 65276479Sdim MCContext &Ctx); 66276479Sdim 67327952SdimMCAsmBackend *createARMLEAsmBackend(const Target &T, const MCSubtargetInfo &STI, 68327952Sdim const MCRegisterInfo &MRI, 69314564Sdim const MCTargetOptions &Options); 70226633Sdim 71327952SdimMCAsmBackend *createARMBEAsmBackend(const Target &T, const MCSubtargetInfo &STI, 72327952Sdim const MCRegisterInfo &MRI, 73314564Sdim const MCTargetOptions &Options); 74276479Sdim 75288943Sdim// Construct a PE/COFF machine code streamer which will generate a PE/COFF 76288943Sdim// object file. 77327952SdimMCStreamer *createARMWinCOFFStreamer(MCContext &Context, 78327952Sdim std::unique_ptr<MCAsmBackend> &&MAB, 79341825Sdim std::unique_ptr<MCObjectWriter> &&OW, 80327952Sdim std::unique_ptr<MCCodeEmitter> &&Emitter, 81327952Sdim bool RelaxAll, 82296417Sdim bool IncrementalLinkerCompatible); 83276479Sdim 84288943Sdim/// Construct an ELF Mach-O object writer. 85341825Sdimstd::unique_ptr<MCObjectTargetWriter> createARMELFObjectWriter(uint8_t OSABI); 86234353Sdim 87288943Sdim/// Construct an ARM Mach-O object writer. 88341825Sdimstd::unique_ptr<MCObjectTargetWriter> 89341825SdimcreateARMMachObjectWriter(bool Is64Bit, uint32_t CPUType, 90341825Sdim uint32_t CPUSubtype); 91226633Sdim 92288943Sdim/// Construct an ARM PE/COFF object writer. 93341825Sdimstd::unique_ptr<MCObjectTargetWriter> 94341825SdimcreateARMWinCOFFObjectWriter(bool Is64Bit); 95261991Sdim 96288943Sdim/// Construct ARM Mach-O relocation info. 97261991SdimMCRelocationInfo *createARMMachORelocationInfo(MCContext &Ctx); 98353358Sdim 99353358Sdimnamespace ARM { 100353358Sdimenum OperandType { 101353358Sdim OPERAND_VPRED_R = MCOI::OPERAND_FIRST_TARGET, 102353358Sdim OPERAND_VPRED_N, 103353358Sdim}; 104353358Sdiminline bool isVpred(OperandType op) { 105353358Sdim return op == OPERAND_VPRED_R || op == OPERAND_VPRED_N; 106353358Sdim} 107353358Sdiminline bool isVpred(uint8_t op) { 108353358Sdim return isVpred(static_cast<OperandType>(op)); 109353358Sdim} 110353358Sdim} // end namespace ARM 111353358Sdim 112224133Sdim} // End llvm namespace 113224133Sdim 114224133Sdim// Defines symbolic names for ARM registers. This defines a mapping from 115224133Sdim// register name to register number. 116224133Sdim// 117224133Sdim#define GET_REGINFO_ENUM 118224133Sdim#include "ARMGenRegisterInfo.inc" 119224133Sdim 120224133Sdim// Defines symbolic names for the ARM instructions. 121224133Sdim// 122224133Sdim#define GET_INSTRINFO_ENUM 123224133Sdim#include "ARMGenInstrInfo.inc" 124224133Sdim 125224133Sdim#define GET_SUBTARGETINFO_ENUM 126224133Sdim#include "ARMGenSubtargetInfo.inc" 127224133Sdim 128224133Sdim#endif 129